TWI556449B - 具有富鍺裝置層及摻雜轉移層的半導體裝置、半導體裝置堆疊及其製造方法 - Google Patents

具有富鍺裝置層及摻雜轉移層的半導體裝置、半導體裝置堆疊及其製造方法 Download PDF

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TWI556449B
TWI556449B TW104131636A TW104131636A TWI556449B TW I556449 B TWI556449 B TW I556449B TW 104131636 A TW104131636 A TW 104131636A TW 104131636 A TW104131636 A TW 104131636A TW I556449 B TWI556449 B TW I556449B
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layer
sige
semiconductor
stack
rich
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TW201611291A (zh
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威利 瑞奇曼第
凡 雷
拉維 皮拉瑞斯提
潔西卡 卡琴恩
馬克 法藍奇
亞倫 布德里維奇
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英特爾股份有限公司
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Description

具有富鍺裝置層及摻雜轉移層的半導體裝置、半導體裝置堆疊及其製造方法
本發明之實施例係於半導體裝置的領域，更明確地說，具有鍺(Ge)主動層的半導體裝置。
過去幾十年以來，積體電路的縮放特性已經促成了半導體晶片上的功能單元的密度增加。例如，收縮電晶體尺寸允許增加數量的記憶體裝置被加入一晶片上，造成具有增加容量的產品的製造。
在積體電路裝置的場效電晶體(FET)的製造中，矽以外的半導電結晶材料為有利的。此一例材料的例子為Ge，其相對於矽提供若干可能較佳特性，例如但並不限於高電荷載體(電洞)遷移率、帶隙偏移、不同晶格常數、及與矽作成合金以形成SiGe的半導電二元合金的能力。
在現今電晶體設計中，使用Ge的一個問題為現對於矽FET逐年逐步縮小所完成的極端細微特性(例 如，22nm及以下)現在對Ge很難完成，當以較不逐步縮小形式實施時，經常使得可能材料為主的效能增益白費。縮小的困難度係有關於Ge的材料特性，更明確地說，有關於蝕刻SiGe的困難度，SiGe經常被使用作為在Ge主動層(例如電晶體通道層)及下層矽基材材料間之中間層，對Ge有足夠選擇性，以移除SiGe，而不會腐蝕細微列印的Ge主動層特性。
材料堆疊架構及完成高SiGe：Ge蝕刻選擇性的蝕刻技術因此有利的。
100‧‧‧半導體層堆疊
104‧‧‧基板
106‧‧‧SiGe緩衝層堆疊
106A‧‧‧第一層
106B‧‧‧第二層
107‧‧‧轉移層堆疊
107A‧‧‧n-型摻雜SiGe層
107A’‧‧‧間隔層
107B‧‧‧p-型摻雜SiGe層
107C‧‧‧半導體層
108‧‧‧富Ge裝置層堆疊
108A‧‧‧富Ge裝置層
204‧‧‧基板
206A‧‧‧SiGe緩衝層
206B‧‧‧SiGe緩衝層
207A‧‧‧轉移層
207B‧‧‧轉移層
207C‧‧‧轉移層
208A‧‧‧裝置層
208B‧‧‧裝置層
209A‧‧‧犧牲層
209B‧‧‧犧牲層
250‧‧‧側壁
260‧‧‧溝渠
300‧‧‧半導體裝置
304‧‧‧基板
305‧‧‧閘極堆疊
305A‧‧‧閘極介電層
305B‧‧‧閘極電極
307A‧‧‧洩漏抑制層
307B‧‧‧p-型Ge蝕刻抑制層
307C‧‧‧轉移層
308A‧‧‧鍺裝置層
318‧‧‧介電間隔層
320‧‧‧凹陷區域
400‧‧‧半導體裝置
404‧‧‧基板
405‧‧‧閘極堆疊
406‧‧‧緩衝層
407A‧‧‧n-型洩漏抑制層
407B‧‧‧p-型層
407C‧‧‧轉移層
408A‧‧‧裝置體
418‧‧‧介電間隔層
420‧‧‧隔離區域
422‧‧‧凹陷區域
424‧‧‧汲極區域
500‧‧‧半導體
504‧‧‧基板
505‧‧‧閘極堆疊
506‧‧‧通道區域
507A‧‧‧接面洩漏抑制層
507B‧‧‧Ge蝕刻抑制層
507C‧‧‧SiGe轉移層
508‧‧‧堆疊鍺奈米線
508A‧‧‧奈米線
508B‧‧‧奈米線
510‧‧‧源極區域
512‧‧‧汲極區域
514‧‧‧接觸
516‧‧‧間隔層
604‧‧‧基板
607A‧‧‧n-型摻雜層
607B‧‧‧p-型摻雜層
607C‧‧‧轉移層
608A’‧‧‧富Ge裝置層
608B’‧‧‧富Ge裝置層
609A’‧‧‧富矽材料層
609B’‧‧‧富矽材料層
612‧‧‧鰭型結構
614A‧‧‧犧牲閘極
614B‧‧‧犧牲閘極
614C‧‧‧犧牲閘極
616‧‧‧犧牲閘極氧化物層
618‧‧‧犧牲多晶矽閘極層
620‧‧‧區域
622‧‧‧間隔層
624‧‧‧層間介電層
626‧‧‧溝渠
608A‧‧‧奈米線
608B‧‧‧奈米線
700‧‧‧計算裝置
702‧‧‧板
704‧‧‧處理器
706‧‧‧通訊晶片
圖1A例示依據本發明實施例之半導體層堆疊的剖面圖，其包含配置於差量(delta)摻雜p-型轉移層之上的鍺裝置層；圖1B例示依據本發明實施例之半導體層堆疊的摻雜物濃度深度分佈圖，其包含有差量摻雜p-型轉移層；圖2A及2B例示依據本發明實施例之在圖2A所繪之半導體層堆疊的本地生長的剖面圖；圖3A及3B例示依據本發明之另一實施例之採用圖1A的半導體堆疊的平面半導體裝置的製造剖面圖；圖4A-4C例示依據本發明實施例之製造採用圖1A的半導體堆疊的非平面半導體裝置的方法中之各種 操作斜角圖；圖5A例示依據本發明實施例之採用圖1A的半導體堆疊的奈米線或奈米帶半導體裝置的等角剖面視圖；圖5B例示依據本發明實施例之圖5A的奈米線為主半導體結構的剖面通道圖；圖5C例示依據本發明實施例之圖5A的奈米線為主半導體結構的剖面圖；圖6A-6D例示依據本發明實施例，代表在製程中至少具有一點具有鍺裝置層配置於p-摻雜轉移層之上的奈米線半導體裝置的製造方法中的各種操作的等角剖面視圖；及圖7例示依據本發明實施法的計算裝置。
【發明內容及實施方式】
於此描述具有富Ge主動層配置於摻雜半導體轉移層上的半導體裝置。於以下說明中，各種細節係被說明。然而，對於熟習於本技藝者明顯地本發明可以在沒有這些細節下實施。在一些例子中，已知方法與裝置係以方塊圖形式顯示，而不是詳細顯示，以避免模糊本發明。於本說明書中之提之“實施例”表示有關該實施例所述之特定特性、結構、功能、或特徵係被包含在本發明的至少一實施例中。因此，在說明書各處出現的“在實施例中”用語並不必然表示本發明之同一實施例。再者，特定特性、結 構、功能或特徵可以在一或更多實施例中，以任何適當方式加以組合。例如，只要第一實施例不排斥第二實施例，兩實施例可以任意組合。
用語“耦接”及“連接”及其衍生用語在此可以被用以描述兩元件間之結構關係。應了解的是，這些用語並不是彼此同義。相反地，在特定實施例中，“連接”可以用以表示兩或更多元件以直接實體或電彼此接觸。“耦接”可以用以表示兩或更多元件係直接或間接(其間有其他中介元件)實體或電彼此接觸，及/或兩或更多元件彼此配合或互動(例如，造成一作動關係)。
於此所用之用語“在..上方”、“在...之下”、“在..之間”及“在...上”為一材料層或元件與其他層或元件的相對位置。例如，一層配置在另一層之上(上方)或下可能直接接觸該另一層或可以具有一或更多中介層。再者，配置於兩層間之一層可以直接接觸該兩層或可以具有一或更多中介層。相反地，第一層在第二層上為直接接觸該第二層。類似地，除非特別說明，否則，配置在兩特性間之一特性可以為直接接觸相鄰特性或者也可以具有一或更多中介特性。
於此所描述之一或更多實施例利用矽上有鍺(Ge-on-Si)基板裝置架構，其更利用一轉移層配置於富Ge裝置層與Si基板之間，轉移層被摻雜以改良富Ge裝置層對蝕刻劑的阻抗，該蝕刻劑被用以移除較裝置層相對為少的Ge構成的裝置堆疊的其他半導體層。
在實施例中，p-型摻雜半導體轉移層係配置於富Ge裝置層與Si基板之間。此等配置可以被利用以形成鍺為主電晶體作為平面裝置、鰭或三閘為主的裝置、及全周閘裝置(例如奈米線裝置)。更明確地說，一或更多實施例係有關於執行矩形的含Ge奈米線或奈米帶由Ge/SiGe、Ge/Si、SiGe/SiGe、或SiGe/Si多層堆疊的釋放。
於此所述之一或更多實施例利用p-型差量摻雜(δ-doped)埋入半導體層，以加強在上層富Ge裝置層對某些有用於由半導體裝置堆疊移除其他材料的濕蝕刻劑的阻抗，半導體裝置堆疊例如具有相對低Ge含量(即，矽含量富於該裝置層)的一或更多SiGe(或純Si)層，藉以改良對純Ge的裝置層或對Ge中的SiGe較富的裝置層蝕刻製程選擇性。在實施例中，p-型摻雜埋入層的出現已經被發現為改良富Ge裝置層對在Ge裝置層底切及/或釋放製程(例如，用於全周閘或奈米線/奈米帶裝置)時所用之對SiGe的濕蝕刻劑的阻抗，藉以保留細微富Ge奈米線幾何。
發明人發現對於某些對於在曝露Ge層(或相對地Ge較富的SiGe層)的表面原子氧化狀態靈敏的濕蝕刻劑，Ge的溶解可能隨著埋入p-型摻雜半導體層的引入半導體膜堆疊中而劇烈地減少。雖然未為理論所約束，但現已經至少部份歸因於富Ge裝置層與埋入p-型摻雜層間之以電荷的電流耦合及在富Ge裝置層內的電子裝態為在 p-型摻雜埋入層所調變，而改良富Ge裝置層的蝕刻阻抗，藉以改變影響Ge溶解的電流處理。其中，在富Ge裝置層間之材料層係曝露至蝕刻劑以及埋入p-型摻雜層未摻雜(即本徵摻雜濃度)，但p-型摻雜層可以設定回到裝置層之下(例如，50-100nm，或更多)，並例如當曝露至SiGe的濕蝕刻劑時，仍抑制上層富Ge半導體裝置層的蝕刻。
在一或更多實施例中，p-型差量摻雜埋入層係被配置於半導體裝置堆疊的n-型次通道洩漏抑制層(也可是差量摻雜層的)之上。其中，p-型摻雜層係配置於n-型摻雜洩漏抑制層之上，摻雜材料板可以形成摻雜雙極。有關於由摻雜雙極造成的導帶不連續性的整流特性也可以在觀察Ge蝕刻抑制中扮演一角色。以在富Ge裝置層與埋入p-型摻雜層間之材料層未摻雜(例如，本徵)，Ge蝕刻抑制也可以以差量摻雜的p-型摻雜層完成，其具有一摻雜物濃度，其確保行動電荷係為下層的n-型摻雜洩漏抑制層所完全空乏，使得p-型摻雜層的出現並不會有害地增加於FET裝置的源極與汲極間之次通道洩漏。在實施例中，p-型差量摻雜埋入層可以在熱處理時(例如，在選擇地蝕刻在Ge之上的SiGe之後)，進行遷移/擴散及發散至多於15nm，但並不會完全補償在洩漏抑制層中之n-型摻雜物，以完成在製造時的Ge蝕刻抑制及抑制在完成FET裝置中之洩漏。
圖1A中顯示依據本發明實施例的半導體層堆 疊100的剖面圖，其包含Ge裝置層配置於差量摻雜轉移層上。如所示，半導體裝置堆疊100包含鍺(Ge)為主裝置層堆疊108(例如壓縮應變鍺層)成長於矽(Si)基板104(例如，矽晶圓的一部份)之上。
基板104可以由任何半導體材料構成，其可以忍受製造並作為在堆疊100中之半導體層的長晶時的種層。在實施例中，基板104為單體基板，例如，P-型矽基板，如同於半導體工業中所常用者。在實施例中，基板104由結晶矽、矽/鍺或摻雜有帶電載體的鍺層構成，載體例如但並不限於磷、砷、硼、或其組合。在一實施例中，在基板104中矽原子的濃度為大於97%，或者，也可以，摻雜原子的濃度低於1%。在另一實施例中，基板104係由成長於個別結晶基板上的磊晶層，例如，成長於摻硼單體矽單晶基板上的矽磊晶層所構成。基板104也可以包含絕緣層配置於單體結晶基板與磊晶層之間，以例如形成絕緣層有矽基板。在實施例中，絕緣層由例如但並不限於二氧化矽、氮化矽、氧氮化矽或高-k介電層的材料構成。基板104也可以由III-V族材料構成。在一實施例中，基板104係例如但並不限於氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、砷化銦鎵、砷化鋁鎵、磷化銦鎵、或其組合的III-V材料構成。在另一實施例中，基板104由III-V材料及例如但並不限於碳、矽、鍺、氧、硫、硒或碲的電荷載體摻雜雜質原子構成。
富Ge裝置層堆疊108可以包含一或更多Ge 裝置層，具有只有如圖1A所示之第一富Ge裝置層108A。在例示實施例中，富Ge裝置層108A的厚度範圍為5-15nm並主要由純Ge(即，可以有一些本徵等級雜質)構成。分佈於Si基板104與富Ge裝置層堆疊108間的是矽鍺(SiGe)緩衝層堆疊106(例如，更包含大約0.5-1μm的Si0.7Ge0.3的第一層106A，及由大約0.3-1μm的Si0.3Ge0.7構成的第二層106B)，以容許於Ge與Si間之熱及/或晶格失配。或者，緩衝層堆疊106也可以包含具有漸變Ge組成物(例如，由30%至70%)的SiGe，或者，具有變化Ge濃度的多層SiGe，或這些各種類型緩衝層結構的任意組合。在例示實施例中，緩衝層堆疊106係立即配於或直接在Si基板204之上，並具有轉移層堆疊107立即配在緩衝層堆疊106上或之上，並也在該Si基板104與該裝置層堆疊108之間。
轉移層堆疊107包含n-型摻雜SiGe層107A(例如，一層鬆弛摻磷Si0.3Ge0.7)。在例示實施例中，n-型摻雜SiGe層107A具有5-20nm的厚度，及範圍1e17-1e19原子/立方公分的摻雜物濃度，較佳係至少1e18cm-3。因為磷及其他n-型摻雜，例如，砷係快速擴散於SiGe及Ge中，所以n-型摻雜SiGe層107A由Ge裝置層堆疊108後移，以減少N-型摻雜物進入Ge裝置層堆疊108中。例如，n-型摻雜SiGe層107A可以為在Ge裝置層108下25-100nm，例如為由鬆弛本徵Si0.3Ge0.7構成的半導體層107C所分開。或者，為進一步改良短通道效應，及/或洩 漏，在裝置層108在“關斷”或非導通狀態時，半導體層107C可以(或除了本徵Si0.3Ge0.7厚度外，進一步包含)為相對低濃度鍺(例如，<7%Ge)的未摻雜Si或SiGe層作為加強擴散阻障。因此，半導體層107A的總厚度可以相當大地改變。
轉移層堆疊107更包含p-型摻雜SiGe層107B(例如，一層鬆弛Si0.3Ge0.7)。在例示實施例中，p-型摻雜SiGe層107B為差量摻雜層，近似片電荷的2-D板。在此等實施例中，p-型摻雜SiGe層107B具有5-15nm的厚度，可以在轉移層堆疊107的磊晶成長時透過原處摻雜加以完成。也可能有更大厚度，只要限制為不完全補償n-型摻雜層107A。在例示實施例中，p-型摻雜SiGe層107B具有於5e17及1e19cm-3間，較佳至少1e18cm-3的摻雜。在例示實施例中，p-型摻雜物種為硼，但也可以預期到其他p-型摻雜物種以類似地執行。
圖1B例示依據本發明實施例之包含差量摻雜p-型SiGe轉移層，例如層107B的半導體層堆疊的摻雜濃度深度分佈圖，該轉移層係配置於例如SiGe層107A的n-型摻雜洩漏抑制層之上。所示摻雜物濃度深度分佈圖代表相反於“已退火”狀態的半導體堆疊的“成長”狀態。如圖1B所示，摻硼SiGe轉移層具有超出2e18cm-3的硼濃度及大約至少1e18cm-3的差量摻雜在標示為“107B”的約15nm深度間隔之上。磷摻雜到達大約1e18cm-3間隔標示為“107A”的深度對應於該SiGe轉移層n-型摻雜洩漏抑制 層。如於圖1B所示，摻磷層107A具有大於摻硼層107B為厚的厚度並較摻硼層107B更有階級(即，未差量摻雜)。
在實施例中，p-型SiGe轉移層係與下層n-型SiGe轉移層分隔開非故意摻雜(例如，本徵摻雜)SiGe層。此間隔層在圖1A中被標示為107A’，且為最小厚度(例如，2-5nm)，其係取決於成長速率動力學及成長室切換於n-型及p-型摻雜物間的快速性。間隔層107A’為SiGe(例如，Si0.3Ge0.7)，其係在n-型摻雜物終止後及在P-型摻雜物引入之前成長。間隔層107A’的有效摻雜係被例示於圖1B的實施例中，其中，硼及磷摻雜位準係低於5e17cm-3。在實施例中，間隔層107A’具有2-5nm的厚度。對於在此範圍上限的實施例，層107A、107A’及107B可以特徵為p-i-n差量摻雜結構，其中至少該p-型層為差量摻雜層。
取決於實施例，半導體堆疊100可以為“全面”膜堆疊，配置於基板的整個表面上(例如圖1A中之基板104代表整個晶圓)，或者“局部”膜堆疊，其係只有配置於基板的某部份(例如，圖1A中之基板104代表晶圓的小部份)。在任一實施例中，半導體堆疊100可以被已知適用於SiGe材料的磊晶技術所形成，例如，但並不限於CVD及分子束磊晶(MBE)。如於此所用，“磊晶”層係對準種表面(例如，由於晶種表面的結晶性，而具有較佳結晶取向)。圖2A及2B例示一局部成長實施例的剖 面圖，其中描繪於圖1A的半導體層堆疊係以縱深比陷(ART)的優點加以成長。
如於圖2A所示，隔離介電質具有定義溝渠260的側壁250，其具有半導體種面曝露於溝渠的底部。如於圖2B所示，結晶半導體的局部及選擇性磊晶成長形成SiGe緩衝層206B(例如，具有層106A所述之特性)於SiGe緩衝層206A(例如，具有層106A所述之特性)上，該層206A係配置在基板204(例如，具有基板104所述之特性)上。配置在溝渠260中的是轉移層207A、207B、及207C(例如，分別具有層107A、107B及107C所述之特性)，及裝置層208A及208B具有中介犧牲層209A及209B。在例示實施例中，犧牲層209A及209B各個為SiGe層並各個具有相同組成。在有利實施例中，在犧牲層209A、209B中之Ge濃度係低於在轉移層中者(例如，<70%Ge)，以相對於轉移層207C具有想要的應變位準(例如，1-1.5%)。在一實施例中，裝置層208A及208B均為基本上純Ge。在另一實施例中，裝置層208A及208B各個為SiGe組成，其在Ge中較犧牲層209A、209B為富，犧牲層為SiGe合金或也可以為矽。
圖3A及3B例示利用半導體堆疊100的平面半導體裝置實施例的剖面視圖。首先，參考圖3B，半導體裝置300包含閘極堆疊305配置在基板304之上。富Ge裝置層308A係配置於基板304之上、在閘極堆疊305之下。通常，半導體裝置300可以為任意半導體裝置，其 合併閘極、通道區域、及一對源/汲極區域，例如，但並不限於為MOS-FET。在例示實施例中，裝置300為作為在CMOS積體電路內的互補電晶體類型之一的PMOS FET。
在例示實施例中，富Ge裝置層308A基本上為純Ge，被壓縮應變1-2%。SiGe轉移層307C係配置於基板304之上，及在鍺主動層308A之下。n-型接面洩漏抑制層307A係安置於基板304之上，具有p-型Ge蝕刻抑制層307B配置於轉移層307C與洩漏抑制層307A之間，如同於堆疊100的文中所述。在例示PMOS實施例中，上升源極及汲極區域322係被沈積或成長重摻雜p-型(例如，硼)及配置於接面洩漏抑制層307A之上，在閘極堆疊305的兩側上。源極汲極區域322可以形成具有n-型洩漏抑制層307A的p+/n接面，或者，沒有洩漏抑制層(例如，源極/汲極區域322配置在轉移層307C的上部份上)。
在圖3A所示之實施例中，閘極堆疊305係直接配置於Ge主動層308A上，鍺裝置層308A係直接配置於未摻雜SiGe轉移層307C上，轉移層307C係直接配置於p-型轉移層307B上，p-型轉移層307B係直接配置於接面洩漏抑制層307A上(其間只有例如107A’的SiGe間隔層)。
如於圖3A所示，閘極堆疊305可以包含直接配置於閘極介電層305A之上的閘極電極305B。在實施例 中，閘極電極305B係由金屬閘極構成及閘極介電層305A係由高-K材料構成。例如，在一實施例中，閘極介電層305A係由例如但並不限定於氧化鉿、氧氮化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅、或其組合的材料所構成。再者，閘極介電層305A的部份可以包含一層由富Ge裝置層308A的上方幾層所形成的一層本地氧化物。在實施例中，閘極介電層305A係由半導體材料的氧化物所構成的一頂高-k部份及較大部份所構成。在一實施例中，閘極介電層305A係由氧化鉿的頂部份及二氧化矽或氧氮化矽的底部份所構成。
在實施例中，閘極電極305B係例如但並不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳、或導電金屬氧化物的金屬層所構成。在特定實施例中，閘極電極305B係由形成在金屬功函數設定層上的非功函數設定填料所構成。在實施例中，閘極電極305B係由P-型材料構成。閘極堆疊305也可以包含介電間隔層318，如圖3A所示。
如於圖3B所示，源極及汲極區域322係“嵌入”或“上升”替換源極及汲極區。圖3A更例示在製造裝置300時的剖面視圖。參考圖3A，富Ge裝置層308A的部份及在例示實施例中之頂轉移層307C的部份，甚至p-型轉移層307B的部份係被移除，以在閘極堆疊305的兩側 上，提供凹陷區域320。凹陷區域320也可以藉由例如乾蝕刻或濕蝕刻製程之任何適當技術，移除裝置層308A等的部份加以形成。在一實施例中，凹陷區域320的至少一部份係被以對富Ge裝置層308A的氧化狀態靈敏的濕蝕刻劑形成，其例如但並不限於含水氫氧化物化學品，如氫氧化銨(NH4OH)、氫氧化鉀(KOH)、氫氧化四甲銨(TMAH)、或其他氫氧化四烷基銨。在一實施例中，區域320的第一凹陷必然有乾電漿蝕刻，以使用NF3、HBr、SF6、或Cl2界定富Ge裝置層308A，而區域320的第二凹陷必然有使用含水氫氧化物化學品的濕蝕刻SiGe轉移層307C。p-型轉移層307B的出現係有利於凹陷區域320的形成，例如，允許第一蝕刻富Ge裝置層308A，隨後，SiGe蝕刻頂轉移層307C，這係對於富Ge裝置層308A(例如，純Ge)有高選擇性(接近無限)。因此，源極、汲極區域中接近裝置通道末端的尖端可以被以高精準度形成，以允許FET的閘極長度(Lg)的縮放。在一實施例中，閘極堆疊305導引凹陷區域320的形成(即，自對準凹陷區域320)。在一實施例中，如圖3B所示，凹陷區域320係形成有圓化轉角。然而，在另一實施例中，凹陷區域320係被形成有小刻面轉角。在實施例中，n-型洩漏抑制層307A作動為在形成凹陷區域320中之蝕刻停止層。再次參考圖3B，一對嵌入源極、汲極區域322係被磊晶形成在凹陷區域320中，或不是磊晶方式形成在凹陷區域320中。在實施例中，源極、汲極區域322係被單 軸壓縮應變該富Ge裝置層308並由具有晶格常數大於鍺的材料所構成，例如具有晶格常數大於鍺的III-V族材料。
如上所述，本發明的實施例可以應用至非平面MOS-FET。例如，具有三維架構的裝置，例如，三閘極裝置可以由包含埋入p-型轉移層的半導體裝置堆疊得利。圖4A-4C例示依據本發明實施例之代表利用圖1A的半導體堆疊製造非平面半導體裝置的方法的各種操作的斜角視圖。
通常，非平面FET實施例可以藉由使鰭被形成在富Ge裝置層中，而由埋入p-型Ge蝕刻抑制層中得利，該鰭為很細側向尺寸(例如，<22nm)。在形成富Ge鰭後，SiGe的周圍及/或下層區域可以以對富Ge鰭結構基本上無限大選擇性進行蝕刻，使得通道長度及/或源/汲極尖端、及/或次通道下特性尺寸可以以沿著富Ge結構形成的化學尖銳介面加以良好控制。
參考圖4A，半導體裝置400包含配置在基板404上的閘極堆疊405。三維富Ge裝置體408A係配置於基板404上及在閘極堆疊405之下。隔離區域420係配置於基板404之上，具有三維裝置體408A由該處延伸(裝置體與隔離區域420同平面也是可能)。頂轉移層407C係配置於基板404之上，在三維富鍺裝置體408A之下。 Ge蝕刻抑制層407B係配置於頂轉移層407C之下並具有至少一部份於說明書其他部份所述裝置堆疊100(圖1) 的層107B的文中所述之特性。層407B係配置於接面洩漏抑制層407C之上，該抑制層係配置於緩衝層406與基板404之上。在裝置400中之所有半導體層的材料組成與尺寸係相同或類似於半導體裝置300所述者，因為兩裝置實施例利用半導體堆疊100。
在一實施例中，隔離區域420及/或為隔離區域420所包圍的非平面半導體裝置堆疊的至少一部份係為濕蝕刻劑所形成，該蝕刻係對富Ge裝置層408A的氧化狀態靈敏，蝕刻劑係例如但並不限於於此說明書中之其他部份所述之含水氫氧化物化學品(TMAH等)。在一實施例中，形成隔離區域420的半導體裝置堆疊(例如堆疊100)的第一蝕刻必然產生乾電漿蝕刻，例如但並不限於NF3、HBr、SF6或Cl2。例如，為乾蝕刻所曝露的半導體堆疊的乾蝕刻側壁的第二蝕刻必然產生使用含水氫氧化物化學品的SiGe轉移層307C的濕蝕刻。或者，或額外地，相對於非平面半導體主體的隔離區域420的凹陷可以包含靈敏於富Ge裝置層408A的氧化狀態的濕式蝕刻，例如但並不限於本說明書中之其他部份所述之含水氫氧化物化學品(TMAH等)。在任一狀況中，p-型轉移層307B的出現使得頂轉移層307C的SiGe蝕刻，其係對富Ge裝置層308A(例如，純Ge)高度靈敏(接近無限大)。
裝置體408A未置於閘極堆疊405(及周圍介電間隔層418)之下的部份係為摻雜的源極與汲極區域。依據本發明之實施例，如圖4A所示，隔離區域420係下 凹至三維富Ge(例如純Ge)裝置體408A與頂轉移層407C(例如Si0.3Ge0.7)之介面。然而，其他實施例也可以包含設定隔離區域420的高度高於或低於此特定界面。
在一實施例中，源極與汲極區域係藉由摻雜(例如，p-型)三維鍺主動體406中未為閘極堆疊405所覆蓋的部份所形成。轉移層407C的部份也可以是p-型摻雜源極與汲極區，以p-型摻雜物一路延伸進入p-型層407B，以在非平面裝置主體的相對端上形成具有n-型洩漏抑制層407A的p+/n二極體。然而，在另一實施例中，源極與汲極區域係為嵌入源極及汲極區域。例如，圖4B及4C顯示依據本發明另一實施例之在製造另一半導體裝置時的剖面視圖，其具有下層擴散阻障層的富Ge裝置層。
參考圖4B，三維富Ge體408A部份、及可能轉移層407C與p-型轉移層407B的部份係被移除，以在閘極堆疊405的兩側上提供凹陷區域422。凹陷區域422可以藉由任何適當移除三維富Ge裝置層408A等的部份之技術形成，該技術例如乾蝕刻或濕蝕刻製程。在一實施例中，凹陷區域422的至少一部份係以對富Ge裝置層408A的氧化狀態靈敏的濕蝕刻劑形成，其係於本說明書中之其他部份中所述之含水氫氧化物化學品(TMAH等)。在一實施例中，區域422的第一凹陷必然發生乾電漿蝕刻，以使用NF3、HBr、SF6或Cl2界定富Ge裝置層408A，而區域422的第二凹陷必然發生使用NH4OH或 TMAH或類似物的濕蝕刻劑。p-型轉移層407B的出現係有利於形成凹陷區域422，例如，允許第一蝕刻富Ge裝置層408A，隨後SiGe蝕刻轉移層407C，其係對富Ge裝置層408A(例如，純Ge)高選擇性(近無限大)。因此，源極、汲極區域的尖端可以以高精準度形成，允許FET的閘極長度(Lg)的縮放。在一實施例中，閘極堆疊405導引凹陷區域422的形成，形成自對準凹陷區域422。在實施例中，n-型洩漏抑制層407A作為在形成凹陷區域422時的蝕刻停止。
參考圖4C，一對上升源極、汲極區域424係被磊晶或非磊晶形成在凹陷區域422中。在實施例中，源極、汲極區域424係單軸壓縮應變該富Ge裝置層408A並由具有晶格常數大於鍺的材料構成，例如，具有晶格常數大於鍺的III-V材料。
圖5A例示依據本發明實施例之利用圖1A的半導體堆疊的奈米線或奈米帶半導體裝置的等角剖面圖。圖5B顯示依據本發明實施例之圖5A的奈米線為主半導體結構的剖面通道圖。圖5C顯示依據本發明實施例之圖5A的奈米線為主半導體結構的剖面視圖。
首先，參考圖5A，半導體裝置500包含一或更多垂直對準或堆疊的鍺奈米線(508組)，配置於基板504上。於此實施例包含單線裝置或多線裝置。例如，具有奈米線508A、508B的兩奈米線為主裝置係被以例示目的加以顯示。為了方便說明起見，奈米線508A係被使用 作為例子，其中說明只針對在組508中之奈米線之一條。應了解的是，於此所述一奈米線的屬性，根據多數奈米線的實施例也可以具有與各個奈米線相同的屬性。
各個富Ge(例如，純Ge)奈米線508包含通道區域506配置於奈米線中。通道區域506具有長度(L)。參考圖5B，通道區域也具有正交於長度(L)的周圍。參考圖5A及5B，閘極堆疊505包圍各個通道區域506的整個周圍。閘極堆疊505包含沿著在通道區域506與閘極電極(未個別顯示)間配置的閘極介電層的閘極電極。通道區域506為分立的，其完全為閘極堆疊505所包圍，而沒有任何中介材料，例如，下層基板材料(例如參考堆疊100的轉移層107C)或其他犧牲通道製造材料間隔開富Ge奈米線508。因此，在具有多數奈米線508的實施例中，奈米線的通道區域506也彼此相互分離，如圖5B所示。接面洩漏抑層507A係配置於基板504上，在該一或更多鍺奈米線508之下。閘極堆疊505係配置於n-型洩漏抑制層507A之上，並可以如所示在SiGe轉移層507C之上。雖然未顯示，但在一實施例中，緩衝層也可以直接配置於基板504與該接面洩漏抑制層507A之間，其大致如同裝置堆疊100的文所述。
再次參考圖5A，各個奈米線508也包含源極與汲極區域510及512配置於奈米線中在通道區域506的兩側。如所示，源極與汲極區域510/512係配置在SiGe轉移層507C上。在實施例中，源極及汲極區域510/512 為替換源極及汲極區域，例如，奈米線的至少一部份被移除並以一源極/汲極材料區域替換。然而，在另一實施例中，源極及汲極區域510/512係由一或更多鍺奈米線508的只被(以例如硼佈植物等)摻雜的部份所構成。
一對接觸514(在圖5A中之虛線)係配置在源/汲極區域510/512之上。在實施例中，半導體裝置500更包含一對間隔層516(圖5A中之虛線)。間隔層516係配置於閘堆疊505及該對接觸514之間。如上所述，在至少幾個實施例中，通道區域及源/汲極區域係作成分立。然而，並非奈米線508的所有區域均需要分立。例如，參考圖5C，奈米線508A-508B在位於間隔層516下的位置並非分立。在一實施例中，奈米線508A-508B的堆疊具有中介犧牲半導體材料於其間(509B)，及在之下(509A)，其可以SiGe(例如具有較轉移層107C為低之Ge濃度)，或矽。在一實施例中，底奈米線508A係仍與例如用於如下所述製程的轉移層507C的部份接觸。
在實施例中，如於本說明書其他部份所述之用於裝置堆疊100，一或更多富Ge奈米線508係基本上由鍺構成，轉移層507C為Si0.3Ge0.7，p-型Ge蝕刻抑制層507B為p-型摻雜Si0.3Ge0.7及接面洩漏抑制層507A為n-型摻雜Si0.3Ge0.7。在實施例中，該一或更多鍺奈米線508係為壓縮應變(例如，相對於轉移層507C應變1-2%)。
雖然於上所述之裝置500係用於單一裝置， 例如，PMOS裝置，但也可以形成CMOS架構，以包含NMOS及PMOS奈米線為主之裝置配置於相同基板上或之上。在實施例中，奈米線508也可以作成大小為線，具有z及y尺寸實質相同或者，為z及y尺寸之一大於另一者的帶。奈米線508也可以具有無角、圓化或小刻面(例如有些角度非正交於z及y軸)。材料組成及尺寸也可以相同或類似於半導體堆疊100、及裝置300或400所述者。
在另一態樣中，提供製造奈米線半導體結構的方法。例如，圖6A-6D例示依據本發明實施例之三維剖面視圖，其顯示在製造奈米線半導體裝置的方法的各種操作，該裝置在製程中具有至少一點，具有下層SiGe轉移層的富Ge裝置層、及p-型摻雜Ge蝕刻抑制層。
參考圖6A，鰭型結構612係形成在基板604之上。該鰭包含富Ge裝置層608A’及608B’及兩中介富矽材料層609A’及609B’，例如，矽或矽鍺層中之高Si含量，高於裝置層608A’及608B’。雖然在其他實施例中，鰭型結構612可以向下延伸以包含有圖案部份的轉移層607C，但於此鰭停止於轉移層607C上。在實施例中，雖然未描繪出，但一緩衝層係被直接配置於基板604與接面洩漏抑制層607C之間。
圖6B例示具有三犧牲閘極結構614A、614B及614C分佈於其上的鰭型結構612。在此一實施例中，三犧牲閘極614A、614B及614C係由犧牲閘極氧化物層616及犧牲多晶矽閘極層618構成，這些譬如係以本技藝 中習知的電漿蝕刻製程加以全面沈積並圖案化。
圖案化以形成三犧牲閘極614A、614B及614C後，間隔層可以形成在三犧牲閘極614A、614B及614C的側壁上，並摻雜可以執行於圖6B所示之鰭型結構612的區域620中(例如，尖端及/或源及汲極區摻雜)，及層間介電層可以被形成以覆蓋然後再曝露該三犧牲閘極614A、614B及614C。層間介電層然後可以研磨以曝露出三個犧牲閘極614A、614B及614C，用於替換閘或閘最後(gate-last)製程。參考圖6C，三個犧牲閘極614A、614B及614C係與間隔層622及層間介電層614一起曝露。
例如，在本技藝中之替換閘或閘最後(gate last)製程流程中，犧牲閘極614A、614B及614C然後相對於被選擇材料被移除，以曝露出鰭型結構612之通道部份。參考圖6D，犧牲閘極614A、614B及614C被移除，以提供溝渠626，然後，因此，露出奈米線的通道部份。為溝渠626所曝露之中介犧牲層的部份被移除，以留下富Ge裝置層608A’及608B’的分立部份，以形成奈米線608A及608B。在圖6D中，犧牲材料609A係為清楚目的被顯示，但典型地將與配置在奈米線608A及608B間的犧牲層一起被移除。
在一實施例中，富矽犧牲層609A及609B係以濕蝕刻加以選擇地蝕刻，其並不蝕刻富Ge裝置層608A’及608B’，以釋放或底切裝置層608A’及608B’的長 度，而不為其他結構(例如間隔層622)所錨定。在一實施例中，濕蝕刻係靈敏於富Ge裝置層608A’及608B’的氧化狀態。例如但並不限於含水氫氧化物化學品，包含NH4OH、KOH及TMAH的蝕刻化學品可以被利用以選擇地蝕刻犧牲層609A及609B。p-型轉移層607B的出現係有利於改良相對於富Ge裝置層608A’及608B’的SiGe蝕刻的選擇性。在裝置層608A’及608B’為例如純Ge的實施例中，對奈米線的蝕刻選擇性係接近於無限大，使得犧牲層609A及609B可以沿著與裝置層608A’及608B’的化學尖銳介面移除(即裝置層的任何部份均未被蝕刻)。
在其他實施例中，雖然未顯示出，但轉移層607C及607B也可以例如在移除犧牲層609A及609B之前、之後或同時被移除。同時，擴散阻障層也可以整個移除或僅部份移除，例如在間隔層下留下殘留物，或者也可以完全不動。隨後，裝置製造可以完成。在一實施例中，如有關圖5A所述，包圍閘電極係被形成在鍺奈米線604及608周圍並在洩漏抑制層507A之上。
在圖6D所繪之製程階段中，也可以執行通道加工或調整。例如，在一實施例中，富Ge裝置層608A及608B的分立部份可以使用氧化及蝕刻製程等變薄。因此，無關於該裝置的源極及汲極區域的大小，由富Ge層608A’及608B’形成的初始線可以開始變厚，並變薄至適用於奈米線裝置的通道區域的大小。
在如圖6D所繪之分立通道區域的形成後， 高-k閘介電及金屬閘處理可以被執行，並加入源極與汲極接觸。接觸可以被形成在殘留在圖6D中之層間介電層624部份的位置中。再者，一或更多熱處理也可以退火半導體層，使得p-型摻雜層607B及n-型摻雜層607A可以一起擴散，甚至到達p-型及n-型摻雜物不會形成如圖1B所示之摻雜物分佈中之分開峰的點。然而，n-型摻雜層607A並未完全地為p-型摻雜層607A所補償，並且，因為退火可以在選擇性蝕刻SiGe犧牲層後執行，所以，p-型摻雜層607A的功能仍可以實現。
圖8例示依據本發明一實施法的計算裝置700。計算裝置700包圍住一板702。該板702可以包含若干元件，包含但並不限於處理器704及至少一通訊晶片706。處理器704為實體及電耦接至板702。在一些實施法中，該至少一通訊晶片706也實體及電耦接至板702。在其他實施法中，通訊晶片706係為處理器704的一部份。
取決於其應用，計算裝置700可以包含其他元件，其可以或可不實體及電耦接至板702。其他元件包含但並不限於揮發性記憶體(例如，DRAM)、非揮發記憶體(例如，ROM)、快閃記憶體、圖型處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控顯示器、觸控螢幕控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、喇叭、攝影機、及大量儲存裝置(例 如，硬碟機、光碟(CD)、數位多功能光碟(DVD)等等)。
通訊晶片706賦能無線通訊，用以傳送資料進出計算裝置700。用語“無線”及其衍生詞可以被用以描述電路、裝置、系統、方法、技術、通訊通道等，其可以透過使用調變電磁輻射經由非固體媒體而傳送資料。該用語並未暗示相關裝置未包含任何線，而是在一些實施例中可能沒有線。通訊晶片706可以實施若干無線標準或協定，包含但並不限於Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、Bluetooth及其衍生，及其他指定為3G、4G、5G及後續的無線協定之任一。計算裝置700可以包含多數通訊晶片706。例如，第一通訊晶片706可以專屬於較短距無線通訊，例如WiFi及藍芽及第二通訊晶片706可以專屬於較長距無線通訊，例如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
計算裝置700的處理器704包含封裝於處理器704內的積體電路晶粒。在本發明之一些實施例中，處理器的積體電路晶粒包含一或更多裝置，例如，依據本發明於其他部份所述實施例所建構的MOS-FET。用語“處理器”可以表示為任一裝置或裝置的部份，其處理來自暫存器及/或記憶體的電子資料，以轉換電子資料為可以被儲 存於暫存器及/或記憶體中之其他電子資料。
通訊晶片706也包含封裝於通訊晶片706內的積體電路晶粒。依據本發明的另一實施例，通訊晶片的積體電路晶粒包含一或更多裝置，例如具有特性及/或依據於說明書他處所述之實施例所製造的MOS-FET。
在其他實施法中，包圍在計算裝置700中的另一元件可以包含積體電路晶粒，其包含一或更多裝置，例如具有特性及/或依據於說明書他處所述之實施例所製造的MOS-FET。
在實施例中，計算裝置700可以為膝上型電腦、小筆電、筆記型電腦、超筆記型電腦、智慧手機、平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、列表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、行動音樂播放器或數位視訊記錄器。
應了解的是，上述說明只作例示性非限制性。再者，很多其他實施例將為熟習於本技藝者於讀取及了解以上說明後所明白。雖然本發明已經參考特定例示實施例加以描述，但可以得知，本發明並不限於所述實施例，而是在隨附申請專利範圍的精神與範圍內加以修改及更換實施。因此，本發明之範圍應參考隨附申請專利範圍及此等申請專利範圍的等效全範圍加以決定。
100‧‧‧半導體層堆疊
104‧‧‧基板
106‧‧‧SiGe緩衝層堆疊
106A‧‧‧第一層
106B‧‧‧第二層
107‧‧‧轉移層堆疊
107A‧‧‧n-型摻雜SiGe層
107A’‧‧‧間隔層
107B‧‧‧p-型摻雜SiGe層
107C‧‧‧半導體層
108‧‧‧富Ge裝置層堆疊
108A‧‧‧富Ge裝置層

Claims (13)

  1. 一種半導體裝置堆疊，包含：富鍺(Ge)裝置層，配置於基板之上；SiGe轉移層，配置於該基板上，並在該富鍺裝置層之下；p-型差量(δ)摻雜SiGe層，配置於該基板之上，及在該SiGe轉移層之下；及n-型SiGe層，配置於該基板之上，並在該p-型差量摻雜SiGe層之下。
  2. 如申請專利範圍第1項所述之半導體裝置堆疊，其中，該富鍺裝置層係為多數裝置層之一，該等多數裝置層係為中介犧牲半導體層所分開，其第一裝置層直接配置於第一犧牲層上，該第一犧牲層直接配置於該SiGe轉移層上，該SiGe轉移層直接配置於該p-型差量摻雜SiGe層上，及該p-型差量摻雜SiGe層與該n-型SiGe層分開SiGe間隔層。
  3. 如申請專利範圍第2項所述之半導體裝置堆疊，其中，該等中介犧牲半導體層具有較該等多數裝置層為低之Ge濃度；及其中該SiGe轉移層、該p-型差量摻雜SiGe層、該SiGe間隔層、及該n-型SiGe層都具有相同矽及鍺含量。
  4. 如申請專利範圍第3項所述之半導體裝置堆疊，其中該SiGe轉移層厚度係在25及100nm之間、該p-型差量摻雜SiGe層厚度係在5及15nm之間、該SiGe間隔 層厚度係在2及5nm之間、及該n-型SiGe層厚度係在5及20nm之間。
  5. 如申請專利範圍第4項所述之半導體裝置堆疊，其中該SiGe轉移層係本徵，其中該p-型差量摻雜SiGe層具有至少1e18cm-3的硼摻雜濃度，及其中該n-型SiGe層具有至少1e18cm-3的磷摻雜濃度。
  6. 如申請專利範圍第4項所述之半導體裝置堆疊，其中該等多數裝置層基本上為鍺構成且為未摻雜，且各個該等多數裝置層具有於5及15nm間之厚度，及其中該等中介犧牲半導體層係由SiGe所構成並各個具有5及30nm間之厚度。
  7. 如申請專利範圍第1項所述之半導體裝置堆疊，其中至少該富鍺裝置層及該SiGe轉移層被嵌入於相鄰隔離區域內也配置該基板。
  8. 一種半導體裝置，包含：閘極堆疊，包含閘極介電層及閘極電極配置於如申請專利範圍第1項所述之半導體裝置堆疊之上，其中該閘極介電層係直接接觸該富鍺裝置層；及源極區域及汲極區域，配置在該閘極堆疊的相對側上。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該富鍺裝置層包含非平面主體，具有二相對側壁由配置於該基板上並相鄰該半導體裝置堆疊的介電隔離區域延伸，及其中該閘極堆疊係配置於該等側壁上。
  10. 一種製造奈米線半導體裝置的方法，該方法包含：接收半導體裝置堆疊，其包含：富鍺(Ge)裝置層，配置在犧牲半導體層上，該犧牲半導體層較在該富鍺裝置層包含更多矽(Si)；p-型差量摻雜SiGe層，埋入在該犧牲半導體層之下；以濕蝕刻劑對該富鍺裝置層選擇地蝕刻該犧牲半導體層的至少部份厚度，以底切該富鍺裝置層並形成奈米線的分立通道區域；及形成至少部分地包圍該奈米線的該分立通道區域的閘極堆疊。
  11. 如申請專利範圍第10項所述之方法，其中該濕蝕刻劑係由：氫氧化銨、氫氧化鉀及氫氧化四甲銨(TMAH)所構成的群組選出。
  12. 如申請專利範圍第10項所述之方法，其中該濕蝕刻劑在該富鍺裝置層與該犧牲半導體層之間形成化學尖銳介面。
  13. 如申請專利範圍第10項所述之方法，其中該蝕刻係被執行，而沒有將該p-型差量摻雜SiGe層曝露至該濕蝕刻劑。
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