TWI775995B - 奈米線或奈米層片電晶體元件之電晶體延遲的控制方法 - Google Patents

奈米線或奈米層片電晶體元件之電晶體延遲的控制方法 Download PDF

Info

Publication number
TWI775995B
TWI775995B TW107143538A TW107143538A TWI775995B TW I775995 B TWI775995 B TW I775995B TW 107143538 A TW107143538 A TW 107143538A TW 107143538 A TW107143538 A TW 107143538A TW I775995 B TWI775995 B TW I775995B
Authority
TW
Taiwan
Prior art keywords
fin structure
stacked
channel
channel material
stacked fin
Prior art date
Application number
TW107143538A
Other languages
English (en)
Other versions
TW201937569A (zh
Inventor
傑佛瑞 史密斯
蘇巴迪普 卡爾
安東 德維利耶
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW201937569A publication Critical patent/TW201937569A/zh
Application granted granted Critical
Publication of TWI775995B publication Critical patent/TWI775995B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Networks Using Active Elements (AREA)
  • Pulse Circuits (AREA)

Abstract

一種製造半導體元件的方法包含：提供一基板，該基板包含用於形成第一環繞式閘極（GAA）電晶體之通道的第一堆疊鰭結構，該第一堆疊鰭結構包含一初始體積的第一通道材料，及用於形成第二GAA電晶體之通道的第二堆疊鰭結構，該第二堆疊鰭結構包含一初始體積的第二通道材料；將第二通道材料的初始體積相對於第一通道材料的初始體積減小對應於第一GAA電晶體之延遲的一預定量；及分別在第一通道材料及第二通道材料周圍形成第一及第二GAA閘極結構。

Description

奈米線或奈米層片電晶體元件之電晶體延遲的控制方法
本揭示內容關於製造半導體元件（諸如積體電路及用於積體電路之電晶體及電晶體元件）的方法。 [相關申請案]
本揭示內容主張於2017年12月4日申請、標題為“Method for Controlling Transistor Delay and for Balancing of NMOS and PMOS Nanowires on Nanosheets in Transistor Devices”之美國臨時專利申請案第62/594,352號的權利，其全部內容於此藉由參照納入本案揭示內容。
本文提供的背景說明係為了一般性地呈現本揭示內容之背景。在此先前技術章節中所述之目前列名發明者的工作成果、以及可能未在申請時以其他方式適格作為習知技術之說明的實施態樣，均不被明示或暗示承認為對於本揭示內容的習知技術。
在半導體元件的製造期間，執行諸多製造製程，諸如膜形成的沉積、蝕刻遮罩之產生、圖案化、光阻顯影、材料蝕刻和移除、及摻雜處理。重複地執行這些製程以在基板上形成期望的半導體裝置元件。歷史上，利用微製造，已使電晶體在一平面中產生，而具有配線/金屬化形成於其上，並因此已被特性化為二維（2D）電路或2D製造。縮放努力已大幅增加2D電路中每單位面積之電晶體的數目，然而隨著縮放進入個位數奈米半導體元件製造節點，縮放努力正面臨更大的挑戰。半導體元件製造者已表達對於三維（3D）半導體元件的需求，其中元件、電晶體及標準單元堆疊在彼此頂部上作為持續縮放的手段。3D半導體元件的製造引起許多與新製程整合、新穎硬體和製程能力、設計、製造後處理、電子設計自動化、及3D製造製程之其他方面相關之新及罕見的挑戰。
在一實施例中，製造半導體元件的方法包含：提供一基板，該基板包含用於形成第一環繞式閘極（GAA）電晶體之通道的第一堆疊鰭結構，該第一堆疊鰭結構包含設置在第一犧牲性材料之上部與下部間之一初始體積的第一通道材料，使得第一通道材料及第一犧牲性材料在第一堆疊鰭結構的一側處曝露，及用於形成第二GAA電晶體之通道的第二堆疊鰭結構，該第二堆疊鰭結構包含設置在第二犧牲性材料之上部與下部間之一初始體積的第二通道材料，使得第二通道材料及第二犧牲性材料在第二堆疊鰭結構的一側處曝露；將第二通道材料的初始體積相對於第一通道材料的初始體積減小對應於第一GAA電晶體之延遲的一預定量；及分別在第一通道材料及第二通道材料周圍形成第一及第二GAA閘極結構。
在另一實施例中，半導體元件包含：具有平坦表面的基板；第一環繞式閘極場效電晶體（GAA-FET），其設置在基板上且包含第一通道，該第一通道具有對應於由第一通道所形成的第一堆疊鰭結構內之第一通道材料的體積之未修整之第一通道材料的體積；及第二GAA-FET，其設置在基板上且包含第二通道，該第二通道具有修整之第二通道材料的體積，其小於未修整之第一通道材料的體積一預定修整量，該預定修整量對應於第二GAA-FET相對於第一GAA-FET的延遲調整，其中第一及第二GAA-FET電性連接作為互補性FET。
在另一實施例中，製造半導體元件的方法包含：提供一基板，該基板包含用於形成第一環繞式閘極（GAA）電晶體之通道的第一堆疊鰭結構，該第一堆疊鰭結構包含設置在第一犧牲性材料之上部與下部間之一初始體積的第一通道材料，使得第一通道材料及第一犧牲性材料在第一堆疊鰭結構的一側處曝露，及用於形成第二GAA電晶體之通道的第二堆疊鰭結構，該第二堆疊鰭結構包含設置在第二犧牲性材料之上部與下部間之一初始體積的第二通道材料，使得第二通道材料及第二犧牲性材料在第二堆疊鰭結構的一側處曝露；將第二通道材料的初始體積相對於第一通道材料的初始體積減小對應於第一GAA電晶體之閾值電壓的一預定量；及分別在第一通道材料及第二通道材料周圍形成第一及第二GAA閘極結構。
注意此發明內容章節未明確指出本揭示內容或所請發明的所有實施例及/或增加的新穎實施態樣。取而代之的是，此發明內容僅提供不同實施例的初步討論及新穎性的對應點。對於本發明及實施例的額外細節及/或可能的看法，讀者可參照下方進一步討論的實施方式章節及本揭示內容之相對應的圖式。
如本文描述之步驟的討論順序已為了清楚起見而呈現。通常，這些步驟可以任何適當的順序執行。此外，雖然本文各個不同的特徵、技術、配置等可在本揭示內容的不同地方討論，但吾人欲使各概念可彼此獨立或彼此結合而實行。因此，本發明可以許多不同的方式體現及審視。
現參照圖式，其中類似的參考數字指定遍及若干視圖之相同或對應的部分，以下描述關於用於藉由無數蝕刻技術平衡電晶體元件中之電晶體延遲的系統、裝置及相關的方法。
某些類型的電晶體元件以互補方式使用N型金屬氧化物半導體（NMOS）及P型金屬氧化物半導體（PMOS）。NMOS元件係基於電子的遷移率，其與電洞的遷移率相比可快好幾倍，電洞是PMOS元件的基礎。已開發藉由引起PMOS通道上的應變以增加PMOS元件中的遷移率、或藉由將PMOS元件的通道材料直接從矽改變為矽鍺而處理此不匹配的方法。還有一些影響場效電晶體（FET）中之電晶體延遲的其他因素，諸如材料、布局、尺寸等。舉例而言，與互補性主動區域相比，關聯於FET元件內之NMOS至PMOS平衡的延遲亦可為在NMOS或PMOS主動區域中從電力軌至輸出線的電源之間電晶體的數目間具有不匹配的結果。就三輸入NAND電路布局100而言，圖1中顯示前述者之一示例，其包含PMOS主動區域110及NMOS主動區域120。如圖所示，布局100包含閘極區域131、132及133，其每一者對互補性的電晶體對提供共同閘極輸入（A、B或C）。
進入NMOS主動區域120中的Vss節點141之來自Vss軌140的電源將在到達V外 節點151處的V外 端子150之前穿越三個電晶體，如NMOS主動區域120中的虛線箭頭所示。同時，用於Vdd的電源在3輸入NAND元件中可分成兩個獨立點，使得對於來自PMOS主動區域110中之Vdd軌160的電源而言，僅需使單一電晶體被穿越以到達V外 節點152。舉例而言，進入節點161之來自Vdd軌160的電源將在到達V外 節點152之前穿越單一電晶體，如由PMOS主動區域110中的虛線箭頭所示（顯示的三個不同路徑）。由於與PMOS主動區域110相比，需被穿越的電晶體之數目增加為三倍，因此對NMOS主動區域120引入延遲。在一些單元設計中，主動區域間之電晶體數目中的如此不平衡導致延遲效應，特別是當通過給定電晶體的輸出係接著在給定單元設計中供應作為至另一電晶體的輸入之時。
如此不平衡可藉由增加主動區域中之鰭結構的數目作為電晶體不平衡的一部分而加以處理。考慮三輸入NAND單元作為示例，NMOS主動區域將針對相應之PMOS主動區域中的每一鰭結構使用三個鰭結構。此技術可用於其中元件通道係鰭結構本身的鰭式場效電晶體（FinFET）處理、及其中元件通道係由從基鰭結構提供的一或更多單獨的奈米結構構成的奈米線或奈米層片處理。此方法在如此2D設計中係非常直接了當的，且簡單地涉及鰭結構的移除，無論在初始的鰭圖案化製程（通常藉由在圖案化製程的開始、中間、或結束時執行鰭切割（鰭移除）的自對準四重圖案化（SAQP））期間、或在鰭已轉移至主體矽中之後。舉例而言，利用如此2D設計，元件通道在通常是基板（例如晶圓）之工作表面的xy平面中分開。蝕刻系統可垂直於基板的工作表面（z平面）定向地蝕刻，且因此可使用蝕刻遮罩阻擋或切割橫向間隔的鰭或通道，只要可達到期望的解析度即可。當電晶體通道垂直堆疊在彼此的頂部上時，如此定向蝕刻技術係不合適的。
對於垂直堆疊的奈米線及/或奈米層片的情況及對於3D配置中之互補性場效電晶體元件（CFET）的情況而言，平衡NMOS及PMOS通道數係更具挑戰性，因為通道不作為在後續圖案化步驟期間可自元件簡單地切割之分隔實體而存在。
利用如此3D電路，奈米線或奈米層片可在彼此頂部之上堆疊，其中在垂直堆疊的奈米線或奈米層片之間有非常有限的距離（類似於下面描述之圖2的結構）。此間隔距離可為在10 nm以下的等級。因此，移除3D電路中的個別奈米線或奈米層片可包含配置切割介質，諸如已平坦化並向下凹陷、具有小誤差容限之非常精確之沉積的膜。如此平坦化及凹陷在整個晶圓之垂直堆疊的奈米線或奈米層片之間需要相對高的精確度。本發明人察知即使使用由下而上之選擇性沉積的膜沉積製程，在複雜拓撲之內進行膜之如此置放的能力仍具挑戰性。
作為另一選擇，奈米線或奈米層片可彼此配對。舉例而言，取代使四個堆疊的PMOS或NMOS奈米線或奈米層片通道在共同的起源鰭結構之內垂直地堆疊，使鰭數加倍而使得在各鰭結構上存在兩條堆疊的線。此技術針對使用上述簡單的鰭切割技術提供一些餘裕以容許電晶體平衡。此技術的一個缺點是有額外的鰭節距被納入給定的單元高度中。此外，如同對於三輸入NAND單元的情況而言是必需的，延遲僅可藉由移除通道對而不是移除單一通道加以處理。更整體而言，藉由完全移除僅單一通道的平衡被限制在基於關聯於整個通道的延遲之獨立的調整值。
對於包含在其互補性通道上垂直堆疊的PMOS或NMOS通道（奈米線或奈米層片）的互補性場效電晶體（CFET）元件的情況而言，挑戰增加。在此配置中，將起源鰭結構配對對於CFET的情況而言不再有效，因為此將移除單一基鰭結構之內的NMOS及PMOS通道兩者。
本文技術提供實現如此3D CFET元件及其他CFET元件之電晶體平衡的方法。本文技術藉由使用PMOS通道及NMOS通道材料的蝕刻選擇性修整而不是完全移除通道提供平衡。對於三輸入NAND單元的情況而言，取代驅動三個NMOS奈米線通道及單一PMOS奈米線通道，起源鰭數可包含用於NMOS及PMOS兩者的全部三個奈米線。此技術可包含其中PMOS通道被「修整」的方法，使得剩餘通道的電容效應將校正電晶體不平衡。因此，在此示例中，PMOS線可相對於NMOS線的尺寸修整，以校正此不平衡或產生期望的平衡。
圖2A顯示本揭示內容的技術可提供的示例結構。如圖所示，結構200包含其上具有基鰭結構203的基板201。各基鰭結構203包含在基鰭結構203內以高度方向h堆疊之通道材料205及犧牲性材料207之交替的層。基鰭結構203沿基板201的寬度方向w以及沿長度方向l橫向地間隔開。各基鰭結構203可用以形成一或更多第一環繞式閘極（GAA）電晶體。在圖2A的示例結構中，基鰭結構203各者包含用於形成第一GAA電晶體之通道區域的第一堆疊鰭結構210及用於形成第二GAA電晶體之通道區域的第二堆疊鰭結構220。第一及第二堆疊鰭結構210、220各者皆包含設置在犧牲性材料207的下部與上部間之通道材料205的初始體積。雖然堆疊鰭結構210、220各者皆顯示包含兩層通道材料205，但可僅使用單層。下部堆疊鰭結構210可用以提供例如NMOS元件，而上部堆疊鰭結構220可用以形成PMOS元件，如下進一步討論。
圖2B顯示用於製造半導體元件之方法的製程流程。如圖所示，製程包含提供其上具有第一及第二堆疊鰭結構210、220之半導體基板的步驟251。如此堆疊鰭結構210、220可在基板上設置在單一基鰭之內或設置在彼此橫向分開的單獨鰭片內。第一堆疊鰭結構210係用於形成第一環繞式閘極（GAA）電晶體的通道，而第二堆疊鰭結構220係用於形成第二GAA電晶體的通道。第一堆疊鰭結構210包含設置在第一犧牲性材料207的上部與下部間之一初始體積的第一通道材料205，使得第一通道材料及第一犧牲性材料在第一堆疊鰭結構210的一側處曝露。第二堆疊鰭結構220包含設置在第二犧牲性材料207的上部與下部間之一初始體積的第二通道材料205，使得第二通道材料205及第二犧牲性材料207在第二堆疊鰭結構220的一側處曝露。
在步驟253中，將第二通道材料205的初始體積相對於第一通道材料205的初始體積減小一預定量。如此減小可藉由蝕刻「修整」通道材料之初始體積的一部分而執行。預定量的體積減小對應於第一GAA電晶體的延遲。因此，「減小」允許第一GAA電晶體之電晶體延遲的調整，且可允許在第一與第二GAA電晶體之中對延遲進行平衡。
在步驟255中，第一和第二GAA閘極結構分別在第一通道材料205和第二通道材料205周圍形成。更具體而言，移除第一及第二犧牲性材料207以「釋放」第一及第二通道材料205。GAA閘極結構接著在所釋放之通道材料的每一者周圍形成。第一及第二GAA結構可電性連接，使得其彼此為互補的。因此，通道材料的其中一者自其初始體積的減小可用以平衡互補性元件中的延遲。
在一實施例中，藉由修整的平衡技術可應用於2D設計，其中在橫向間隔的基鰭結構之內設置主動區域。在一實施例中，第一主動區域包含第一類型的電晶體（例如NMOS），且第二主動區域包含第二類型的電晶體（例如PMOS）。第一主動區域包括包含第一類型通道（例如NMOS通道）的至少一鰭結構。第二主動區域包括包含第二類型通道（例如PMOS通道）的至少一鰭結構。這些通道可為單一奈米線或奈米層片通道、或由單一基鰭結構形成的多奈米結構。具有如此2D設計之NMOS或PMOS通道的選擇性修整是直接了當的，因為各組線存在於其獨特的主動區域（即基鰭）之內。就此而言，在執行蝕刻之前可沉積遮罩圖案，使得一主動區域（例如具有NMOS通道的NMOS主動區域）不受蝕刻，而第二主動區域（例如具有PMOS通道的PMOS主動區域）受蝕刻所影響。因此，電晶體延遲可藉由PMOS通道的「修整」而不是完全移除基鰭結構和與其關聯的所有通道加以平衡。
對於其中NMOS和PMOS通道在相同基鰭結構上之CFET元件的實施例而言，該方法變得更具挑戰性。然而，本文有諸多技術可用以在相同的起源鰭結構之內選擇性地修整NMOS及PMOS。舉例而言，本發明人察知儘管NMOS和PMOS通道設置在相同的基鰭結構上，但在NMOS和PMOS通道的垂直位置中有一些容限度量，使得在NMOS和PMOS通道間的垂直（z平面）邊界處可存在大於10 nm的間隔。此較大的間隔可促進材料填充、然後平坦化（CMP）、且接著向下凹陷以相對於其互補物選擇性地打開NMOS或PMOS。
在另一實施例中，在NMOS和PMOS之間使用不同的通道材料，且主體起源鰭結構可由磊晶生長的膜構成，該磊晶生長的膜對NMOS及PMOS的所欲通道材料兩者皆具有選擇性以增加PMOS區域內之電洞的遷移率。此實施例的示例包含SiGe作為PMOS通道材料、Si作為NMOS通道材料、且接著特定類型之摻雜的矽作為線釋放過程中最終將被移除之鰭的非通道材料。在此實施例中，使用具有不同蝕刻特性的至少兩個通道材料，其中可蝕刻第一通道材料而不蝕刻（移除）第二通道材料或第三主體鰭通道材料。
所提出之利用NMOS或PMOS通道之選擇性修整的方法不僅應用於控制電晶體延遲，亦可用以控制閾值電壓（Vt）。通常，藉由在通道上設定不同功函數金屬厚度調諧Vt。在典型的FINFET或環繞式閘極（GAA）元件中，此係通常藉由在所有通道沉積預定量的功函數金屬、且接著利用一組複雜的阻擋遮罩實現，該阻擋遮罩可用以打開選擇的電晶體以在待調諧的電晶體上回蝕預定量的功函數金屬。對於3D架構（諸如其中NMOS和PMOS元件堆疊在彼此頂部之上的互補性FET（CFET））而言，如此Vt調諧的方法在執行上可能是複雜的。此方法可提出調諧3D邏輯元件之Vt的方式，其中可調整初始通道寬度以控制Vt而不是僅改變功函數金屬的厚度。
本文技術實現藉由改變通道材料的體積而改變半導體通道材料中的電性延遲或Vt。此處的製程實現縮小鰭結構內的一或更多層通道材料，以造成一段通道材料之較小的體積或較小的橫截面體積。鰭結構可藉由沉積諸多不同的層形成以產生期望的鰭堆疊。此可包含在諸多第二通道材料層之頂部上形成的諸多第一通道材料層。各層通道材料可由諸如主體材料或載體材料的犧牲性材料分開。在形成層堆疊之後，可在其上形成蝕刻遮罩並用以非等向性地將圖案轉移通過材料的堆疊，從而產生鰭結構（具有諸多不同層之材料的線）。使用一蝕刻遮罩導致具有基本上相同初始體積的每一層。對於某些設計而言，縮小通道材料的其中一些者以造成改變（減小）的體積可為有益的，其因此造成不同的電性延遲值或Vt。因此，不同類型的材料（NMOS和PMOS）可堆疊在彼此的頂部上並以初始、相同的體積形成，且接著選擇性地縮小以改變通道材料的體積，而造成對於各類型材料的所欲延遲或Vt。
返回至圖2B的示例，圖3描繪堆疊的鰭結構300。堆疊的鰭結構300可提供具有複數通道305的目標NMOS區域310及目標PMOS區域320。複數通道305可為奈米線或奈米層片。在一實施例中，可藉由一阻擋遮罩保護目標NMOS區域310或PMOS區域320的主動區域，且同時保持互補物曝露以受蝕刻。在互補物受保護的情況下，曝露的奈米線或奈米層片可受蝕刻。如此重新制定尺寸可藉由蝕刻選擇性的修整執行。如此蝕刻選擇性的修整可為等向性的、氣相修整或化學氧化物移除（COR）。將露出的通道材料橫向修整且在通道的上和下表面上藉由非通道主體鰭材料307保護。舉例而言，對於NMOS區域310的情況而言，選擇Si作為通道材料並選擇SiGe作為主體鰭材料307。使用如此選擇及配置，蝕刻製程可使通道305的寬度選擇性地橫向凹陷，其中對SiGe主體鰭材料307具有非常高的選擇性（沒有SiGe的蝕刻或沒有SiGe的顯著蝕刻）以調整NMOS區域310的寬度。因此，在沒有個別通道移除的情況下使NMOS區域310及PMOS區域320平衡，且作為替代而藉由調整穿過主動區域之累積性通道材料的總體積或面積加以平衡。如上所討論，移除共同基鰭結構（例如圖2A的基鰭結構203）內的個別層變得困難，因為個別奈米線或奈米層片之間的間隙可小於10 nm，且置放覆蓋或阻擋膜來保護任何所需之具有良好容差之被保留線以曝露以蝕刻為目標之通道305（奈米線或奈米層片）的製程在目前處理（例如：材料沉積、CMP、凹槽蝕刻）的情況下可能非常困難。因此，在一實施例中，可在NMOS區域310與PMOS區域320之間產生相對較大的間隔。
圖3描繪堆疊的鰭結構300，其中間隔足以實現填充物材料330的使用，例如介電填充材料、後接CMP、後接凹部以相對於另一者保護或曝露一組通道305。舉例而言，介電填充物330材料可包含SiO。在圖3的示例中，NMOS區域310及PMOS區域320各包含Si通道305。也就是說，NMOS和PMOS區域的通道材料具有相同的化學組成。介電填充物330已充分凹陷以使堆疊的鰭結構300的上部中之NMOS區域310中的通道305曝露。接著執行選擇性的蝕刻以橫向修整曝露的通道305材料。舉例而言，可執行等向性的氣相蝕刻。如此氣相蝕刻相對於在對應的鰭組成中使用之其他磊晶生長晶體膜（諸如SiGe或摻雜的Si）可具有100：1的蝕刻選擇性。在此實施例中，可接著修整NMOS區域310之通道305的材料，其中PMOS區域320之通道305的材料藉由填充物材料330保護免受蝕刻。蝕刻改變NMOS區域310之通道305的材料之曝露的輪廓，其中通道305的橫截面或體積減小。
在一實施例中，NMOS區域310之通道305的材料可藉由在堆疊的鰭結構300之頂部上沉積填充物材料330而不覆蓋PMOS區域320之通道305的材料加以保護免受蝕刻。舉例而言，填充物材料330可藉由具有角度的蒸鍍方法朝堆疊的鰭結構300之頂部選擇性地沉積。複數遮罩鰭可毗鄰堆疊的鰭結構300製造，以在曝露於具有角度的蒸鍍時提供遮罩，其中複數遮罩鰭防止填充物材料330在複數遮罩鰭之陰影中的沉積。舉例而言，可藉由掠射角沉積（GLAD）提供具有角度的蒸鍍方法。
經修整之通道305之材料的量可基於電性要求或規格以使NMOS區域310及PMOS區域320平衡，且可基於預期的電晶體延遲或Vt計算，其中預期的電晶體延遲或Vt可基於被調諧之特定單元的局部區域。因此，蝕刻的量可基於相應單元的尺寸、單元的布局、使用的材料等。舉例而言，可使用循環性蝕刻製程將蝕刻調諧至幾埃的等級。可使用其他選擇性蝕刻製程，諸如原子層蝕刻（ALE）蝕刻及準ALE。就此而言，如此修整可提供精細程度的延遲或Vt調諧，其對於依賴如上討論之通道的完全移除之平衡技術是不可能的。
圖4描繪示例性受蝕刻之堆疊的鰭結構400，其中曝露的NMOS區域310已受蝕刻且具有減少的寬度之通道305’（即，通道體積）的特徵。
在具有塊狀填充的修整蝕刻之後，可完全移除剩餘的填充物330、或進一步使之充分地凹陷以曝露下方的通道材料。圖5描繪示例性堆疊的鰭結構500，其中填充物材料330進一步凹陷以曝露PMOS區域320，但在原位留下淺溝槽隔離（STI）部分530。
可針對特定區域、單元等接著移除犧牲性主體鰭材料307，例如SiGe。圖6顯示自堆疊的鰭結構移除SiGe主體鰭材料307以提供結構600的示例結果，該結構600包含垂直配置的NMOS區域310和PMOS區域320的通道305及減少之寬度之通道305’的部分。
如圖7所描繪，單元製造可繼續高k介電質705、NMOS功函數金屬710、PMOS功函數金屬715、和閘極填充金屬720的沉積、或如針對特定製造方案指定的其他製程，以產生環繞式閘極（GAA）電晶體元件700。換句話說，使通道305及減少之寬度的通道305’之尺寸改變以控制由NMOS區域310/PMOS區域320不平衡引起的延遲。在此實施例中，PMOS區域320和NMOS區域310可為相同的材料；在一材料受阻擋或覆蓋的情況下，可重新定制另一材料的尺寸。
在另一實施例中，可藉由選擇性的蝕刻及使用不同的通道材料改變NMOS和PMOS通道的尺寸或體積。此尺寸修改控制由NMOS/PMOS不平衡引起的延遲，並提供一或二通道類型的調諧。對於不同通道中的選擇性蝕刻而言，必須使用諸多不同的材料。如圖8所描繪，基鰭堆疊800包含具有第一通道材料805的第一堆疊鰭結構810、具有第二通道材料809的第二堆疊鰭結構820、及基板801上的犧牲性主體鰭材料807。舉例而言，主體鰭材料807可為摻雜的矽Si：X，例如Si：B材料。第一堆疊鰭結構810可為PMOS材料，而第二堆疊鰭結構820可為NMOS材料。第一通道材料805可為SiGe，而第二通道材料809可為Si，其中主體鰭材料807是第三材料。第一、第二、及第三材料對於特定的蝕刻製程具有不同的蝕刻抗性。第二堆疊鰭結構820可設置在第一堆疊鰭結構810之上，其中主體鰭材料807將兩區域分開。可有各通道類型的複數通道。更具體而言，可將不同通道材料用於第一通道材料805及第二通道材料809兩者。注意這是非限制性的，且可選擇更多材料及組合。利用具有不同蝕刻抗性之材料，不需覆蓋或阻擋一主動通道型區域，因為蝕刻抗性本身將保護互補性及主體材料免於受到蝕刻（顯著地受蝕刻）。
執行蝕刻製程，其蝕刻基鰭堆疊800中的一材料而不蝕刻基鰭堆疊800中的其他材料。此蝕刻製程可包含等向性蝕刻以在任何方向上均勻地蝕刻曝露的材料。基鰭堆疊800可為具有交替之具有不同蝕刻抗性之材料層的鰭結構。如上所述，可執行氣相蝕刻、化學氧化物移除蝕刻、ALE或準ALE蝕刻。因此，由於通道的側壁曝露，所以蝕刻導致橫向蝕刻。此選擇性蝕刻可橫向地修整給定材料的一部分，該給定材料係可藉由所使用的特定蝕刻劑及製程條件（化學化合物、腔室壓力、溫度等）加以蝕刻。
在一實施例中，蝕刻製程可選擇性地蝕刻第二堆疊鰭結構820的通道材料809而不顯著地蝕刻第一堆疊鰭結構810的通道材料805，其中第二堆疊鰭結構820可堆疊在第一堆疊鰭結構810的頂部之上。在另一實施例中，蝕刻製程可選擇性地蝕刻第一堆疊鰭結構810的通道材料805而不顯著地蝕刻第二堆疊鰭結構820的通道材料809，其中第二堆疊鰭結構820可堆疊在第一堆疊鰭結構810的頂部之上。
圖9描繪選擇性蝕刻後之示例性基鰭堆疊900的結果。注意在此示例中，第二堆疊鰭結構820的通道材料809’已橫向地蝕刻預定量而不蝕刻第一堆疊鰭結構810之通道材料805或主體鰭犧牲性材料807。
在第一蝕刻製程之後，若需要的話，可使用第二蝕刻製程以修整另一互補性通道材料。修整互補性通道材料可基於元件設計及電路的布局以產生所需的電晶體延遲或滿足電晶體延遲容差或Vt。修整互補性通道材料可在給定的處理腔室中藉由改變蝕刻化學品及蝕刻製程參數而原位執行。所修整的材料量可基於電性要求或規格，以在通道材料之垂直堆疊的配置中平衡PMOS區域810和NMOS區域820。針對給定通道材料之蝕刻的量可藉由基於預期的電晶體延遲或Vt之計算而決定，該預期的電晶體延遲或Vt係基於針對中繼而被調諧之給定單元的局部面積或區域。
在一或二（或更多）通道材料的蝕刻之後，可接著移除主體鰭材料807以露出區域810、820。主體鰭材料807可在露出的部分中被移除，使得奈米線或奈米層片在每一端部處受支撐。圖10描繪示例結果。如此主體鰭材料的移除亦可在相同的處理腔室（諸如使用氣相蝕刻的腔室/系統）內執行。
如圖11所描繪，在主體鰭材料的移除之後，處理可繼續以形成環繞式閘極（GAA）通道，諸如藉由沉積高k介電質1105、NMOS功函數金屬1110、PMOS功函數金屬1115、和閘極填充金屬1120。值得注意的是，圖11描繪對於其中PMOS和NMOS在彼此頂部之上的堆疊元件而言，藉由功函數金屬厚度減小進行Vt調諧可能有多困難。對於使用寬奈米線/奈米層片結構的堆疊元件而言，從線或層片的側面相較於層片之底部中心或頂部中心中移除相同量的金屬變得困難，尤其當在上方或下方有其他的層片之時。因此，所揭示之Vt調諧的方法可藉由針對個別電晶體改變通道體積而不是改變功函數金屬厚度而達成。
本文描述的如此修整技術實現一或二通道材料的調諧以精確地修改在包含3D CFET元件之FET元件中的電晶體延遲或Vt。本技術領域的人員可察知前述描述可能傾向描述調整電晶體延遲，但在判定通道體積減小方面，可針對調整而非電晶體延遲而以期望的預定閾值電壓調諧為目標。
在先前的描述中已說明具體細節，諸如處理系統的特殊幾何結構及其中使用的諸多元件與製程的描述。然而應理解，本文技術可在背離這些具體細節的其他實施例中實行，且此等細節係以解釋而非限制為目的。本文揭示的實施例已參考隨附圖式描述。同樣地，為了解釋的目的，已說明特定的數字、材料、及配置以提供完整的理解。儘管如此，實施例可在無如此具體細節的情況下實施。具有實質上相同功能性結構的元件以類似的參考符號表示，且因此可省略任何冗餘的描述。
為了有助於理解諸多實施例，將諸多技術以多個分立操作描述。不應將所述之順序理解成暗示該等操作必定為順序相依。尤其，該等操作不需以敘述的順序執行。所述之操作可以不同於所述實施例的順序執行。在額外的實施例中，可執行諸多額外操作及/或可省略所述之操作。
如本文使用的「基板」或「目標基板」泛指根據本發明所處理的物件。基板可包含元件（尤其是半導體或其他電子元件）的任何材料部分或結構，且例如可為基底基板結構，諸如半導體晶圓、倍縮光罩、或基底基板結構之上或覆蓋基底基板結構的一層（諸如薄膜）。因此，基板不限於任何特定的基底結構、下方層或覆蓋層、圖案化或未圖案化，而是設想為包含任何如此的層或基底結構、及層及/或基底結構的任何組合。此描述可能論及特定類型的基板，但此僅用於說明之目的。
精於本項技術之人士亦將理解對於以上所述技術的操作，可做出許多變化，且仍達到本發明的相同目標。如此變化意圖由本揭示內容的範圍所包含。因此，本發明之實施例的先前描述非意圖為限制性的。更準確地說，本發明之實施例的任何限制係呈現於以下申請專利範圍中。
雖然本揭示內容的實施態樣已結合其作為示例提出的具體實施例加以描述，但可針對該等示例做出替代方案、改良處理及變化。因此，如本文闡述的實施例意圖為說明性而非限制性的。在不背離下述申請專利範圍之範疇的情況下，可做出改變。
100‧‧‧布局 110‧‧‧PMOS主動區域 120‧‧‧NMOS主動區域 131‧‧‧閘極區域 132‧‧‧閘極區域 133‧‧‧閘極區域 140‧‧‧Vss軌 141‧‧‧Vss節點 150‧‧‧V外端子 151‧‧‧V外節點 152‧‧‧V外節點 160‧‧‧Vdd軌 161‧‧‧節點 200‧‧‧結構 201‧‧‧基板 203‧‧‧基鰭結構 205‧‧‧通道材料 207‧‧‧犧牲性材料 210‧‧‧第一堆疊鰭結構 220‧‧‧第二堆疊鰭結構 251‧‧‧步驟 253‧‧‧步驟 255‧‧‧步驟 300‧‧‧堆疊的鰭結構 305‧‧‧通道 305’‧‧‧通道 307‧‧‧主體鰭材料 310‧‧‧NMOS區域 320‧‧‧PMOS區域 330‧‧‧填充物材料（填充物） 400‧‧‧堆疊的鰭結構 500‧‧‧堆疊的鰭結構 530‧‧‧淺溝槽隔離（STI）部分 600‧‧‧結構 700‧‧‧環繞式閘極（GAA）電晶體元件 705‧‧‧高k介電質 710‧‧‧NMOS功函數金屬 715‧‧‧PMOS功函數金屬 720‧‧‧閘極填充金屬 800‧‧‧基鰭堆疊 801‧‧‧基板 805‧‧‧通道材料 807‧‧‧主體鰭材料（主體鰭犧牲性材料） 809‧‧‧通道材料 809’‧‧‧通道材料 810‧‧‧第一堆疊鰭結構（PMOS區域） 820‧‧‧第二堆疊鰭結構（NMOS區域） 900‧‧‧基鰭堆疊 1105‧‧‧高k介電質 1110‧‧‧NMOS功函數金屬 1115‧‧‧PMOS功函數金屬 1120‧‧‧閘極填充金屬
將參照以下圖式詳細描述作為示例提出之本揭示內容的諸多實施例，其中類似的號碼指示類似的元件，且其中：
圖1顯示根據本揭示內容的實施例之三輸入NAND電路的示例布局；
圖2A顯示根據本揭示內容的實施例之奈米線/奈米層片FET結構的等角視圖；
圖2B顯示製造半導體元件之方法的製程流程；
圖3顯示根據本揭示內容的實施例之具有保護一組通道之遮罩材料之鰭結構的橫截面圖；
圖4顯示根據本揭示內容的實施例之包含已受蝕刻之一組頂部通道之鰭結構的橫截面圖；
圖5顯示根據本揭示內容的實施例之包含已受蝕刻之一組頂部通道及已凹陷之遮罩材料之鰭結構的橫截面圖；
圖6顯示根據本揭示內容的實施例之鰭結構的橫截面圖，其中主體鰭材料已被移除；
圖7顯示根據本揭示內容的實施例之環繞式閘極電晶體元件；
圖8顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中遮罩材料保護一組通道；
圖9顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中一組頂部通道已選擇性地受蝕刻；
圖10顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中主體鰭材料已被移除；及
圖11顯示根據本揭示內容的實施例之具有兩不同通道材料的環繞式閘極電晶體元件。
251‧‧‧步驟
253‧‧‧步驟
255‧‧‧步驟

Claims (16)

  1. 一種製造半導體元件的方法，包含：提供一基板，該基板包含：用於形成第一環繞式閘極(GAA)電晶體之通道的第一堆疊鰭結構，該第一堆疊鰭結構包含設置在第一犧牲性材料之上部與下部間之一初始體積的第一通道材料，使得該第一通道材料及該第一犧牲性材料在該第一堆疊鰭結構的一側處曝露，及用於形成第二GAA電晶體之通道的第二堆疊鰭結構，該第二堆疊鰭結構包含設置在第二犧牲性材料之上部與下部間之一初始體積的第二通道材料，使得該第二通道材料及該第二犧牲性材料在該第二堆疊鰭結構的一側處曝露；遮蔽該第一堆疊鰭結構的側壁；在該遮蔽過後，經由蝕刻該第二堆疊鰭結構以將該第二通道材料的初始體積修整至對應於該第二GAA電晶體之預定延遲之修整的體積，藉以將該第二通道材料的初始體積相對於該第一通道材料的初始體積減小對應於該第一GAA電晶體之延遲的一預定量；及分別在該第一通道材料及該第二通道材料周圍形成第一及第二GAA閘極結構。
  2. 如申請專利範圍第1項之製造半導體元件的方法，其中該第二堆疊鰭結構堆疊在共同基鰭結構內的該第一堆疊鰭結構之上。
  3. 如申請專利範圍第2項之製造半導體元件的方法，其中該第一通道材料具有與該第二通道材料相同的化學組成。
  4. 如申請專利範圍第2項之製造半導體元件的方法，更包含在該第一堆疊鰭結構與該第二堆疊鰭結構之間提供預定厚度的犧牲性間隔材料，該預定厚度係選擇成提供用於遮罩該第一堆疊鰭結構的製程容差。
  5. 如申請專利範圍第4項之製造半導體元件的方法，其中該預定厚度的犧牲性間隔材料係大於10nm。
  6. 如申請專利範圍第2項之製造半導體元件的方法，其中：該第一通道材料具有不同於該第二通道材料的化學組成，及該減小步驟包含將該第一及第二堆疊鰭結構曝露於等向性蝕刻製程，該等向性蝕刻製程相對於該第一通道材料選擇性地蝕刻該第二通道材料。
  7. 如申請專利範圍第1項之製造半導體元件的方法，其中該第一堆疊鰭結構設置在第一基鰭結構之內，且該第二堆疊鰭結構設置在第二基鰭結構之內，該第二基鰭結構沿該基板的平坦表面與該第一基鰭結構橫向間隔。
  8. 如申請專利範圍第7項之製造半導體元件的方法，其中該減小步驟包含：遮蔽該第一基鰭結構，及蝕刻該第二基鰭結構以減小該第二通道材料的初始體積。
  9. 如申請專利範圍第1項之製造半導體元件的方法，其中該第一堆疊鰭結構堆疊在共同基鰭結構內的該第二堆疊鰭結構之上。
  10. 如申請專利範圍第1項之製造半導體元件的方法，其中該第一堆疊鰭結構堆疊在共同基鰭結構內的該第二堆疊鰭結構之上，及使用具有角度的沉積而進行遮罩材料的沉積，藉以遮蔽該第一堆疊鰭結構。
  11. 如申請專利範圍第10項之製造半導體元件的方法，更包括：至少一毗鄰遮罩結構，其中該至少一毗鄰遮罩結構的陰影避免該遮罩材料在該具有角度的沉積期間沉積於該第二堆疊鰭結構上。
  12. 一種製造半導體元件的方法，包含：提供一基板，該基板包含：用於形成第一環繞式閘極(GAA)電晶體之通道的第一堆疊鰭結構，該第一堆疊鰭結構包含設置在第一犧牲性材料之上部與下部間之一初始體積的第一通道材料，使得該第一通道材料及該第一犧牲性材料在該第一堆疊鰭結構的一側處曝露，及用於形成第二GAA電晶體之通道的第二堆疊鰭結構，該第二堆疊鰭結構包含設置在第二犧牲性材料之上部與下部間之一初始體積的第二 通道材料，使得該第二通道材料及該第二犧牲性材料在該第二堆疊鰭結構的一側處曝露；遮蔽該第一堆疊鰭結構的側壁；在該遮蔽過後，經由蝕刻該第二堆疊鰭結構以將該第二通道材料的初始體積修整至對應於該第二GAA電晶體之預定延遲之修整的體積，藉以將該第二通道材料的初始體積相對於該第一通道材料的初始體積減小對應於該第一GAA電晶體之閾值電壓的一預定量；及分別在該第一通道材料及該第二通道材料周圍形成第一及第二GAA閘極結構。
  13. 如申請專利範圍第12項之製造半導體元件的方法，其中該第二堆疊鰭結構堆疊在共同基鰭結構內的該第一堆疊鰭結構之上。
  14. 如申請專利範圍第12項之製造半導體元件的方法，更包含在該第一堆疊鰭結構與該第二堆疊鰭結構之間提供預定厚度的犧牲性間隔材料，該預定厚度係選擇成提供用於遮罩該第一堆疊鰭結構的製程容差。
  15. 如申請專利範圍第12項之製造半導體元件的方法，其中該第一堆疊鰭結構堆疊在共同基鰭結構內的該第二堆疊鰭結構之上，及使用具有角度的沉積而進行遮罩材料的沉積，藉以遮蔽該第一堆疊鰭結構。
  16. 如申請專利範圍第15項之製造半導體元件的方法，更包括： 至少一毗鄰遮罩結構，其中該至少一毗鄰遮罩結構的陰影避免該遮罩材料在該具有角度的沉積期間沉積於該第二堆疊鰭結構上。
TW107143538A 2017-12-04 2018-12-04 奈米線或奈米層片電晶體元件之電晶體延遲的控制方法 TWI775995B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762594352P 2017-12-04 2017-12-04
US62/594,352 2017-12-04

Publications (2)

Publication Number Publication Date
TW201937569A TW201937569A (zh) 2019-09-16
TWI775995B true TWI775995B (zh) 2022-09-01

Family

ID=66659359

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107143538A TWI775995B (zh) 2017-12-04 2018-12-04 奈米線或奈米層片電晶體元件之電晶體延遲的控制方法

Country Status (6)

Country Link
US (2) US10714391B2 (zh)
JP (1) JP7089656B2 (zh)
KR (2) KR102449793B1 (zh)
CN (1) CN111566803B (zh)
TW (1) TWI775995B (zh)
WO (1) WO2019112954A1 (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404325B2 (en) 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
KR102434993B1 (ko) * 2015-12-09 2022-08-24 삼성전자주식회사 반도체 소자
US10825933B2 (en) * 2018-06-11 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around structure and manufacturing method for the same
US20200295127A1 (en) * 2019-03-13 2020-09-17 Intel Corporation Stacked transistors with different crystal orientations in different device strata
US11037905B2 (en) * 2019-04-26 2021-06-15 International Business Machines Corporation Formation of stacked vertical transport field effect transistors
US11069679B2 (en) 2019-04-26 2021-07-20 International Business Machines Corporation Reducing gate resistance in stacked vertical transport field effect transistors
JP2022532757A (ja) * 2019-05-13 2022-07-19 ボード オブ リージェンツ，ザ ユニバーシティ オブ テキサス システム ３次元ｓｒａｍアーキテクチャ及び光導波路を製造するための触媒影響化学エッチング
US11710667B2 (en) * 2019-08-27 2023-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same
US11557655B2 (en) * 2019-10-11 2023-01-17 Tokyo Electron Limited Device and method of forming with three-dimensional memory and three-dimensional logic
CN112951912B (zh) * 2019-12-10 2024-05-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11302692B2 (en) * 2020-01-16 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
US11368016B2 (en) 2020-03-18 2022-06-21 Mavagail Technology, LLC ESD protection for integrated circuit devices
US11837280B1 (en) * 2020-05-20 2023-12-05 Synopsys, Inc. CFET architecture for balancing logic library and SRAM bitcell
WO2022067580A1 (zh) * 2020-09-29 2022-04-07 华为技术有限公司 晶体管及其制作方法、集成电路、电子设备
WO2022104489A1 (es) 2020-11-20 2022-05-27 Drovid Technologies Método para transmitir y rastrear parámetros detectados por drones mediante (paas) con (ia).
CN116250077A (zh) * 2020-11-24 2023-06-09 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法
US11527535B2 (en) 2021-01-21 2022-12-13 International Business Machines Corporation Variable sheet forkFET device
US11424120B2 (en) 2021-01-22 2022-08-23 Tokyo Electron Limited Plasma etching techniques
CN113130489A (zh) * 2021-03-12 2021-07-16 中国科学院微电子研究所 一种半导体器件的制造方法
US11843001B2 (en) 2021-05-14 2023-12-12 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
US20220367658A1 (en) * 2021-05-14 2022-11-17 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
CN115425076A (zh) * 2021-05-14 2022-12-02 三星电子株式会社 纳米片晶体管器件及其形成方法
CN115347043A (zh) * 2021-05-14 2022-11-15 三星电子株式会社 纳米片晶体管器件及其形成方法
US12087770B2 (en) 2021-08-05 2024-09-10 International Business Machines Corporation Complementary field effect transistor devices
KR20230025178A (ko) * 2021-08-13 2023-02-21 삼성전자주식회사 반도체 소자
US20230066265A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation layers in stacked semiconductor devices
US12113067B2 (en) 2021-09-13 2024-10-08 International Business Machines Corporation Forming N-type and P-type horizontal gate-all-around devices
US11837604B2 (en) 2021-09-22 2023-12-05 International Business Machine Corporation Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
US20230086888A1 (en) * 2021-09-23 2023-03-23 International Business Machines Corporation Dual strained semiconductor substrate and patterning
WO2023225155A1 (en) * 2022-05-20 2023-11-23 Tokyo Electron Limited Sequential complimentary fet incorporating backside power distribution network through wafer bonding prior to formation of active devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7374986B2 (en) * 2004-09-07 2008-05-20 Samsung Electronics Co., Ltd. Method of fabricating field effect transistor (FET) having wire channels
US9224810B2 (en) * 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
TW201701359A (zh) * 2015-06-30 2017-01-01 台灣積體電路製造股份有限公司 半導體元件與其製作方法
US20170040321A1 (en) * 2015-08-06 2017-02-09 Imec Vzw Gate-all-around nanowire device and method for manufacturing such a device
CN106531632A (zh) * 2015-09-10 2017-03-22 中国科学院微电子研究所 堆叠纳米线mos晶体管制作方法
CN106960870A (zh) * 2016-01-11 2017-07-18 三星电子株式会社 半导体装置及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029503A (ja) 2009-07-28 2011-02-10 Toshiba Corp 半導体装置
US8551833B2 (en) * 2011-06-15 2013-10-08 International Businesss Machines Corporation Double gate planar field effect transistors
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
WO2014018201A1 (en) 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
KR102002380B1 (ko) * 2012-10-10 2019-07-23 삼성전자 주식회사 반도체 장치 및 그 제조 방법
WO2015050546A1 (en) * 2013-10-03 2015-04-09 Intel Corporation Internal spacers for nanowire transistors and method of fabrication thereof
US9893167B2 (en) * 2014-03-24 2018-02-13 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
WO2017044107A1 (en) * 2015-09-10 2017-03-16 Intel Corporation Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
US9583399B1 (en) * 2015-11-30 2017-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9627540B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US20170170268A1 (en) * 2015-12-15 2017-06-15 Qualcomm Incorporated NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES
KR102416133B1 (ko) 2016-01-11 2022-07-01 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102360333B1 (ko) 2016-02-18 2022-02-08 삼성전자주식회사 반도체 장치
WO2017151958A1 (en) 2016-03-02 2017-09-08 Tokyo Electron Limited Isotropic silicon and silicon-germanium etching with tunable selectivity
US10770593B2 (en) * 2016-04-01 2020-09-08 Intel Corporation Beaded fin transistor
US9660028B1 (en) * 2016-10-31 2017-05-23 International Business Machines Corporation Stacked transistors with different channel widths

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7374986B2 (en) * 2004-09-07 2008-05-20 Samsung Electronics Co., Ltd. Method of fabricating field effect transistor (FET) having wire channels
US9224810B2 (en) * 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
TW201701359A (zh) * 2015-06-30 2017-01-01 台灣積體電路製造股份有限公司 半導體元件與其製作方法
US20170040321A1 (en) * 2015-08-06 2017-02-09 Imec Vzw Gate-all-around nanowire device and method for manufacturing such a device
CN106531632A (zh) * 2015-09-10 2017-03-22 中国科学院微电子研究所 堆叠纳米线mos晶体管制作方法
CN106960870A (zh) * 2016-01-11 2017-07-18 三星电子株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
CN111566803B (zh) 2024-02-23
US10714391B2 (en) 2020-07-14
US20190172751A1 (en) 2019-06-06
KR102550501B1 (ko) 2023-06-30
KR20220137168A (ko) 2022-10-11
KR20200085920A (ko) 2020-07-15
CN111566803A (zh) 2020-08-21
WO2019112954A1 (en) 2019-06-13
JP7089656B2 (ja) 2022-06-23
KR102449793B1 (ko) 2022-09-29
JP2021506141A (ja) 2021-02-18
TW201937569A (zh) 2019-09-16
US10991626B2 (en) 2021-04-27
US20200303256A1 (en) 2020-09-24

Similar Documents

Publication Publication Date Title
TWI775995B (zh) 奈米線或奈米層片電晶體元件之電晶體延遲的控制方法
JP7117057B2 (ja) 相補型電界効果トランジスタ（ｃｆｅｔ）デバイスにおいて複数のチャネル材料を組み込む方法
KR102393744B1 (ko) 나노와이어 ｆｅｔ 디바이스를 위한 게이트 스페이서를 형성하는 방법
TWI710013B (zh) 使用單元隔離柱對主動奈米結構間的 n-p 空間之功函數金屬圖案化
CN114097074A (zh) 用于通过高k金属栅极(hkmg)膜堆叠的选择性沉积来进行阈值电压调谐的方法
US20160086952A1 (en) Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
TW202137572A (zh) 積體晶片
US10236291B2 (en) Methods, apparatus and system for STI recess control for highly scaled finFET devices
TW202226345A (zh) 用於高性能邏輯的多數個3d垂直cmos裝置
JP2023552930A (ja) Ｎ／ｐ境界構造を有するナノシート半導体デバイス
US20240145595A1 (en) 3d isolation of a segmentated 3d nanosheet channel region

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent