CN110676304B - 制造半导体器件的方法和半导体器件 - Google Patents
制造半导体器件的方法和半导体器件 Download PDFInfo
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- CN110676304B CN110676304B CN201910439996.9A CN201910439996A CN110676304B CN 110676304 B CN110676304 B CN 110676304B CN 201910439996 A CN201910439996 A CN 201910439996A CN 110676304 B CN110676304 B CN 110676304B
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Abstract
一种制造半导体器件的方法包括:在半导体衬底上形成沿第一方向延伸的多个鳍结构。每个鳍结构包括靠近半导体衬底的第一区域和远离半导体衬底的第二区域。在第一相邻鳍结构对的第一区域之间形成导电层。在鳍结构的第二区域上方形成沿与第一方向基本垂直的第二方向延伸的栅电极结构,并且在栅电极结构上形成包括至少一条导线的金属化层。本发明的实施例还涉及半导体器件。
Description
技术领域
本发明的实施例涉及制造半导体集成电路的方法,并且更具体地涉及制造包括鳍式场效应晶体管(FinFET)和/或全环栅(GAA)FET的半导体器件的方法以及半导体器件。
背景技术
随着半导体行业在寻求更高器件密度、更高性能和更低成本的工艺中已经发展成纳米技术工艺节点,制造和设计问题的挑战引起了三维设计的发展,例如多栅极场效应晶体管(FET),包括鳍式FET(FinFET)和全环栅(GAA)FET。在FinFET中,栅电极与沟道区的三个侧表面相邻,栅极介电层插入其间。因为栅极结构在三个表面上围绕(包裹)鳍,所以晶体管基本上具有三个栅极,栅极控制通过鳍或沟道区的电流。沟道的第四侧、底部进一步远离栅电极,因此不受栅极控制。相反,在GAA FET中,沟道区的所有侧表面都被栅电极围绕。随着晶体管尺寸不断缩小到低于10-15纳米的技术节点,需要进一步改进FinFET和GAA FET。
发明内容
本发明的实施例提供了一种制造半导体器件的方法,包括:在半导体衬底上形成沿第一方向延伸的多个鳍结构,其中,每个所述鳍结构包括靠近所述半导体衬底的第一区域和远离所述半导体衬底的第二区域;在第一相邻鳍结构对的所述第一区域之间形成导电层;在所述鳍结构的所述第二区域上方形成沿与所述第一方向垂直的第二方向延伸的栅电极结构;以及在所述栅电极结构上形成包括至少一条导线的金属化层。
本发明的另一实施例提供了一种制造半导体器件的方法,包括:在半导体衬底上形成具有第一组分的第一半导体层;在所述第一半导体层上形成具有第二组分的第二半导体层;在所述第二半导体层上形成具有所述第一组分的另一第一半导体层;在所述另一第一半导体层上形成具有所述第二组分的另一第二半导体层;图案化所述第一半导体层、所述第二半导体层和所述半导体衬底以形成沿第一方向延伸的多个鳍结构,其中,所述鳍结构包括与所述半导体衬底相邻的第一区域和包括所述第一半导体层和所述第二半导体层的第二区域,所述第二区域包括在一对第二部分之间沿所述第一方向延伸的第一部分;在所述鳍结构上形成绝缘衬垫层;在所述鳍结构之间形成隔离绝缘层;从第一对相邻鳍结构之间去除所述隔离绝缘层;在所述第一对相邻鳍结构之间形成第一导电层;从所述鳍结构的所述第二区域去除所述绝缘衬垫层;从所述鳍结构的所述第二区域的第一部分去除所述第一半导体层,从而形成包括所述第二半导体层的纳米线;在所述鳍结构的所述第一部分上形成围绕所述纳米线的介电层和第二导电层,从而形成在垂直于所述第一方向的第二方向上延伸的栅电极结构;以及在所述栅电极结构上形成包括多条导线的金属化层。
本发明的又一实施例提供了一种半导体器件,包括:多个鳍结构,沿第一方向延伸并且设置在半导体衬底上,其中,每个所述鳍结构包括靠近所述半导体衬底的第一区域和远离所述半导体衬底的第二区域;至少一个第一导电层,设置在相邻的一对鳍结构的所述第一区域之间;至少一个栅电极结构,在垂直于所述第一方向的第二方向上延伸并且设置在所述鳍结构的所述第二区域的第一部分上;以及金属化层,包括至少一条导线并且设置在所述栅电极结构上方。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的等距视图。
图2示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的等距视图。
图3A至图3E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图3A是等距视图。图3B是沿图3A中的线A-A'截取的截面图。图3C是沿图3A中的线B-B'的截面图。图3D是沿图3A的线C-C'截取的截面图。图3E是沿图3A中的线D-D’截取的截面图。
图4A至图4E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图4A是等距视图。图4B是沿图4A中的线A-A'截取的截面图。图4C是沿图4A的线B-B’截取的截面图。图4D是沿图4A的线C-C’截取的截面图。图4E是沿图4A的线D-D’截取的截面图。
图5A至图5E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图5A是等距视图。图5B是沿图5A中的线A-A'截取的截面图。图5C是沿图5A的线B-B’截取的截面图。图5D是沿图5A的线C-C’截取的截面图。图5E是沿图5A的线D-D’截取的截面图。
图6A至图6E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图6A是等距视图。图6B是沿图6A中的线A-A'截取的截面图。图6C是沿图6A的线B-B’截取的截面图。图6D是沿图6A中的线C-C'截取的截面图。图6E是沿图6A的线D-D’截取的截面图。
图7A至图7E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图7A是等距视图。图7B是沿图7A中的线A-A'截取的截面图。图7C是沿图7A的线B-B’截取的截面图。图7D是沿图7A中的线C-C'截取的截面图。图7E是沿图7A的线D-D’截取的截面图。
图8A至图8E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图8A是等距视图。图8B是沿图8A中的线A-A'截取的截面图。图8C是沿图8A的线B-B’截取的截面图。图8D是沿图8A中的线C-C'截取的截面图。图8E是沿图8A的线D-D’截取的截面图。
图9A至图9E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图9A是等距视图。图9B是沿图9A中的线A-A'截取的截面图。图9C是沿图9A的线B-B’截取的截面图。图9D是沿图9A中的线C-C'截取的截面图。图9E是沿图9A的线D-D’截取的截面图。
图10A至图10E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图10A是等距视图。图10B是沿图10A中的线A-A'截取的截面图。图10C是沿图10A的线B-B’截取的截面图。图10D是沿图10A中的线C-C'截取的截面图。图10E是沿图10A的线D-D’截取的截面图。
图11A至图11E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图11A是等距视图。图11B是沿图11A中的线A-A'截取的截面图。图11C是沿图11A的线B-B’截取的截面图。图11D是沿图11A中的线C-C'截取的截面图。图11E是沿图11A的线D-D’截取的截面图。
图12A至图12E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图12A是等距视图。图12B是沿图12A中的线A-A'截取的截面图。图12C是沿图12A的线B-B’截取的截面图。图12D是沿图12A中的线C-C'截取的截面图。图12E是沿图12A的线D-D’截取的截面图。
图13A至图13F示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图13A是等距视图。图13B是沿图13A中的线A-A'截取的截面图。图13C是沿图13A的线B-B’截取的截面图。图13D是沿图13A中的线C-C'截取的截面图。图13E是沿图13A的线D-D’截取的截面图。图13F是沿图13A中的线C-C'截取的另一实施例的截面图。
图14A至图14F示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图14A是等距视图。图14B是沿图14A中的线A-A'截取的截面图。图14C是沿图14A的线B-B’截取的截面图。图14D是沿图14A中的线C-C'截取的截面图。图14E是沿图14A的线D-D’截取的截面图。图14F是沿图14A中的线C-C'截取的另一实施例的截面图。
图15A至图15E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图15A是等距视图。图15B是沿图15A中的线A-A'截取的截面图。图15C是沿图15A的线B-B’截取的截面图。图15D是沿图15A中的线C-C'截取的截面图。图15E是沿图15A的线D-D’截取的截面图。
图16A至图16E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图16A是等距视图。图16B是沿图16A中的线A-A'截取的截面图。图16C是沿图16A的线B-B’截取的截面图。图16D是沿图16A中的线C-C'截取的截面图。图16E是沿图16A的线D-D’截取的截面图。
图17A至图17E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图17A是等距视图。图17B是沿图17A中的线A-A'截取的截面图。图17C是沿图17A的线B-B’截取的截面图。图17D是沿图17A中的线C-C'截取的截面图。图17E是沿图17A的线D-D’截取的截面图。
图18A至图18E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图18A是等距视图。图18B是沿图18A中的线A-A'截取的截面图。图18C是沿图18A的线B-B’截取的截面图。图18D是沿图18A中的线C-C'截取的截面图。图18E是沿图18A的线D-D’截取的截面图。
图19A至图19E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图19A是等距视图。图19B是沿图19A中的线A-A'截取的截面图。图19C是沿图19A的线B-B’截取的截面图。图19D是沿图19A中的线C-C'截取的截面图。图19E是沿图19A的线D-D’截取的截面图。
图20A至图20E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图20A是等距视图。图20B是沿图20A中的线A-A'截取的截面图。图20C是沿图20A的线B-B’截取的截面图。图20D是沿图20A中的线C-C'截取的截面图。图20E是沿图20A的线D-D’截取的截面图。
图21A至图21E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图21A是等距视图。图21B是沿图21A中的线A-A'截取的截面图。图21C是沿图21A的线B-B’截取的截面图。图21D是沿图21A中的线C-C'截取的截面图。图21E是沿图21A的线D-D’截取的截面图。
图22A至图22E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图22A是等距视图。图22B是沿图22A中的线A-A'截取的截面图。图22C是沿图22A的线B-B’截取的截面图。图22D是沿图22A中的线C-C'截取的截面图。图22E是沿图22A的线D-D’截取的截面图。
图23A至图23E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图23A是等距视图。图23B是沿图23A中的线A-A'截取的截面图。图23C是沿图23A的线B-B’截取的截面图。图23D是沿图23A中的线C-C'截取的截面图。图23E是沿图23A的线D-D’截取的截面图。
图24A至图24E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图24A是等距视图。图24B是沿图24A中的线A-A'截取的截面图。图24C是沿图24A的线B-B’截取的截面图。图24D是沿图24A中的线C-C'截取的截面图。图24E是沿图24A的线D-D’截取的截面图。
图25A至图25E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图25A是等距视图。图25B是沿图25A中的线A-A'截取的截面图。图25C是沿图25A的线B-B’截取的截面图。图25D是沿图25A中的线C-C'截取的截面图。图25E是沿图25A的线D-D’截取的截面图。
图26A至图26E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图26A是等距视图。图26B是沿图26A中的线A-A'截取的截面图。图26C是沿图26A的线B-B’截取的截面图。图26D是沿图26A中的线C-C'截取的截面图。图26E是沿图26A的线D-D’截取的截面图。
图27A至图27E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图27A是等距视图。图27B是沿图27A中的线A-A'截取的截面图。图27C是沿图27A的线B-B’截取的截面图。图27D是沿图27A中的线C-C'截取的截面图。图27E是沿图27A的线D-D’截取的截面图。
图28A至图28E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图28A是等距视图。图28B是沿图28A中的线A-A'截取的截面图。图28C是沿图28A的线B-B’截取的截面图。图28D是沿图28A中的线C-C'截取的截面图。图28E是沿图28A的线D-D’截取的截面图。
图29A至图29E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图29A是等距视图。图29B是沿图29A中的线A-A'截取的截面图。图29C是沿图29A的线B-B’截取的截面图。图29D是沿图29A中的线C-C'截取的截面图。图29E是沿图29A的线D-D’截取的截面图。
图30A至图30E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图30A是等距视图。图30B是沿图30A中的线A-A'截取的截面图。图30C是沿图30A的线B-B’截取的截面图。图30D是沿图30A中的线C-C'截取的截面图。图30E是沿图30A的线D-D’截取的截面图。
图31A至图31E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图31A是等距视图。图31B是沿图31A中的线A-A'截取的截面图。图31C是沿图31A的线B-B’截取的截面图。图31D是沿图31A中的线C-C'截取的截面图。图31E是沿图31A的线D-D’截取的截面图。
图32A至图32E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图32A是等距视图。图32B是沿图32A中的线A-A'截取的截面图。图32C是沿图32A的线B-B’截取的截面图。图32D是沿图32A中的线C-C'截取的截面图。图32E是沿图32A的线D-D’截取的截面图。
图33A至图33E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图33A是等距视图。图33B是沿图33A中的线A-A'截取的截面图。图33C是沿图33A的线B-B’截取的截面图。图33D是沿图33A中的线C-C'截取的截面图。图33E是沿图33A的线D-D’截取的截面图。
图34A至图34E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图34A是等距视图。图34B是沿图34A中的线A-A'截取的截面图。图34C是沿图34A的线B-B’截取的截面图。图34D是沿图34A中的线C-C'截取的截面图。图34E是沿图34A的线D-D’截取的截面图。
图35A至图35E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图35A是等距视图。图35B是沿图35A中的线A-A'截取的截面图。图35C是沿图35A的线B-B’截取的截面图。图35D是沿图35A中的线C-C'截取的截面图。图35E是沿图35A的线D-D’截取的截面图。
图36A至图36E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图36A是等距视图。图36B是沿图36A中的线A-A'截取的截面图。图36C是沿图36A的线B-B’截取的截面图。图36D是沿图36A中的线C-C'截取的截面图。图36E是沿图36A的线D-D’截取的截面图。
图37A至图37E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图37A是等距视图。图37B是沿图37A中的线A-A'截取的截面图。图37C是沿图37A的线B-B’截取的截面图。图37D是沿图37A中的线C-C'截取的截面图。图37E是沿图37A的线D-D’截取的截面图。
图38A至图38E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图38A是等距视图。图38B是沿图38A中的线A-A'截取的截面图。图38C是沿图38A的线B-B’截取的截面图。图38D是沿图38A中的线C-C'截取的截面图。图38E是沿图38A的线D-D’截取的截面图。图38F是沿图38A中的线C-C'截取的另一实施例的截面图。
图39A至图39E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图39A是等距视图。图39B是沿图39A中的线A-A'截取的截面图。图39C是沿图39A的线B-B’截取的截面图。图39D是沿图39A中的线C-C'截取的截面图。图39E是沿图39A的线D-D’截取的截面图。图39F是沿图39A中的线C-C'截取的另一实施例的截面图。
图40A至图40E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图40A是等距视图。图40B是沿图40A中的线A-A'截取的截面图。图40C是沿图40A的线B-B’截取的截面图。图40D是沿图40A中的线C-C'截取的截面图。图40E是沿图40A的线D-D’截取的截面图。
图41A至图41E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图41A是等距视图。图41B是沿图41A中的线A-A'截取的截面图。图41C是沿图41A的线B-B’截取的截面图。图41D是沿图41A中的线C-C'截取的截面图。图41E是沿图41A的线D-D’截取的截面图。
图42A至图42E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图42A是等距视图。图42B是沿图42A中的线A-A'截取的截面图。图42C是沿图42A的线B-B’截取的截面图。图42D是沿图42A中的线C-C'截取的截面图。图42E是沿图42A的线D-D’截取的截面图。
图43A至图43E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图43A是等距视图。图43B是沿图43A中的线A-A'截取的截面图。图43C是沿图43A的线B-B’截取的截面图。图43D是沿图43A中的线C-C'截取的截面图。图43E是沿图43A的线D-D’截取的截面图。
图44A至图44E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图44A是等距视图。图44B是沿图44A中的线A-A'截取的截面图。图44C是沿图44A的线B-B’截取的截面图。图44D是沿图44A中的线C-C'截取的截面图。图44E是沿图44A的线D-D’截取的截面图。
图45A至图45E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图45A是等距视图。图45B是沿图45A中的线A-A'截取的截面图。图45C是沿图45A的线B-B’截取的截面图。图45D是沿图45A中的线C-C'截取的截面图。图45E是沿图45A的线D-D’截取的截面图。
图46A至图46E示出了根据本发明的实施例的制造GAA FET半导体器件的各个阶段之一的视图。图46A是等距视图。图46B是沿图46A中的线A-A'截取的截面图。图46C是沿图46A的线B-B’截取的截面图。图46D是沿图46A中的线C-C'截取的截面图。图46E是沿图46A的线D-D’截取的截面图。
图47A是根据本发明的实施例的半导体器件的平面图。图47B是沿图47A的线E-E'截取的截面图。
图48A是根据本发明的实施例的半导体器件的平面图。图48B是沿图48A的线F-F'截取的截面图。
图49A是根据本发明的实施例的半导体器件的平面图。图49B是沿图49A的线G-G'截取的截面图。
图50A是根据本发明的实施例的半导体器件的平面图。图50B是沿图50A的线H-H'截取的截面图。
图51A是根据本发明的实施例的半导体器件的平面图。图51B是沿图51A的线J-J'截取的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如,元件的尺寸不限于所公开的范围或值,但可能依赖于工艺条件和/或器件所需的性能。此外,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的,各个部件可以以不同的比例任意地绘制。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。另外,术语“由…构成”可以表示“包含”或“由…组成”。在本发明中,除非另有说明,短语“A、B和C之一”表示“A、B和/或C”(A;B;C;A和B;A和C;B和C;或A、B和C),并不意味着来自A的一个元件、来自B的一个元件和来自C的一个元件。
在本发明中,提供了一种用于制造GAA FET和堆叠沟道FET的方法。应注意,在本发明中,源极和漏极可互换使用,并且其结构基本相同。
半导体器件可以包括多个金属轨,包括电源轨,例如正电压轨(VDD)和接地轨(GND);和多条信号线。增加金属轨的数量可以降低芯片上布局和布线的复杂性,并提高芯片的密度。在一些半导体器件中,电源轨和信号线位于有源器件上方的第一金属化层(M0)中。然而,随着半导体器件尺寸的缩小,诸如电源轨和信号线的金属轨的空间减小。因此,同时减小半导体器件尺寸和增加金属轨的数量是一个挑战。
图1至图26E示出了根据本发明的实施例的制造半导体器件的方法。如图1所示,将杂质离子(掺杂剂)12注入硅衬底10中以形成阱区。执行离子注入以防止穿通效应。在一个实施例中,衬底10至少在其表面上包括单晶半导体层。衬底10可以包括单晶半导体材料,例如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在一个实施例中,衬底10由Si制成。
衬底10可在其表面区域中包括一个或多个缓冲层(未示出)。缓冲层可用于逐渐地将晶格常数从衬底的晶格常数改变为源极/漏极区的晶格常数。缓冲层可以由外延生长的单晶半导体材料形成,例如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在特定实施例中,衬底10包括在硅衬底10上外延生长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可从最底部缓冲层的30原子%的锗增加到最顶部缓冲层的70原子%的锗。在本发明的一些实施例中,衬底10包括已经适当地掺杂有杂质(例如,p型或n型导电性)的各种区域。掺杂剂12例如是用于n型FinFET的硼(BF2)和用于p型FinFET的磷。
在图2中,在衬底10上形成由不同材料制成的第一半导体层30和第二半导体层35的交替叠层。在本发明的一些实施例中,第一半导体层30和第二半导体层35由具有不同晶格常数的材料形成,并且包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP的一个或多个层。
在一些实施例中,第一半导体层30和第二半导体层35由Si、Si化合物、SiGe、Ge或Ge化合物形成。在一个实施例中,第一半导体层30是Si1-xGex,其中x大于约0.3,或Ge(x=1.0),第二半导体层35是Si或Si1-yGey,其中y小于约0.4并且x>y。在本发明中,“M化合物”或“M基化合物”表示该化合物的主要部分是M。
在另一实施例中,第二半导体层35是Si1-yGey或Ge,其中y大于约0.3,并且第一半导体层30是Si或Si1-xGex,其中x小于约0.4并且x<y。在其他实施例中,第一半导体层30由Si1-xGex制成,其中x在约0.3至约0.8的范围内,第二半导体层35由Si1-xGex制成,其中x在从约0.1至约0.4的范围内。
图2示出了第一半导体层30和第二半导体层35的五层。然而,层的数量不限于五个,并且在一些实施例中可以小至1(每层一层),或者第一和第二半导体层中的每个2至10层。通过调整堆叠层的数量,可以调整GAA FET器件的驱动电流。
第一半导体层30和第二半导体层35外延地形成在衬底10上。第一半导体层30的厚度可以等于、大于或小于第二半导体层35的厚度,并且在一些实施例中,在约3nm至约40nm的范围内,在其他实施例中,在约3nm至约30nm的范围内,在其它实施例中,在约5nm至约10nm的范围内。在一些实施例中,第二半导体层35的厚度在约2nm至约40nm的范围内,在其他实施例中在约3nm至约30nm的范围内,并且在其他实施例中在约5nm至约10nm的范围内。在一些实施例中,底部第一半导体层30(与衬底10最接近的层)比剩余的第一半导体层30厚。底部第一半导体层30的厚度在一些实施例中在约10nm至约40nm的范围内,或者在其他实施例中,在约10nm至约30nm的范围内。
此外,如图2所示,在堆叠的第一和第二半导体层30、35上形成硬掩模层40。在一些实施例中,硬掩模层40包括第一掩模层45和第二掩模层50。在一些实施例中,第一掩模层45是由氧化硅制成的衬垫氧化物层。第一掩模层45可以通过热氧化形成。在一些实施例中,第二掩模层50由氮化硅制成。第二掩模层50可以通过化学气相沉积(CVD)(包括低压CVD(LPCVD)和等离子体增强CVD(PECVD))、物理气相沉积(PVD)(包括溅射)、原子层沉积(ALD)或其他合适的工艺形成。
通过使用包括光刻和蚀刻的图案化操作将硬掩模层40图案化为掩模图案。接下来,如图3A至图3E所示,通过使用图案化的掩模层图案化第一和第二半导体层30、35的堆叠层和下面的衬底10,从而堆叠层和衬底的一部分形成为在X方向上延伸的鳍结构15。在图3A至图3C中,四个鳍结构15沿Y方向布置。但是鳍结构的数量不限于四个,并且可以小到一个或两个,或者多于四个。在一些实施例中,一个或多个伪鳍结构形成在鳍结构15的两侧上,以改善图案化操作中的图案保真度。如图3A至图3E所示,鳍结构15具有由堆叠的第一和第二半导体层30、35构成的上部25,上部25将形成沟道区;和下部20,下部20是阱区。
在图3A至图26E中,A图是制造半导体器件的顺序操作的等距视图。B图是沿着A图的线A-A'截取的截面图。B图是沿Y方向沿半导体器件的栅极区截取的。C图是沿A图的长线B-B’截取的截面图。C图是沿Y方向沿半导体器件的源极/漏极区截取的。D图是沿着A图的线C-C'截取的截面图。D图是沿X方向沿半导体器件的鳍结构截取的。E图是沿着A图的线D-D'截取的截面图。E图是沿X方向沿栅极切割截取的截面图。
在一些实施例中,鳍结构15的上部25沿Y方向的宽度W1在约4nm至约40nm的范围内,在其他实施例中在约5nm至约30nm的范围内,并且在其他实施例中在约6nm至约20nm的范围内。在一些实施例中,围绕上部25的底部的相邻鳍结构之间的间隔S1在约20nm至约80nm的范围内,并且在其他实施例中在约30nm至约60nm的范围内。在一些实施例中,沿着鳍结构15的Z方向的高度H1在约75nm至约300nm的范围内,并且在其他实施例中在约100nm至约200nm的范围内。
可以通过任何合适的方法图案化堆叠的鳍结构15。例如,可以使用一个或多个光刻工艺来图案化该结构,包括双重图案化或多重图案化工艺。通常,双重图案化或多重图案化工艺组合光刻和自对准工艺,允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上形成牺牲层并使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层,然后可以使用剩余的间隔件来图案化堆叠的鳍结构15。
随后在硬掩模层40、鳍结构15和衬底10上形成绝缘衬垫层55,如图4A至图4E所示。在一些实施例中,绝缘衬垫层55共形地覆盖硬掩模层40、鳍结构15和衬底。在一个实施例中,绝缘衬垫层55由氮化物(例如氮化硅)、氮化硅基材料(例如,SiON、SiCN或SiOCN)或氮化碳制成。绝缘衬垫层55可以通过CVD、LPCVD、PECVD、PVD、ALD或其他合适的工艺形成。在一些实施例中,绝缘衬垫层55的厚度在约1nm至约20nm的范围内。在一些实施例中,绝缘衬垫层的厚度范围为约3nm至约15nm。在一些实施例中,绝缘衬里层55包括两层或多层不同的材料。
在形成绝缘衬垫层55之后,在衬底上形成包括一层或多层绝缘材料的第一绝缘材料层60,使得鳍结构完全嵌入绝缘层中。用于第一绝缘材料层60的绝缘材料可以包括由LPCVD(低压力化学气相沉积)、等离子体CVD或可流动CVD形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、掺氟硅酸盐玻璃(FSG)或低K介电材料。可以在形成绝缘层之后执行退火操作。然后,执行平坦化操作,例如化学机械抛光(CMP)方法和/或回蚀刻方法,使得绝缘衬垫层55的上表面从第一绝缘材料层60露出,如图5A至图5E所示。
然后,如图6A至图6E所示,使第一绝缘材料层60的一部分凹进以形成暴露相邻鳍结构15之间的绝缘衬垫层55的第一凹槽开口65。本发明不限于去除每隔一对相邻的鳍结构之间的第一绝缘材料层60的部分,如图6A至图6C所示。合适的光刻和蚀刻操作用于从鳍结构15之间去除第一绝缘材料层60的部分。
如图7A至图7E所示,随后用第一牺牲材料填充第一凹槽开口65以形成第一牺牲层70。在一些实施例中,在沉积牺牲材料之后执行平坦化操作,例如CMP操作或回蚀刻操作。在一些实施例中,第一牺牲材料是导电的。在一些实施例中,牺牲材料是多晶体硅(多晶硅)、非晶硅、多晶锗或非晶锗。
随后对第一牺牲层70和第一绝缘材料层60进行凹进蚀刻,以暴露鳍结构15的上部沟道区。在一些实施例中,将第一牺牲层70和第一绝缘层60凹进蚀刻成Z方向上的厚度t1在约30nm至约80nm的范围内。在其他实施例中,在凹进蚀刻之后,第一牺牲层70和第一绝缘材料层60在Z方向上的厚度t1为约40nm至约60nm。凹进蚀刻的第一绝缘材料层60也称为隔离绝缘层。随后在鳍结构15上方沉积第二绝缘材料层,填充相邻鳍结构15之间的空间。在沉积第二绝缘材料层之后,例如通过CMP或回蚀刻操作平坦化器件。去除硬掩模层40,对第二绝缘材料层进行凹进蚀刻以暴露鳍结构15的上部沟道区25,并且通过合适的蚀刻操作从鳍结构的上部沟道区25去除绝缘衬垫层55,从而形成第二凹槽开口75。合适的蚀刻操作包括各向异性或各向同性等离子体蚀刻和湿蚀刻技术。第二绝缘材料层80的一部分保留在先前凹进蚀刻的牺牲层70上,如图8A至图8E所示。在一些实施例中,第二绝缘材料层80的剩余部分的厚度t2在约2nm至约20nm的范围内。在一些实施例中,第二绝缘材料层80的在第一牺牲层70上方的剩余部分的厚度t2在约5nm至约15nm的范围内。
在一些实施例中,通过将第一牺牲层70蚀刻至厚度t1以及然后形成完全覆盖鳍结构15的第二绝缘材料层80来形成第二凹槽开口75。执行化学机械抛光以平坦化器件,然后回蚀刻第二绝缘材料层80至覆盖第一牺牲层70的厚度t2。通过适当的蚀刻操作去除硬掩模层40,并且通过适当的蚀刻操作从鳍结构15的上部25去除绝缘衬垫层55。
如图9A至图9E所示,在鳍结构15的上部25上形成牺牲栅极介电层85。随后用导电材料填充第二凹槽开口75以形成牺牲导电层90。在一些实施例中,第二导电层层90是牺牲栅电极层,随后将其去除。
牺牲栅极介电层85包括一层或多层绝缘材料,例如基于氧化硅的材料。在一个实施例中,使用通过CVD形成的氧化硅。在一些实施例中,牺牲栅极介电层85的厚度在约1nm至约5nm的范围内。
牺牲栅极介电层85和牺牲栅电极层90形成牺牲栅极结构。通过在鳍结构上首先毯式沉积牺牲栅极介电层来形成牺牲栅极结构。然后将牺牲栅电极层毯式沉积在牺牲栅极介电层上和鳍结构上,使得鳍结构完全嵌入牺牲栅电极层中。牺牲栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中,牺牲栅电极层的厚度在约100nm至约200nm的范围内。在一些实施例中,牺牲栅电极层经受平坦化操作。使用CVD(包括LPCVD和PECVD)、PVD、ALD或其他合适的工艺沉积牺牲栅极介电层和牺牲栅电极层。随后,在牺牲栅电极层90上形成第一上绝缘层95。第一上绝缘层95可以包括一个或多个层,并且可以通过CVD、PVD、ALD或其他合适的工艺形成。
接下来,使用合适的光刻和蚀刻操作对上绝缘层95执行图案化操作。随后使用合适的蚀刻操作将上绝缘层95中的图案转移到牺牲栅电极层90和牺牲栅极介电层85,如图10A至图10E所示。蚀刻操作形成在Y方向上延伸的开口100,开口100暴露源极/漏极区。蚀刻操作还形成跨越牺牲栅极结构在X方向上延伸的栅极切割开口105。蚀刻操作去除暴露区域中的牺牲栅电极层90和牺牲栅极介电层85,从而留下位于半导体器件的沟道区上面的牺牲栅极结构。牺牲栅极结构包括牺牲栅极介电层85和剩余的牺牲栅电极层90(例如,多晶硅)。
在形成牺牲栅极结构之后,在暴露的鳍结构15和牺牲栅极结构85、90上形成一个或多个侧壁间隔件层110。侧壁间隔件层110以共形方式沉积,因此形成为分别在牺牲栅极结构的垂直表面(例如,侧壁)、水平表面和顶部在上具有基本相等的厚度。在一些实施例中,侧壁间隔件层110的厚度在约2nm至约20nm的范围内,在其他实施例中,侧壁间隔件层的厚度在约5nm至约15nm的范围内。
在一些实施例中,侧壁间隔件层110包括第一侧壁间隔件层和第二侧壁间隔件层。第一侧壁间隔件层可以包括氧化物(例如氧化硅)或任何其他合适的介电材料,第二侧壁间隔件层可以包括Si3N4、SiON和SiCN中的一种或多种或任何其他合适的介电材料。在一些实施例中,第一侧壁间隔件层和第二侧壁间隔件层由不同材料制成,因此可以选择性地蚀刻它们。第一侧壁间隔件层和第二侧壁间隔件层可以通过ALD或CVD或任何其他合适的方法形成。在一些实施例中,侧壁间隔件层110基本上填充栅极切割开口105。
然后,如图11A至图11E所示,对侧壁间隔件层110进行各向异性蚀刻,以去除在上绝缘层95和鳍结构15的源极/漏极区以及第二绝缘材料层80上形成的侧壁间隔件层。如图11D所示,在一些实施例中,各向异性蚀刻操作去除了最上面的第一和第二半导体层30、35的一部分。在一些实施例中,填充在栅极切割开口105中的侧壁间隔件层110未被蚀刻并保留在栅极切割开口105中。
接下来,使用合适的蚀刻操作去除鳍结构15的源极/漏极区中的第一半导体层30。第一半导体层30和第二半导体层35由具有不同蚀刻选择性的不同材料制成。因此,用于第一半导体层30的合适的蚀刻剂基本上不蚀刻第二半导体层35。例如,当第一半导体层30是Si并且第二半导体层35是Ge或SiGe时,第一半导体层30可以使用湿蚀刻剂选择性地去除,湿蚀刻剂例如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液。另一方面,当第一半导体层30是SiGe或Ge并且第二半导体层35是Si时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于HF:HNO3溶液、HF:CH3COOH:HNO3、或H2SO4溶液和HF:H2O2:CH3COOH。在一些实施例中,使用干蚀刻技术和湿蚀刻技术的组合来去除第一半导体层30。
在去除源极/漏极区中的第一半导体层30之后,在侧壁间隔件层110、源极/漏极区中的第二半导体层35、上绝缘层95和第二绝缘材料层80上形成内间隔件层115,如图12A至图12E所示。内间隔件层115以共形方式沉积,并环绕第二半导体层35。在一些实施例中,内间隔件层115的厚度在约3nm至约15nm的范围内,在其他实施例中,内间隔件层115的厚度在约5nm至约12nm的范围内。在一些实施例中,内间隔件层115基本上填充相邻的第二半导体层35之间的空间。在一些实施例中,内间隔件层115包括氧化物(例如氧化硅)或氮化物(例如Si3N4、SiON和SiCN)或任何其他合适的介电材料,包括氧化铝。内间隔件层115可以通过ALD或CVD或任何其他合适的工艺形成。
接下来,使用延伸开口100的适当蚀刻操作对内间隔件层115和第二半导体层35进行凹进蚀刻,如图13A至图13E所示。如图13D所示,在一些实施例中,凹槽蚀刻延伸穿过第二半导体层35。在另一个实施例中,不蚀刻第二半导体层35,并且仅蚀刻内间隔件层115,如图13F所示。图13F是沿图13A的线C-C’截取的截面图。
随后,在开口100中形成源极/漏极外延层120,如图14A至图14E所示。源极/漏极外延层120包括用于n沟道FET的Si、SiP、SiC和SiCP的一个或多个层或用于p沟道FET的Si、SiGe、Ge。对于P沟道FET,硼(B)也可以包含在源极/漏极中。源极/漏极外延层120通过使用CVD、ALD或分子束外延(MBE)的外延生长方法形成。如图14C所示,源极/漏极外延层120生长在鳍结构上。在另一实施例中,源极/漏极外延层120环绕第二半导体层35的暴露部分,如图14F所示。图14F是沿图14A的线C-C’截取的截面图。在一些实施例中,相邻鳍结构上的生长的源极/漏极外延层120彼此合并。在一些实施例中,源极/漏极外延层120的截面具有菱形、六边形、其他多边形或半圆形。
随后,在源极/漏极层120和开口100的侧壁上形成接触蚀刻停止层(CESL)125,然后形成层间介电(ILD)层130,基本上填充源极/漏极区上的开口100,如图15A至图15E所示。在一些实施例中,位于源极/漏极区上面的CESL 125具有约1nm至约15nm的厚度。CESL 125可以包括Si3N4、SiON、SiCN或任何其他合适的材料,并且可以通过CVD、PVD或ALD形成。用于ILD层130的材料包括包含Si、O、C和/或H的化合物,例如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于ILD层130。在形成ILD层130之后,执行诸如化学机械抛光(CMP)的平坦化操作,使得牺牲栅电极层90的顶部部分暴露。CMP还去除侧壁间隔件层110的一部分以及覆盖牺牲栅电极层90的上表面的上绝缘层95。
然后,去除牺牲栅电极层90,从而形成栅极间隔135,其中鳍结构15的沟道区被暴露,如图16A至图16E所示。在去除牺牲栅极结构期间,ILD层130保护源极/漏极外延层120。可以使用等离子体干蚀刻和/或湿蚀刻来去除牺牲栅电极层90。当牺牲栅电极层90是多晶硅并且ILD层130是氧化硅时,可以使用诸如四甲基氢氧化铵(TMAH)溶液的湿蚀刻剂来选择性地去除牺牲栅电极层90。
在去除牺牲栅电极层90之后,使用图案化的光刻胶和/或底部抗反射涂(BARC)层140掩蔽该器件,如图17A至图17E所示。使用合适的光刻技术图案化光刻胶和/或BARC。
使用图案化的光刻胶和/或BARC层140作为掩模,使用合适的蚀刻操作选择性地蚀刻第二绝缘材料层80,如图18A至图18E所示。在一些实施例中,使用基于HF的蚀刻剂或缓冲氧化物蚀刻(NH4F:HF溶液)来选择性地蚀刻氧化硅第二绝缘材料层80。如图18A和18E所示,第二绝缘材料层蚀刻底切侧壁间隔件层110和内间隔件层115,以形成第二绝缘材料层凹槽145。第二绝缘材料层凹槽145提供暴露第一牺牲层70的一部分的开口。
如图19A至图19E所示,随后通过适当的蚀刻操作从鳍结构的阱区20之间的下面去除第一牺牲层70,在第二绝缘材料层80下面形成空隙150。例如,如果第一牺牲层70是多晶硅,则可以使用TMAH溶液去除第一牺牲层70。在其他实施例中,使用NH4OH或KOH溶液去除第一牺牲层70。
如图20A至图20E所示,随后去除图案化的光刻胶和/或BARC层140以形成栅极间隔135'。在一些实施例中,通过合适的光刻胶剥离或等离子体灰化操作去除图案化的光刻胶和/或BARC层140。
然后,在一些实施例中,如图21A至图21E所示,从栅极间隔135'去除牺牲栅极介电层85。可以通过使用合适的等离子体干蚀刻和/或湿蚀刻操作来去除牺牲栅极介电层85。
参照图22A至图22E,使用适当的蚀刻操作在鳍结构15的沟道区25中去除第一半导体层30,以形成由第二半导体层35制成的半导体纳米线。第一半导体层30和第二半导体层35由具有不同蚀刻选择性的不同材料制成。因此,用于第一半导体层30的合适的蚀刻剂基本上不蚀刻第二半导体层35。例如,当第一半导体层30是Si并且第二半导体层35是Ge或SiGe时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液。另一方面,当第一半导体层30是SiGe或Ge并且第二半导体层35是Si时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于HF:HNO3溶液、HF:CH3COOH:HNO3、或H2SO4溶液和HF:H2O2:CH3COOH。在一些实施例中,使用干蚀刻技术和湿蚀刻技术的组合来去除第一半导体层30。
沟道区25中的半导体纳米线35的横截面形状显示为矩形,但可以是任何多边形形状(三角形、菱形等)、具有圆角的多边形形状、圆形或椭圆形(垂直或水平)。
在形成第二半导体层35的半导体纳米线之后,在每个沟道区纳米线35周围形成栅极介电层155,如图22A至图22E所示。在某些实施例中,栅极介电层155包括一层或多层介电材料,例如氧化硅、氮化硅或高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。在一些实施例中,栅极介电层155包括在沟道层和介电材料之间形成的界面层。在一些实施例中,栅极介电层155也形成在第二绝缘材料层80的暴露部分上。
可以通过CVD、ALD或任何合适的方法形成栅极介电层155。在一个实施例中,使用诸如ALD的高度共形沉积工艺形成栅极介电层155,以确保在每个沟道层周围形成具有均匀厚度的栅极介电层。在一些实施例中,栅极介电层155的厚度在约1nm至约6nm的范围内。
在一些实施例中,如图23A至图23E所示,在形成栅极介电层155之后,在栅极间隔135'中的栅极介电层155上方形成栅电极层170。栅电极层170形成在栅极介电层155上以围绕每个纳米线35。在一些实施例中,用于形成栅电极层170的材料还用于在鳍结构15的阱区20之间的空隙150中形成电源轨175。在一些实施例中,同时形成栅电极层170和电源轨175。在其他实施例中,在形成栅电极层170或电源轨175中的另一个之前形成栅电极层170和电源轨175中的一个。
栅电极层170和电源轨175包括一层或多层导电材料,例如铝、铜,钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合。
可以通过CVD、ALD、电镀或其他合适的方法形成栅电极层170和电源轨。在一些实施例中,栅电极层170也沉积在ILD层130的上表面上,然后通过使用例如CMP将在ILD层130上形成的栅电极层的部分平坦化,直到露出ILD层130的顶面。
在本发明的一些实施例中,一个或多个阻挡层160插入在栅极介电层155和栅电极170之间,以及栅极介电层155和绝缘衬垫层55与电源轨175之间。阻挡层160由导电材料制成,例如TiN或TaN的单层或TiN和TaN的多层。
在本发明的一些实施例中,一个或多个功函数调整层165插入在栅极介电层115或阻挡层160与栅电极层170之间,以及栅极介电层115或阻挡层与绝缘衬垫层和电源轨175之间。功函数调整层由导电材料制成,例如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层,或者这些材料中的两种或多种的多层。对于n沟道FET,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函数调整层,对于p沟道FET,TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种用作功函数调整层。功函数调整层可以通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺形成。此外,功函数调整层可以单独形成用于n沟道FET和p沟道FET,n沟道FET和p沟道FET可以使用不同的金属层作为栅电极层170。
随后在ILD层130和栅电极层170上形成金属蚀刻停止层(MESL)180和帽绝缘层185,如图24A至图24E所示。帽绝缘层185形成在MESL180上方。
使用合适的光刻和蚀刻技术在帽绝缘层185中形成接触孔190。通过使用干蚀刻将接触孔延伸到MESL 180和ILD层130中。进一步使用合适的蚀刻操作来将接触孔延伸穿过第二绝缘材料层80以及CESL 125、栅极介电层155、阻挡层160和功函数调整层165中的任何一个,以暴露电源轨175。蚀刻操作还去除覆盖源极/漏极外延层120的CESL 125,从而暴露源极/漏极外延层120。在一些实施例中,还蚀刻源极/漏极外延层120的上部。
在一些实施例中,在包括帽绝缘层185、MESL 180、ILD层130、源极/漏极外延层120和电源轨175的器件上方沉积金属层195,如图25A至图25E所示。在一些实施例中,金属层195是W、Co、Ni、Ti、Mo和Ta的一层或多层。在一些实施例中,金属层195包括金属层,选自W、Co、Ni、Ti、Mo和Ta;金属氮化物层,选自氮化钨、氮化钴、氮化镍、氮化钛、氮化钼和氮化钽。然后对半导体器件进行快速热退火,由此源极/漏极外延层120上方的金属层195的部分与源极/漏极外延层120中的硅反应以形成金属硅化物层200。在一些实施例中,在源/漏极外延层120上形成的金属硅化物层200包括WSi、CoSi、NiSi、TiSi、MoSi和TaSi中的一种或多种。在一些实施例中,金属层195通过CVD、PVD、ALD或其他合适的工艺形成。
然后,在一些实施例中,从接触孔190和帽绝缘层185去除未反应的金属层195,包括金属层和/或金属氮化物层。未反应的金属层195可以通过合适的蚀刻操作去除。在去除未反应的金属层195之后,在接触孔190中形成导电材料以形成导电接触件205,如图26A至图26E所示。导电材料包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。可以通过CVD、ALD、电镀或其他合适的方法形成导电接触件205。在一些实施例中,导电材料也沉积在帽绝缘层185的上表面上,然后通过使用例如CMP将形成在帽绝缘层185上方的导电接触件205的部分平坦化,直到露出帽绝缘层185的顶面。
应理解,根据所公开的方法形成的GAA FET经历进一步的互补金属氧化物半导体(CMOS)工艺以形成各种部件,例如接触件/通孔、互连金属层、介电层、钝化层、具有信号的金属化层线等。
图27A至图46E示出了根据本发明的实施例的制造半导体器件的方法。该方法采用先前关于图1至图5E所公开的相同操作。在图27A至图46E中,A图是制造半导体器件的顺序操作的等距视图。B图是沿着A图的线A-A'截取的截面图。B图是沿Y方向沿半导体器件的栅极区截取的。C图是沿A图的长线B-B’截取的截面图。C图是沿Y方向沿半导体器件的源极/漏极区截取的。D图是沿着A图的线C-C'截取的截面图。D图是沿X方向沿半导体器件的鳍结构截取的。E图是沿着A图的线D-D'截取的截面图。E图是沿X方向沿单元边缘截取的截面图。
从图5A至图5E的结构开始,使第一绝缘材料层60的一部分凹进以形成暴露相邻鳍结构15之间的绝缘衬垫层55的第一凹槽开口65'。本发明不限于如27A至图27E所示的去除第一绝缘材料层60的部分的图案。合适的光刻和蚀刻操作用于从鳍结构15之间去除第一绝缘材料60的部分。
如图28A至图28E所示,各向异性地蚀刻绝缘衬垫层55,以在衬底10的水平表面上去除绝缘衬垫层55的一部分,从而暴露衬底10的表面。在蚀刻操作期间也从鳍结构的上表面去除绝缘衬垫层55。在一些实施例中,各向异性蚀刻是等离子体蚀刻操作。
如图29A至图29E所示,在一些实施例中,在包括鳍结构15、绝缘衬垫层55和衬底10的器件上方沉积金属层210。在一些实施例中,金属层210是W、Co、Ni、Ti、Mo和Ta的一层或多层。在一些实施例中,金属层210包括金属层,选自W、Co、Ni、Ti、Mo和Ta;金属氮化物层,选自氮化钨、氮化钴、氮化镍、氮化钛、氮化钼和氮化钽。然后对半导体器件进行快速热退火,由此衬底10上的金属层210的一部分与衬底10中的硅反应以形成金属硅化物层215。金属硅化物层215为晶种层提供随后的导电材料的选择性沉积。在一些实施例中,在衬底10上形成的金属硅化物层215包括WSi、CoSi、NiSi、TiSi、MoSi和TaSi中的一种或多种。在一些实施例中,金属层210通过CVD、PVD、ALD或其他合适的工艺形成。
然后,在一些实施例中,从鳍结构15和第一绝缘材料层60上方去除包括金属层和/或金属氮化物层的未反应的金属层210,如图30A至图30E所示。可以通过合适的蚀刻操作去除未反应的金属层210。
在去除未反应的金属层210之后,在第一凹槽开口65'中形成导电材料,以形成电源轨175',如图31A至图31E所示。导电材料包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。电源轨175'可以通过CVD、PVD、ALD、电镀或其他合适的方法形成。在一些实施例中,导电材料沉积在鳍结构15的上表面上,然后通过使用例如CMP使导电材料平坦化。随后执行回蚀刻操作,直到导电材料在相邻鳍结构15的相邻阱区20之间减小到所需高度。在其他实施例中,导电材料沉积在第一凹槽开口65'中,直到获得电源轨175'的所需高度为止。
如图32A至图32E所示,随后在的鳍结构15上沉积第二绝缘材料层220,填充第二凹槽开口65'。在沉积第二绝缘材料层220之后,例如通过CMP或回蚀刻操作平坦化器件。
接下来,去除硬掩模层40,凹进蚀刻第二绝缘材料层220以暴露鳍结构15的上部沟道区25,并且通过适当的蚀刻操作从鳍结构的上部沟道区25去除绝缘衬垫层55,从而形成第二凹槽开口225。合适的蚀刻操作包括各向异性或各向同性等离子体蚀刻和湿蚀刻技术。第二绝缘材料层220的一部分保留在先前形成的电源轨175'和第一绝缘材料层60上,如图33A至图33E所示。在一些实施例中,在电源轨175'上的第二绝缘材料层220的剩余部分的厚度范围为从约2nm到约20nm。在一些实施例中,第二绝缘材料层220的剩余部分的厚度在约5nm至约15nm的范围内。
如图34A至图34E所示,在鳍结构的上部25上形成牺牲栅极介电层230。随后用导电材料填充第二凹槽开口225以形成牺牲导电层235。在一些实施例中,第二导电层235是牺牲栅电极层,其随后将被去除。
牺牲栅极介电层230包括一层或多层绝缘材料,例如基于氧化硅的材料。在一个实施例中,使用通过CVD形成的氧化硅。在一些实施例中,牺牲栅极介电层230的厚度在约1nm至约5nm的范围内。
牺牲栅极介电层230和牺牲栅电极层235形成牺牲栅极结构。通过在鳍结构上首先毯式沉积牺牲栅极介电层来形成牺牲栅极结构。然后将牺牲栅电极层毯式沉积在牺牲栅极介电层上和鳍结构上,使得鳍结构完全嵌入牺牲栅电极层中。牺牲栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中,牺牲栅电极层的厚度在约100nm至约200nm的范围内。在一些实施例中,牺牲栅电极层经受平坦化操作。使用CVD(包括LPCVD和PECVD)、PVD、ALD或其他合适的工艺沉积牺牲栅极介电层和牺牲栅电极层。随后,在牺牲栅电极层90上形成第一上绝缘层240。第一上绝缘层240可以通过CVD、PVD、ALD或其他合适的工艺形成。
接下来,使用合适的光刻和蚀刻操作对第一上绝缘层240执行图案化操作。随后使用合适的蚀刻操作将第一上绝缘层240中的图案转移到牺牲栅电极层235和牺牲栅极介电层230,如图35A至图35E所示。蚀刻操作形成在Y方向上延伸的开口245,开口245暴露源极/漏极区。蚀刻操作还形成跨越牺牲栅极结构在X方向上延伸的栅极切割开口250。蚀刻操作去除暴露区域中的牺牲栅电极层235和牺牲栅极介电层230,从而留下位于半导体器件的沟道区上面的牺牲栅极结构。牺牲栅极结构包括牺牲栅极介电层230、剩余的牺牲栅电极层235(例如,多晶硅)。
在形成牺牲栅极结构之后,在暴露的鳍结构15和牺牲栅极结构230、235上方形成一个或多个侧壁间隔件层255,如图36A至图36E所示。在一些实施例中,侧壁间隔件层255以共形方式沉积,以便形成为在牺牲栅极结构的垂直表面(例如侧壁)、水平表面和顶部上分别具有基本相等的厚度。在一些实施例中,侧壁间隔件层255的厚度在约2nm至约20nm的范围内,在其他实施例中,侧壁间隔件层255的厚度在约5nm至约15nm的范围内。
在一些实施例中,侧壁间隔件层255包括第一侧壁间隔件层和第二侧壁间隔件层。第一侧壁间隔件层可以包括氧化物(例如氧化硅)或任何其他合适的介电材料,第二侧壁间隔件层可以包括Si3N4、SiON和SiCN中的一种或多种或任何其他合适的介电材料。在一些实施例中,第一侧壁间隔件层和第二侧壁间隔件层由不同材料制成,因此可以选择性地蚀刻它们。第一侧壁间隔件层和第二侧壁间隔件层可以通过ALD或CVD或任何其他合适的方法形成。在一些实施例中,侧壁间隔件层255基本上填充栅极切口250。然后,如图36A至图36E所示,对侧壁间隔件层225进行各向异性蚀刻,以去除在第一上绝缘层240和鳍结构15的源极/漏极区以及第二绝缘材料层220上形成的侧壁间隔件层。在一些实施例中,通过适当的蚀刻操作去除侧壁间隔件层255的上部以暴露第一上绝缘层240的一部分。如图36D所示,在一些实施例中,最上面的第一半导体层30和第二半导体层35的一部分可以在蚀刻操作期间被去除。
接下来,使用合适的蚀刻操作去除鳍结构15的源极/漏极区中的第一半导体层30,如图37A至图37E所示。第一半导体层30和第二半导体层35由具有不同蚀刻选择性的不同材料制成。因此,用于第一半导体层30的合适的蚀刻剂基本上不蚀刻第二半导体层35。例如,当第一半导体层30是Si并且第二半导体层35是Ge或SiGe时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液。另一方面,当第一半导体层30是SiGe或Ge并且第二半导体层35是Si时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于HF:HNO3溶液,HF:CH3COOH:HNO3或H2SO4溶液和HF:H2O2:CH3COOH。在一些实施例中,使用干蚀刻技术和湿蚀刻技术的组合来去除第一半导体层30。
在去除源极/漏极区中的第一半导体层30之后,在侧壁间隔件层255、源极/漏极区中的第二半导体层35、第一上绝缘层240和第二绝缘材料层220上形成内间隔件层260,如图37A至图37E所示。内间隔件层260以共形方式沉积,并环绕第二半导体层35。在一些实施例中,内间隔件层260的厚度在约2nm至约20nm的范围内,在其他实施例中,内间隔件层260的厚度在约5nm至约15nm的范围内。在一些实施例中,内间隔件层260基本上填充相邻的第二半导体层35之间的空间。在一些实施例中,内间隔件层260包括氧化物(例如氧化硅)或氮化物(例如Si3N4、SiON和SiCN)或任何其他合适的介电材料,包括氧化铝。内间隔件层260可以通过ALD或CVD或任何其他合适的工艺形成。
接下来,使用延伸开口245的合适的蚀刻操作对内间隔件层260和第二半导体层35进行凹进蚀刻,如图38A至图38E所示。如图38D所示,在一些实施例中,凹槽蚀刻延伸穿过第二半导体层35。在另一个实施例中,不蚀刻第二半导体层35,并且仅蚀刻内间隔件层260,如图38F所示。图38F是沿图38A的线C-C’截取的截面图。
随后,在开口245中形成源极/漏极外延层265,如图39A至图39E所示。源极/漏极外延层265包括用于n沟道FET的Si、SiP、SiC和SiCP的一个或多个层或用于p沟道FET的Si、SiGe、Ge。对于P沟道FET,硼(B)也可以包含在源极/漏极中。源极/漏极外延层265通过使用CVD、ALD或分子束外延(MBE)的外延生长方法形成。如图39C所示,源极/漏极外延层265生长在鳍结构上。在另一实施例中,源极/漏极外延层265环绕第二半导体层35,如图39F所示。图39F是沿图39A的线C-C’截取的截面图。在一些实施例中,相邻鳍结构上的生长的源极/漏极外延层265彼此合并。在一些实施例中,源极/漏极外延层265的横截面具有菱形、六边形、其他多边形或半圆形。
随后,在源极/漏极外延层265和开口245的侧壁上形成接触蚀刻停止层(CESL)270,然后形成层间介电(ILD)层275,基本上填充源极/漏极区上的开口245,如图40A至图40E所示。在一些实施例中,位于源极/漏极区上面的CESL 270具有约1nm至约15nm的厚度。CESL 270可以包括Si3N4、SiON、SiCN或任何其他合适的材料,并且可以通过CVD、PVD或ALD形成。用于ILD层275的材料包括包含Si、O、C和/或H的化合物,例如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于ILD层275。在形成ILD层275之后,执行诸如化学机械抛光(CMP)的平坦化操作,使得牺牲栅电极层235的顶部暴露。CMP还去除侧壁间隔件层255的一部分以及覆盖牺牲栅电极层235的上表面的上绝缘层240。
然后,去除牺牲栅电极层235和牺牲栅极介电层230,从而形成栅极间隔280,其中鳍结构15的沟道区25被暴露,如图41A至图41E所示。在去除牺牲栅极结构期间,ILD层275保护源极/漏极外延层265。可以使用等离子体干蚀刻和/或湿蚀刻来去除牺牲栅电极层235和牺牲栅极介电层230。当牺牲栅电极层235是多晶硅并且ILD层275是氧化硅时,可以使用诸如四甲基氢氧化铵(TMAH)溶液的湿蚀刻剂来选择性地去除牺牲栅电极层235。
如图42A至图42E所示,使用适当的蚀刻操作在鳍结构15的沟道区25中去除第一半导体层30,以形成由第二半导体层35制成的半导体纳米线。第一半导体层30和第二半导体层35由具有不同蚀刻选择性的不同材料制成。因此,用于第一半导体层30的合适的蚀刻剂基本上不蚀刻第二半导体层35。例如,当第一半导体层30是Si并且第二半导体层35是Ge或SiGe时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于氢氧化铵(NH4OH)四甲基氢氧化铵(TMAH)乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液。另一方面,当第一半导体层30是SiGe或Ge并且第二半导体层35是Si时,可以使用湿蚀刻剂选择性地去除第一半导体层30,湿蚀刻剂例如但不限于HF:HNO3溶液,HF:CH3COOH:HNO3或H2SO4溶液和HF:H2O2:CH3COOH。在一些实施例中,使用干蚀刻技术和湿蚀刻技术的组合来去除第一半导体层30。
沟道区25中的半导体纳米线35的横截面形状显示为矩形,但可以是任何多边形形状(三角形、菱形等)、具有圆角的多边形形状、圆形或椭圆形(垂直或水平)。
在形成第二半导体层35的半导体纳米线之后,在每个沟道区纳米线35周围形成栅极介电层285,如图42A至图42E所示。在某些实施例中,栅极介电层285包括一层或多层介电材料,例如氧化硅、氮化硅或高k介电材料其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。在一些实施例中,栅极介电层285包括在沟道层和介电材料之间形成的界面层。在一些实施例中,栅极介电层285也形成在第二绝缘材料层220的暴露部分上。
可以通过CVD、ALD或任何合适的方法形成栅极介电层285。在一个实施例中,使用诸如ALD的高度共形沉积工艺形成栅极介电层285,以确保在每个沟道层周围形成具有均匀厚度的栅极介电层。在一些实施例中,栅极介电层285的厚度在约1nm至约6nm的范围内。
在一些实施例中,如图43A至图43E所示,在形成栅极介电层285之后,在栅极间隔280中的栅极介电层285上方形成栅电极层300。栅电极层300形成在栅极介电层285上以围绕每个纳米线35。在一些实施例中,用于形成栅电极层300的材料与用于形成电源轨175'的材料相同。
栅电极层300包括一层或多层导电材料,例如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合。
可以通过CVD、ALD、电镀或其他合适的方法形成栅电极层300。在一些实施例中,栅电极层300也沉积在ILD层275的上表面上,然后通过使用例如CMP将在ILD层275上形成的栅电极层的部分平坦化,直到露出ILD层275的顶面。
在本发明的一些实施例中,一个或多个阻挡层290插入在栅极介电层285和栅电极层300之间。阻挡层290由导电材料制成,例如TiN或TaN的单层或TiN和TaN的多层。
在本发明的一些实施例中,一个或多个功函数调整层295插入在栅极介电层285或阻挡层290与栅电极层300之间。功函数调整层由导电材料制成,例如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层,或这些材料中的两种或多种的多层。对于n沟道FET,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函数调整层,对于p沟道FET,TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种用作功函数调整层。功函数调整层可以通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺形成。此外,功函数调整层可以单独形成用于n沟道FET和p沟道FET,n沟道FET和p沟道FET可以使用不同的金属层作为栅电极层300。
随后在ILD层275和栅电极层300上形成金属蚀刻停止层(MESL)305和帽绝缘层310,如图44A至图44E所示。帽绝缘层310形成在MESL305上方。
使用合适的光刻和蚀刻技术在帽绝缘层310中形成接触孔315。通过使用干蚀刻将接触孔315延伸到MESL 305和ILD层275中。合适的蚀刻操作还用于使接触孔延伸穿过第二绝缘材料层220,以及CESL 270、栅极介电层285、阻挡层290和功函数调整层295中的任何一个,以暴露电源轨175'。蚀刻操作还去除覆盖源/漏极外延层265的CESL 270,从而暴露源/漏极外延层265。在一些实施例中,还蚀刻源极/漏极外延层265的上部。
在一些实施例中,在包括帽绝缘层310、MESL 305、ILD层275、源极/漏极外延层265和电源轨175'的器件上沉积金属层320,如图45A至图45E所示。在一些实施例中,金属层320是W、Co、Ni、Ti、Mo和Ta的一层或多层。在一些实施例中,金属层320包括金属层,选自W、Co、Ni、Ti、Mo和Ta;金属氮化物层,选自氮化钨、氮化钴、氮化镍、氮化钛、氮化钼和氮化钽。然后对半导体器件进行快速热退火,由此源极/漏极外延层265上方的金属层320的部分与源极/漏极外延层265中的硅反应以形成金属硅化物层340。在一些实施例中,在源/漏极外延层265上形成的金属硅化物层340包括WSi、CoSi、NiSi、TiSi、MoSi和TaSi中的一种或多种。
然后,在一些实施例中,从接触孔315和帽绝缘层310去除包括金属层和/或金属氮化物层的未反应的金属层320。可以通过合适的蚀刻操作去除未反应的金属层320。在去除未反应的金属层320之后,在接触孔315中形成导电材料以形成导电接触件325,如图46A至图46E所示。导电材料包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。导电接触件325可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,导电材料也沉积在帽绝缘层310的上表面上,然后通过使用例如CMP将形成在帽绝缘层310上方的导电接触件325的部分平坦化,直到露出帽绝缘层310的顶面。
图47A至图51B示出了可以根据所公开的制造半导体器件的方法形成的半导体器件结构的若干实施例。
图47A是根据本发明的实施例的半导体器件的平面图。图47B是沿图47A的线E-E'截取的截面图,并且示出了信号线335在有源器件上面的金属化层355中的放置。
图47A是根据本发明的实施例的半导体器件的示意性平面图,示出了电源轨175、信号线335、栅电极170和鳍结构15的相对布置。如图47A和图47B所示,包括嵌入绝缘层330中的信号线335的金属化层355形成在半导体器件有源区上面。可以通过合适的光刻、蚀刻和材料沉积操作来形成金属化层。绝缘层330可以由氧化硅、氮化硅、氧化硅基材料或氮化硅基材料制成。可以通过CVD、PVD、ALD或其他合适的方法形成绝缘层330。信号线335包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。信号线335可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,信号线335包括W或Cu。如图47B所示,金属化层355示出为直接位于栅电极层170上方,然而,在一些实施例中,附加层位于栅电极层170和金属化层355之间。
电源轨175位于相邻鳍结构15的阱区20之间。电源轨175中的一个是正电压轨(VDD),另一个是接地轨(GND)。通过将电源轨定位在鳍结构15的下部20之间的半导体器件的有源区下方,可以在半导体器件的有源区上面形成附加信号线335。例如,如果电源轨与信号线位于同一层,则可能只有三条信号线的空间。然而,通过将电源轨定位在有源区下方,可以提供四条信号线而不是仅提供三条信号线。
在本发明的一些实施例中,互补金属氧化物半导体场效应晶体管(CMOSFET)提供有形成在同一衬底10上的pFET和nFET。如图所示,pFET和nFET包括六条纳米线35的叠层,但是本发明不限于六条纳米线的堆叠结构。pFET和nFET鳍结构15由绝缘层60隔开,绝缘层60也称为浅沟槽隔离(STI)。纳米线35在横截面中显示为圆形,但是本发明不限于圆形横截面纳米线。纳米线35的厚度(直径)D1、D2在一些实施例中在约2nm至约40nm的范围内,在其他实施例中在约3nm至约30nm的范围内,并且在其他实施例中在约5nm至约10nm的范围内。在一些实施例中,纳米线间隔开约2nm至约40nm的距离S2,在其他实施例中,在约3nm至约30nm的范围内,并且在其他实施例中,在约5nm至约10nm的范围内。在一些实施例中,纳米线堆叠件的高度H2在约20nm至约100nm的范围内,在其他实施例中,高度在约40nm至约80nm的范围内。在一些实施例中,相邻纳米线堆叠件之间的间隔S4在约20nm至约80nm的范围内,并且在其他实施例中,在约30nm至约60nm的范围内。在一些实施例中,纳米线堆叠件与栅电极170的边缘间隔开距离S3,距离S3在约5nm至约50nm的范围内,并且在其他实施例中在约10nm至约40nm的范围内。
在一些实施例中,栅电极170的底部位于相邻鳍结构15之间的衬底10中的凹槽的底部约20nm至约100nm的高度H3处,在其他实施例中,栅电极170的底部的高度H3位于约40nm至约80nm的高度H3处。
在一些实施例中,电源轨175通过绝缘层80与栅电极170分离,绝缘层80具有范围从大约2nm到大约20nm的高度H4,并且在其他实施例中高度H4的范围为从约5nm到约15nm。电源轨175通过绝缘衬垫层55与鳍结构15的侧壁分离,在一些实施例中,绝缘衬垫层55的厚度为约1nm至约20nm,在其他实施例中厚度为约3nm至约15nm。在一些实施例中,电源轨175和鳍结构15之间的绝缘衬垫层55的厚度为约2nm至约5nm。
在一些实施例中,信号线335的高度H5在约5nm至约50nm的范围内,并且在另一个实施例中在约10nm至约25nm的范围内。在一些实施例中,信号线的宽度W2在约3nm至约40nm的范围内,并且在另一个实施例中在约8nm至约20nm的范围内。在一些实施例中,信号线335彼此间隔开距离S8,该距离S8在约5nm至约50nm的范围内,并且在另一个实施例中在约10nm至约25nm的范围内。
图48A是根据本发明的实施例的半导体器件的平面图。图48B是沿着图48A的栅电极170上面的线F-F'截取的截面图,并且示出了信号线335在有源器件上面的金属化层355中的放置。
图48A是根据本发明的实施例的半导体器件的示意性平面图,示出了电源轨175、信号线335、栅电极170、鳍结构15和导电接触件205的相对布置。如图48A和图48B所示,在半导体器件有源区上形成包括嵌入绝缘层330中的信号线335的金属化层。可以通过合适的光刻、蚀刻和材料沉积操作来形成金属化层355。绝缘层330可以由氧化硅、氮化硅、氧化硅基材料或氮化硅基材料制成。可以通过CVD、PVD、ALD或其他合适的方法形成绝缘层330。信号线335包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。信号线335可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,信号线335包括W或Cu。如图48B所示,金属化层355示出为直接位于栅电极层170上方,然而,在一些实施例中,附加层位于栅电极层170和金属化层355之间。
电源轨175位于相邻鳍结构15的阱区20之间。电源轨175中的一个是正电压轨(VDD),另一个是接地轨(GND)。通过将电源轨定位在鳍结构15的下部20之间的半导体器件的有源区下方,可以在半导体器件的有源区上面形成附加信号线335。例如,如果电源轨与信号线位于同一层,则可能只有三条信号线的空间。然而,通过将电源轨定位在有源区下方,可以提供四条信号线而不是仅提供三条信号线。
在一些实施例中,提供CMOSFET,其中纳米线堆叠件中的一个是pFET而另一个纳米线堆叠件是形成在同一衬底10上的nFET。pFET和nFET鳍结构15由STI 60和栅电极170中的间隙350分开,如图48A和图48B所示。在一些实施例中,导电接触件205是与电源轨175和栅电极170接触的导电通孔。因此,在这些实施例中,nFET和pFET通常是截止的。导电接触件205由包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种的导电材料形成。在一些实施例中,导电接触件205由W或Cu制成。在一些实施例中,导电接触件205是将电源轨175连接到金属化层355的导电通孔。在一些实施例中,导电接触件205是将电源轨175连接到金属化层355中的信号线335的导电通孔。
图49A是根据本发明的实施例的半导体器件的平面图。图49B是沿着图49A的源极/漏极区上面的线G-G'截取的截面图,并且示出了信号线335在有源器件上面的金属化层中的放置。
图49A是根据本发明的实施例的半导体器件的示意性平面图,示出了电源轨175、信号线335、栅电极170、鳍结构15和导电接触件205的相对布置。如图49A和图49B所示,在半导体器件有源区上面形成包括嵌入绝缘层330中的信号线335的金属化层355。可以通过合适的光刻、蚀刻和材料沉积操作来形成金属化层。绝缘层330可以由氧化硅、氮化硅、氧化硅基材料或氮化硅基材料制成。可以通过CVD、PVD、ALD或其他合适的方法形成绝缘层330。信号线335包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。信号线335可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,信号线335包括W或Cu。在一些实施例中,附加层位于导电接触件205和金属化层355之间。
电源轨175位于相邻鳍结构15的阱区20之间。电源轨175中的一个是正电压轨(VDD),另一个是接地轨(GND)。通过将电源轨定位在鳍结构15的下部20之间的半导体器件的有源区下方,可以在半导体器件的有源区上面形成附加信号线335。通过将电源轨定位在有源区下方,可以提供四条信号线而不是仅提供三条信号线。
在一些实施例中,导电接触件205经由硅化物层200连接到源极/漏极外延层120。图49B中的箭头示出了从源极/漏极外延层120到电源轨175的电子流动。在一些实施例中,介电层位于源极/漏极外延层120和导电接触件之间,并且电流通过隧穿流动。在一些实施例中,相应nFET和pFET源极/漏极的纳米线堆叠件分开的距离S5为约20nm至约80nm,并且在其他实施例中为约30nm至约60nm。
图50A是根据本发明的实施例的半导体器件的平面图。图50B是沿着图50A的源极/漏极上面的线H-H'截取的截面图,并且示出了信号线335在有源器件上面的金属化层中的放置。
图50A是根据本发明的实施例的半导体器件的示意性平面图,示出了电源轨175、信号线335、335'、栅电极170、鳍结构15和导电接触件205的相对布置。如图50A和图50B所示,在半导体器件有源区上面以及鳍结构15的阱区20之间形成包括嵌入在绝缘层330中的信号线335的金属化层355。金属化层355可以通过合适的光刻、蚀刻和材料沉积操作形成。绝缘层330可以由氧化硅、氮化硅、氧化硅基材料或氮化硅基材料制成。可以通过CVD、PVD、ALD或其他合适的方法形成绝缘层330。信号线335、335'包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。信号线335、335'可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,信号线335、335'包括W或Cu。在一些实施例中,附加层位于导电接触件205和金属化层355之间。
电源轨175位于相邻鳍结构15的阱区20之间。电源轨175中的一个是正电压轨(VDD),另一个是接地轨(GND)。通过将电源轨175和信号线335定位在鳍结构15的下部20之间的半导体器件的有源区下方,可以在半导体器件的有源区上面形成附加信号线335。例如,如果电源轨与信号线位于同一层,则可能只有三条信号线的空间。然而,通过将电源轨和附加信号线335'定位在有源区下方,可以提供五条信号线而不是仅提供三条信号线。位于鳍结构15的下部区域20之间的信号线335'通过绝缘衬垫层55与鳍结构分离。
在一些实施例中,提供CMOSFET,其中纳米线堆叠件中的一个是pFET而另一个纳米线堆叠件是形成在同一衬底10上的nFET。在一些实施例中,pFET和nFET的源极/漏极共享公共导电接触件205,如图50B所示,其中公共导电接触件205还接触设置在相邻鳍结构15的下部20之间的信号线335。在一些实施例中,相应nFET和pFET源极/漏极的纳米线堆叠件相隔距离S6,距离S6在一些实施例中为约20nm至约80nm,在其他实施例中为约30nm至约60nm。
图51A是根据本发明的实施例的半导体器件的平面图。图51B是沿着图51A的源极/漏极上面的线J-J'截取的截面图,并且示出了信号线335在有源器件的金属化层中的放置。
图51A是根据本发明的实施例的半导体器件的示意性平面图,示出了电源轨175、信号线335、栅电极170、鳍结构15和导电接触件205的相对布置。如图51A和图51B所示,在半导体器件有源区上方以及鳍结构15的阱区20之间形成包括嵌入绝缘层330中的信号线335的金属化层355。金属化层可以通过合适的光刻、蚀刻和材料沉积操作形成。绝缘层330可以由氧化硅、氮化硅、氧化硅基材料或氮化硅基材料制成。可以通过CVD、PVD、ALD或其他合适的方法形成绝缘层330。信号线335包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。信号线335可以通过CVD、ALD、电镀或其他合适的方法形成。在一些实施例中,信号线335包括W或Cu。在一些实施例中,附加层位于导电接触件205和金属化层355之间。
电源轨175位于相邻鳍结构15的阱区20之间。电源轨175中的一个是正电压轨(VDD),另一个是接地轨(GND)。通过将电源轨175定位在鳍结构15的下部20之间的半导体器件的有源区下方,可以在半导体器件的有源区上面形成附加信号线335。例如,如果电源轨与信号线位于同一层,则可能只有三条信号线的空间。然而,通过将电源轨175定位在有源区下方,可以提供四条信号线而不是仅提供三条信号线。
在一些实施例中,提供CMOSFET,其中纳米线堆叠件中的一个是pFET而另一个纳米线堆叠件是形成在同一衬底10上的nFET。在一些实施例中,源极/漏极绝缘层360形成在鳍结构15的下部20和nFET和pFET的源极/漏极外延层120,如图51B所示。在一些实施例中,源极/漏极绝缘层360由氧化物或氮化物形成为约2nm至约20nm的厚度。在其他实施例中,源极/漏极绝缘层360的厚度在约5nm至约10nm的范围内。在包括源极/漏极绝缘层360的实施例中,电源轨175和鳍结构15之间的绝缘衬垫层55不是必需的。因此,可以增加电源轨175的横截面积并且可以减小器件的总电阻。参考标号345表示CMOSFET阱PN结。在一些实施例中,相应nFET和pFET源极/漏极的纳米线堆叠件分隔开距离S7,在一些实施例中,距离S7为约20nm至约80nm,并且在其他实施例中为约30nm至约60nm。
应当理解,根据所公开的方法形成的GAA FET经历进一步的CMOS工艺以形成各种部件,例如接触件/通孔、互连金属层、介电层、钝化层、具有信号线的金属化层等。
根据本发明的半导体器件和制造半导体器件的方法提供了增加数量的金属轨,从而降低了芯片上的布局和布线的复杂性,并且在不增加半导体器件的尺寸的情况下提高了芯片的密度。在一些实施例中,根据本发明的器件在芯片上增加了约12%至约14%的器件密度。根据本发明的器件和制造方法还提供了横截面积增大的电源轨和信号线,从而降低了器件的电阻。此外,根据本发明的器件和制造方法在电源轨和栅电极之间、电源轨和源极/漏极之间以及信号线和源极/漏极之间提供直接的低电阻接触,从而减小器件的电阻。
本发明的实施例是一种制造半导体器件的方法,包括:在半导体衬底上形成沿第一方向延伸的多个鳍结构。每个鳍结构包括靠近半导体衬底的第一区域和远离半导体衬底的第二区域。在第一相邻鳍结构对的第一区域之间形成导电层。在鳍结构的第二区域上方形成沿与第一方向基本垂直的第二方向延伸的栅电极结构,并且在栅电极结构上形成包括至少一条导线的金属化层。在一个实施例中,形成多个鳍结构包括在鳍结构的第二区域中形成纳米线结构。在一个实施例中,形成栅电极结构包括在纳米线结构的至少一条导线上形成栅极介电层;以及在所述栅极介电层上形成栅电极层,其中所述栅极介电层和所述栅电极层环绕所述纳米线结构的至少一条导线。在一个实施例中,形成导电层包括:在多个相邻的鳍结构对之间形成绝缘材料层,从至少一对相邻鳍结构之间去除绝缘材料层,以及在去除绝缘材料层之后,在至少一对相邻的鳍结构之间形成导电层。在一个实施例中,该方法包括在金属化层与栅电极结构和鳍结构之间形成第一绝缘层。在一个实施例中,该方法包括在第一绝缘层中形成导电通孔,其中导电通孔连接导电层和金属化层。在一个实施例中,该方法包括形成第二绝缘层,该第二绝缘层填充第二相邻鳍结构对之间的空间,其中没有形成导电层。在一个实施例中,该方法包括在导电层和第一相邻鳍结构对的第一区域之间形成第三绝缘层。在一个实施例中,该方法包括在导电层和栅电极结构之间形成第四绝缘层。
本发明的另一实施例是一种制造半导体器件的方法,包括在半导体衬底上形成具有第一组分的第一半导体层,以及在第一半导体层上形成具有第二组分的第二半导体层。在第二半导体层上形成具有第一组分的另一第一半导体层,在另一第一半导体层上形成具有第二组分的另一第二半导体层。图案化第一半导体层、第二半导体层和半导体衬底以形成沿第一方向延伸的多个鳍结构。鳍结构包括与半导体衬底相邻的第一区域和包括第一半导体层和第二半导体层的第二区域。第二区域包括在一对第二部分之间沿第一方向延伸的第一部分。在鳍结构上形成绝缘衬垫层,并且在鳍结构之间形成隔离绝缘层。从第一对相邻鳍结构之间去除隔离绝缘层。在第一对相邻鳍结构之间形成第一导电层。从鳍结构的第一区域去除绝缘衬垫层。从鳍结构的第二区域的第一部分去除第一半导体层,从而形成包括第二半导体层的纳米线。在围绕纳米线的鳍结构的第一部分上形成介电层和第二导电层,从而形成在基本垂直于第一方向的第二方向上延伸的栅电极结构。在栅电极结构上形成包括多条导线的金属化层。在一个实施例中,在形成金属化层之前,在栅电极结构上形成层间介电层。在一个实施例中,该方法包括在金属化层和第一导电层之间的层间介电层中形成导电通孔。在一个实施例中,该方法包括在鳍结构的第一部分上方形成介电层和第二导电层之前:在围绕纳米线的鳍结构的第一部分上方形成牺牲栅极介电层,形成围绕牺牲栅极介电层的牺牲栅电极层,以及去除牺牲栅极介电层和牺牲栅电极层。
本发明的另一实施例是一种制造半导体器件的方法,包括:在半导体衬底上形成沿第一方向延伸的多个鳍结构。每个鳍结构包括与半导体衬底相邻的第一区域和位于第一区域上面的第二区域,并且每个鳍结构包括沿第一方向延伸的位于一对第二部分之间的第一部分。在第一相邻鳍结构对的第一区域之间形成隔离绝缘区。在第二相邻鳍结构对的第一区域之间形成导电层。在鳍结构的第二区域的第一部分上形成沿基本垂直于第一方向的第二方向延伸的栅电极结构。源极/漏极区形成在鳍结构的第二区域的第二部分上。在栅电极结构上方形成层间介电层,以及在层间介电层上形成至少一条导线。在一个实施例中,该方法包括在形成导电层之前,在鳍结构上形成绝缘衬垫层。在一个实施例中,形成多个鳍结构包括形成由第一半导体材料制成的第一半导体层和由第二半导体材料制成的第二半导体层的交替叠层,其中第一半导体材料和第二半导体材料是不同的材料。在一个实施例中,该方法包括在形成第一栅电极结构之前,去除鳍结构的第一部分中的第一半导体层。在一个实施例中,该方法包括在层间介电层中形成与源极/漏极区和导电层接触的导电通孔。在一个实施例中,该方法包括在源极/漏极区上方形成接触层。在一个实施例中,该方法包括在形成源极漏极/区域之前,在鳍结构的第二部分上形成源极/漏极绝缘层。
本发明的另一实施例是一种半导体器件,包括:沿第一方向延伸的多个鳍结构,所述多个鳍结构设置在半导体衬底上。每个鳍结构包括靠近半导体衬底的第一区域和远离半导体衬底的第二区域。至少一个第一导电层设置在相邻的一对鳍的第一区域之间。至少一个栅电极结构在基本垂直于第一方向的第二方向上延伸并且设置在鳍结构的第二区域的第一部分上,并且包括至少一条导线的金属化层设置在栅电极结构上方。在一个实施例中,鳍结构的第二区域包括纳米线结构,该纳米线结构包括多条纳米线的堆叠件,每条纳米线基本上平行于相邻的纳米线延伸。在一个实施例中,栅电极结构包括栅极介电层和栅电极层,其中栅极介电层和栅电极层环绕每条纳米线。在一个实施例中,第一导电层包括电源轨和接地轨。在一个实施例中,导电通孔将第一导电层连接到金属化层。在一个实施例中,第一绝缘层设置在第一导电层和鳍结构之间。在一个实施例中,源极/漏极设置在鳍结构的第二区域的第二部分上,并且导电接触件连接至少一个第一导电层和源极/漏极。在一个实施例中,第二绝缘层填充一对相邻的鳍结构之间的空间,其中没有形成导电层。在一个实施例中,第三绝缘层设置在导电层和栅电极结构之间。在一个实施例中,源极/漏极区设置在栅电极结构的相对侧上并且位于鳍结构的第一区域上方。在一个实施例中,接触层设置在源极/漏极区上。在一个实施例中,第四绝缘层设置在鳍结构的第一区域和源极/漏极区之间。在一个实施例中,金属化层包括多条信号线。在一个实施例中,下部信号线设置在相邻的鳍结构的第一区域之间,其中没有形成第一导电层。在一个实施例中,导电通孔将下部信号线与金属化层连接。
本发明的另一实施例是一种半导体器件,包括:沿第一方向延伸的多个鳍结构,所述多个鳍结构设置在半导体衬底上。每个鳍结构包括下部阱区和位于阱区上方的上部沟道区。沟道区包括基本平行于阱区延伸的一条或多条纳米线。栅电极结构在基本垂直于第一方向的第二方向上延伸并且设置在沟道区上方,并且栅电极结构环绕一条或多条纳米线。至少一个第一导电层设置在沿第一方向延伸的相邻鳍的沟道区之间。多个第二导电层设置在沿第一方向延伸的栅电极结构上方。在一个实施例中,绝缘衬垫层设置在阱区和第一导电层之间。在一个实施例中,导电通孔设置在第一导电层和第二导电层之间。
本发明的另一实施例是一种半导体器件,包括:沿第一方向延伸的多个鳍结构,所述多个鳍结构设置在半导体衬底上。每个鳍结构包括阱区和设置在阱区上方的纳米线堆叠件。纳米线堆叠件包括在第一方向上基本上彼此平行延伸的多条纳米线。栅电极结构在基本垂直于第一方向的第二方向上延伸并且设置在纳米线堆叠件上方,并且栅电极结构环绕每条纳米线。电源轨沿第一方向延伸,设置在第一对相邻鳍结构的阱区之间。接地轨沿第一方向延伸,设置在第二对相邻鳍结构的阱区之间,并且多条信号线设置在沿第一方向延伸的栅电极结构上。在一个实施例中,绝缘层设置在位于第一对鳍结构和第二对鳍结构之间的第三对鳍结构之间。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并且不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
应当理解,并非所有优点都必须在本文中讨论,没有特定的优点是所有实施例或示例都需要的,并且其他实施例或示例可以提供不同的优点。
Claims (20)
1.一种制造半导体器件的方法,包括:
在半导体衬底上形成沿第一方向延伸的多个鳍结构,其中,每个所述鳍结构包括靠近所述半导体衬底的第一区域和远离所述半导体衬底的第二区域;
在第一相邻鳍结构对的所述第一区域之间形成导电层;
在所述鳍结构的所述第二区域上方形成沿与所述第一方向垂直的第二方向延伸的栅电极结构,其中,所述栅电极结构包括栅极介电层和设置所述栅极介电层上的栅电极层;以及
在所述栅电极结构上形成包括至少一条导线的金属化层,其中,所述导电层沿着从所述半导体衬底延伸到所述金属化层的方向设置在所述半导体衬底和所述栅极介电层之间。
2.根据权利要求1所述的方法,其中,形成多个鳍结构包括在所述鳍结构的所述第二区域中形成纳米线结构。
3.根据权利要求2所述的方法,其中,形成所述栅电极结构包括:
在所述纳米线结构的至少一条线上形成所述栅极介电层;以及
在所述栅极介电层上形成所述栅电极层,
其中,所述栅极介电层和所述栅电极层环绕所述纳米线结构的所述至少一条线。
4.根据权利要求1所述的方法,其中,形成所述导电层包括:
在多个相邻的鳍结构对之间形成绝缘材料层;
从至少一对相邻的鳍结构之间去除所述绝缘材料层;以及
在去除所述绝缘材料层之后,在所述至少一对相邻的鳍结构之间形成所述导电层。
5.根据权利要求1所述的方法,还包括在所述金属化层与所述栅电极结构和所述鳍结构之间形成第一绝缘层。
6.根据权利要求5所述的方法,还包括在所述第一绝缘层中形成导电通孔,其中,所述导电通孔连接所述导电层和所述金属化层。
7.根据权利要求1所述的方法,还包括形成第二绝缘层,所述第二绝缘层填充第二相邻鳍结构对之间的空间,在所述空间中没有形成导电层。
8.根据权利要求1所述的方法,还包括在所述导电层和第一相邻鳍结构对的所述第一区域之间形成第三绝缘层。
9.根据权利要求1所述的方法,还包括在所述导电层和所述栅电极结构之间形成第四绝缘层。
10.一种制造半导体器件的方法,包括:
在半导体衬底上形成具有第一组分的第一半导体层;
在所述第一半导体层上形成具有第二组分的第二半导体层;
在所述第二半导体层上形成具有所述第一组分的另一第一半导体层;
在所述另一第一半导体层上形成具有所述第二组分的另一第二半导体层;
图案化所述第一半导体层、所述第二半导体层和所述半导体衬底以形成沿第一方向延伸的多个鳍结构,其中,所述鳍结构包括与所述半导体衬底相邻的第一区域和包括所述第一半导体层和所述第二半导体层的第二区域,所述第二区域包括在一对第二部分之间沿所述第一方向延伸的第一部分;
在所述鳍结构上形成绝缘衬垫层;
在所述鳍结构之间形成隔离绝缘层;
从第一对相邻鳍结构之间去除所述隔离绝缘层;
在所述第一对相邻鳍结构之间形成第一导电层;
从所述鳍结构的所述第二区域去除所述绝缘衬垫层;
从所述鳍结构的所述第二区域的第一部分去除所述第一半导体层,从而形成包括所述第二半导体层的纳米线;
在所述鳍结构的所述第一部分上形成围绕所述纳米线的介电层和第二导电层,从而形成在垂直于所述第一方向的第二方向上延伸的栅电极结构,其中,所述栅电极结构包括栅极介电层和设置所述栅极介电层上的栅电极层;以及
在所述栅电极结构上形成包括多条导线的金属化层,其中,所述第一导电层沿着从所述半导体衬底延伸到金属化层的方向设置在所述半导体衬底和所述栅极介电层之间。
11.根据权利要求10所述的方法,还包括:在形成所述金属化层之前,在所述栅电极结构上形成层间介电层。
12.根据权利要求11所述的方法,还包括在所述金属化层和所述第一导电层之间的所述层间介电层中形成导电通孔。
13.根据权利要求10所述的方法,还包括在所述第一导电层和所述栅电极结构之间形成绝缘间隔件层。
14.一种半导体器件,包括:
多个鳍结构,沿第一方向延伸并且设置在半导体衬底上,其中,每个所述鳍结构包括靠近所述半导体衬底的第一区域和远离所述半导体衬底的第二区域;
至少一个第一导电层,设置在相邻的一对鳍结构的所述第一区域之间;
至少一个栅电极结构,在垂直于所述第一方向的第二方向上延伸并且设置在所述鳍结构的所述第二区域的第一部分上,其中,所述栅电极结构包括栅极介电层和设置所述栅极介电层上的栅电极层;以及
金属化层,包括至少一条导线并且设置在所述栅电极结构上方,其中,所述第一导电层沿着从所述半导体衬底延伸到所述金属化层的方向设置在所述半导体衬底和所述栅极介电层之间。
15.根据权利要求14所述的半导体器件,其中,所述鳍结构的所述第二区域包括纳米线结构,所述纳米线结构包括多条纳米线的堆叠件,每条纳米线平行于相邻的纳米线延伸。
16.根据权利要求15所述的半导体器件,其中,所述栅极介电层和所述栅电极层环绕每条纳米线。
17.根据权利要求14所述的半导体器件,其中,所述第一导电层包括电源轨和接地轨。
18.根据权利要求14所述的半导体器件,还包括将所述第一导电层连接到所述金属化层的导电通孔。
19.根据权利要求14所述的半导体器件,还包括设置在所述第一导电层和所述鳍结构之间的第一绝缘层。
20.根据权利要求14所述的半导体器件,还包括:
源极/漏极,设置在所述鳍结构的第二区域的第二部分上以及导电接触件,连接至少一个第一导电层和所述源极/漏极。
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