CN106910738A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106910738A
CN106910738A CN201610912509.2A CN201610912509A CN106910738A CN 106910738 A CN106910738 A CN 106910738A CN 201610912509 A CN201610912509 A CN 201610912509A CN 106910738 A CN106910738 A CN 106910738A
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grid
grid structure
layer
electrode layer
gate electrode
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CN106910738B (zh
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谢志宏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括第一FET和第二FET，该第一FET和第二FET分别包括第一和第二沟道区域。第一FET和第二FET分别包括第一和第二栅极结构。第一和第二栅极结构包括在第一和第二沟道区域上方形成的第一和第二栅极介电层以及在第一和第二栅极介电层上方形成的第一和第二栅电极层。第一和第二栅极结构沿着第一方向对准。第一栅极结构和第二栅极结构通过由绝缘材料制成的分离插塞分离。第一栅电极层与分离插塞的侧壁接触。本发明实施例涉及半导体集成电路，且更具体地涉及具有鳍结构的半导体器件及其制造工艺。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体集成电路，且更具体地涉及具有鳍结构的半导体器件及其制造工艺。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET器件通常包括具有高纵横比的半导体鳍，并且在该半导体鳍中形成半导体晶体管器件的沟道和源极/漏极区域。利用沟道和源极/漏极区的增大的表面面积的优势，沿着鳍结构的侧面并且在鳍结构的侧面上方(如，围绕)形成栅极，以产生更快、更可靠和更好控制的半导体晶体管器件。金属栅极结构和具有高电介电常数的高k栅极电介质通常用于FinFET器件，并且通过栅极替换技术制造。
发明内容
根据本发明的一个实施例，提供了一种半导体器件，包括：第一鳍场效应晶体管，包括在第一方向上延伸的第一鳍结构以及包括第一栅极结构，所述第一栅极结构包括在所述第一鳍结构上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在垂直于所述第一方向的第二方向上延伸；以及第二鳍场效应晶体管，包括在所述第一方向上延伸的第二鳍结构以及包括第二栅极结构，所述第二栅极结构包括在所述第二鳍结构上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第二方向上延伸；其中：所述第一栅极结构和所述第二栅极结构沿着所述第二方向对准，所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及所述第一栅电极层与所述分离插塞的侧壁接触。
根据本发明的另一实施例，还提供了一种半导体器件，包括：第一鳍场效应晶体管，包括半导体衬底的第一沟道区域以及包括第一栅极结构，所述第一栅极结构包括在所述第一沟道区域上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在第一方向上延伸；以及第二鳍场效应晶体管，包括所述半导体衬底的第二沟道区域以及包括第二栅极结构，所述第二栅极结构包括在所述第二沟道区域上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第一方向上延伸；其中所述第一栅极结构和所述第二栅极结构沿着所述第一方向对准，所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及所述第一栅电极层与所述分离插塞的侧壁接触。
根据本发明的又一实施例，还提供了一种用于制造半导体器件的方法，包括：在形成在衬底上方的沟道区域上方形成伪栅极结构，所述伪栅极结构包括伪栅电极层；在所述伪栅极结构的两侧处形成层间介电层；在形成所述层间介电层之后，去除所述伪栅电极层从而形成电极间隔；在所述电极间隔中形成栅极结构，所述栅极结构包括栅电极层；图案化所述栅极结构从而将所述栅极结构分成包括由分离开口分隔开的第一栅极结构和第二栅极结构的至少两个分开的栅极结构；以及通过利用绝缘材料填充所述分离开口来形成分离插塞，其中，在所述第一栅极结构中的所述栅电极层与所述分离插塞的侧壁接触。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图9E示出了根据本发明的一个实施例的用于制造FET器件的示例性顺序工艺。
图10A和图10B示出了根据本发明的另一实施例的FET器件的示例性结构。
图11A和图11B示出了根据本发明的一个实施例的FET器件的示例性结构。
具体实施方式
应当理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面将描述元件和布置的特定实例以简化本发明。当然，这些仅仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚，可以以不同的尺寸任意地绘制各个部件。
而且，为便于描述，在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作相应的解释。另外，术语“由...制成”可以意为“包括”或者“由...组成”。
图1至图9E示出了根据本发明的一个实施例的制造FinFET器件的示例性的有序工艺的截面图和/或平面图。应该理解，可以在由图1至图9E示出的工艺之前、期间和/或之后提供附加操作，并且对于方法的额外的实施例，可以替代或消除以下所描述的一些操作。操作/工艺的顺序可交换。
图1示出了示例性截面图，其中，在衬底10上方形成鳍结构20。为了制造鳍结构，例如，通过热氧化工艺和/或化学汽相沉积(CVD)工艺在衬底(例如半导体晶圆)上方形成掩模层。例如，衬底是杂质浓度在从约1艺在衬15cm-3至约5约在衬15cm-3的范围内的p型硅衬底。在其它实施例中，衬底是杂质浓度在从约1在其它15cm-3至约5约其它15cm-3的范围内的n型硅衬底。
可选地，衬底10可以包括另一元素半导体，诸如锗；化合物半导体，包括诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体；或它们的组合。在一个实施例中，衬底10为SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时，鳍结构可从SOI衬底的硅层突出或者可从SOI衬底的绝缘体层突出。在后面的情况下，SOI衬底的硅层用于形成鳍结构。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料也可用作衬底10。衬底10可以包括已合适地掺杂杂质(例如，p型或n型导电性)的各种区域。
例如，在一些实施例中，掩模层包括衬垫氧化物(例如，氧化硅)层和氮化硅掩模层。可通过使用热氧化或CVD工艺形成衬垫氧化物层。氮化硅掩模层可以通过诸如溅射法的物理汽相沉积(PVD)、CVD、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)和/或其它工艺形成。
在一些实施例中，衬垫氧化物层的厚度在从约2nm至约15nm的范围内，并且氮化硅掩模层的厚度在从约2nm至约50nm的范围内。在掩模层上方还形成掩模图案。例如，掩模图案是通过光刻形成的光刻胶图案。
通过使用掩模图案作为蚀刻掩模，形成了衬垫氧化物层106和氮化硅掩模层107的硬掩模图案100。
通过将硬掩模图案用作蚀刻掩模，通过使用干蚀刻方法和/或湿蚀刻方法进行沟槽蚀刻而将衬底图案化为鳍结构20。
在一个实施例中,在衬底10上方设置的鳍结构20是由与衬底10相同的材料制成的并且连续地从衬底10延伸。鳍结构20可以是本征的，或适当地掺杂有n型杂质或p型杂质。
在图1中,设置四个鳍结构20。这些鳍结构用于p型FinFET和/或n型FinFET。鳍结构的数量不局限于四个。数量可以小至一个，或多过四个。此外，多个伪鳍结构中的一个可以邻近鳍结构20的两侧设置以改进在图案化工艺中的图案保真度。在一些实施例中，鳍结构20的宽度W1在从约5nm至约40nm的范围内，并且在特定的实施例中，该宽度在从约7nm至约20nm的范围内。在一些实施例中，鳍结构20的高度H1在从约100nm至约300nm的范围内，并且在其它实施例中，该高度在从约50nm至约100nm的范围内。当鳍结构的高度不一致时，从衬底的高度可以从对应于鳍结构的平均高度的平面测量。
如图2所示，形成隔离绝缘层的绝缘材料层50形成在衬底10上方从而完全覆盖鳍结构20。
例如，用于隔离绝缘层50的绝缘材料由通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的二氧化硅组成。在可流动CVD中，沉积可流动介电材料而不是氧化硅。正如它们的名字所表明的，可流动介电材料在沉积期间可以“流动”以填充具有高纵横比的间隙或空间。通常，将各种化学物质添加至含硅前体以允许沉积的膜流动。在一些实施例中，添加氮氢键。可流动介电前体(特别地，可流动氧化硅前体)的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺(诸如三甲硅烷基胺(TSA))。在多重操作工艺中形成这些可流动氧化硅材料。在沉积可流动膜之后，将可流动膜固化然后退火以去除不需要的元素从而形成氧化硅。当去除不需要的元素时，可流动膜致密并且收缩。在一些实施例中，进行多重退火工艺。固化可流动膜，并且进行不止一次的退火。隔离绝缘层50可以是SOG、SiO、SiON、SiOCN或氟掺杂的硅酸盐玻璃(FSG)。隔离绝缘层50可以掺杂有硼和/或磷。
在形成隔离绝缘层50之后，实施平坦化操作以去除隔离绝缘层50的上部部分以及包括衬垫氧化物层106和氮化硅掩模层107的掩模层100。之后，如图3所示，进一步去除隔离绝缘层50，从而暴露鳍结构20的将成为沟道区域的上部部分。
在形成隔离绝缘层50之后，可选择地实施诸如退火工艺的热工艺以提高隔离绝缘层50的品质。在特定实施例中，通过在诸如N2、Ar或He环境的惰性气体环境中在从约900℃至约1050℃的范围内的温度下使用快速热退火(RTA)实施热工艺持续约1.5秒至约10秒。
如图4A至图4D所示，在鳍结构20的上部部分从隔离绝缘层50暴露之后，栅极绝缘层105和多晶硅层形成在隔离绝缘层50和暴露的鳍结构20上方，并且然后实施图案化操作以获得由多晶硅制成的栅极层110。栅极绝缘层105可为通过CVD、PVD、ALD、电子束蒸发或其他适当的工艺形成的氧化硅。在一些实施例中，多晶硅层的厚度是从约5nm至约100nm的范围内。在用本实施例描述的栅极替换技术中，栅极绝缘层105和栅极层100均为最后去除的伪层。
在图案化多晶硅层之后，还在栅极层110的两侧面处形成侧壁绝缘层80(侧壁间隔件)。侧壁绝缘层80是由诸如SiN、SiCN、SiON或SiOCN的基于氧化硅或氮化硅的材料的一层或多层制成的。在一个实施例中，使用氮化硅。
在形成侧壁绝缘层80之后，将用作接触蚀刻停止层(CESL)的绝缘层(未示出)可以可选地形成在多晶硅层110和侧壁绝缘层80上方。CESL层可以是由诸如SiN、SiCN、SiON或SiOCN的基于氧化硅或氮化硅的材料的一层或多层制成的。在一个实施例中，使用氮化硅。
此外，层间介电层(ILD)70形成在具有侧壁绝缘层80的栅极层110(和CESL，如果形成)之间的间隔中以及栅极层110上方。ILD 70可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、掺氟的硅酸盐玻璃(FSG)或低K介电材料，且可以通过CVD或其他合适的工艺制成。用于隔离绝缘层50的绝缘材料可以与用于ILD 70的绝缘材料相同或不同。
实施诸如回蚀刻工艺和/或化学机械抛光(CMP)工艺的平坦化操作以获得图4A至图4D中所示的结构。图4A是平面图(顶视图)且图4B是形成栅极层110和层间介电层70之后的FinFET器件的立体图。图1至图3和图4C对应于沿图4A中的线X1-X1的截面图，图4D对应于沿图4A的线Y1-Y1的截面图，以及图4B对应于图4A中的封闭部分B1。
如图4A和图4B所示，栅极层110形成为在一个方向(X方向)上延伸的具有等间距的线和间隔的布置。栅极层110可以包括在垂直于一个方向的另一方向(Y方向)上延伸的另一线和间隔的布置，且另一线和间隔的布置具有不同的尺寸。
栅极层110覆盖形成有鳍结构20的FinFET的沟道区域。换言之，在沟道区域上方形成栅极层110。未被栅极层覆盖的鳍结构将通过适合的源极/漏极制造操作变成源极/漏极区域。
接下来，如图5A至图5C所示，在暴露出栅极层110的上表面的平坦化操作之后，通过使用干蚀刻和/或湿蚀刻去除栅极层110和栅极绝缘层105(即，伪层)，从而形成栅极线开口120。
接下来，如图6A至图6D所示，在栅极线开口120中形成包括栅极介电层130和金属栅电极层140的金属栅极结构。图6D是图6B的区域B2的放大图。
在特定实施例中，栅极介电层130包括由氧化硅制成的界面层132以及介电材料134的一层或多层，介电材料134诸如氧化硅、氮化硅或高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。例如，通过鳍结构20的沟道区域的热氧化形成界面层132。通过CVD或ALD在鳍结构的沟道区域上方和隔离绝缘层50的上表面上方形成介电材料层134。
如图6D所示，在特定的实施例中，金属栅电极层140包括按这个顺序堆叠的下面的层(诸如阻挡层142、功函调整层144和胶(粘合)层146)和主金属层148。
为了图6B中说明的目的，尽管鳍结构20的沟道区域的顶部示出为具有矩形(直角)，但是如图6D所示，鳍结构20的沟道区域的顶部通常具有圆形。
例如，阻挡层142是由TiN、TaN、TiAlN、TaCN、TaC或TaSiN组成的。在一个实施例中，使用TaN。
功函调整层144由导电材料制成，诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或者这些材料的两种或多种的多层。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调整层，而对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。功函调整层可以通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺来形成。另外，可以使用不同的金属层分别地形成用于n沟道FinFET和p沟道FinFET的功函调整层。
例如，胶层146是由TiN、TaN、TiAlN、TaCN、TaC或TaSiN制成的。在一些实施例中，使用TiN。
主金属层148包括任何合适的金属材料(诸如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合)的一层或多层。
在形成金属栅极结构中，通过例如用于栅极介电层的CVD或ALD、以及用于金属层的CVD、PVD、ALD或镀的合适的膜形成方法形成栅极介电层130和栅电极层140，然后实施诸如CMP的平坦化操作。
在形成金属栅极结构之后，在图6A至图6D产生的结构上方形成掩模图案150。图7A是对应于图7C中的线X1-X1的截面图，以及图7B是对应于图4A的区域B1的区域的立体图，以及图7C是顶视图。
通过例如具有对形成金属栅极结构的金属材料高蚀刻选择性的材料形成掩模图案150。在一个实施例中，掩模图案150是由氧化硅或氮化硅制成的。掩模图案150具有开口155。在一些实施例中，开口155沿X轴方向的宽度在从约5nm至约100nm的范围内，而在其他实施例中在从约10nm至约30nm的范围内。调整开口155沿Y方向的宽度W2以暴露出期望量的栅极结构。在图7C中，开口155沿Y方向的宽度W2是这样的长度使得两个栅极结构暴露在开口155中，且开口在Y方向上的边缘位于ILD 70上方的邻近的栅极结构之间。
如图8A至图8C所示，通过使用掩模图案150作为蚀刻掩模，去除金属栅极层140和栅极介电层130的部分从而获得将栅极结构分离的开口160。通过等离子体蚀刻实施栅极层的蚀刻。
如图8A所示，沿着Y方向，金属栅电极层140暴露在开口160中，且如图8B所示，沿着X方向，通过栅极介电层130形成开口。
在一些实施例中，如图8A至图8C所示，从开口160的底部完全地去除栅极介电层130。此外，在开口160中还可以完全地去除栅极介电层130使得没有介电层留在开口160中。在其它实施例中，在开口160的底部中保留栅极介电层130。
注意，开口160的横截面图具有图8B中所示的矩形，但是在一些实施例中，开口160具有顶部尺寸较大且底部尺寸较小的锥形。
然后，如图9A至图9E所示，在开口160中形成分离插塞170。图9A是顶视图，图9B是图9A的线X1-X1的截面图，以及图9C是图9A的线Y1-Y1的截面图。图9D是立体图，且图9E是图9B的区域B3的放大图。
为了形成分离插塞170，通过使用CVD或ALD，绝缘材料的毯式层填充在开口160中且形成在栅电极170和ILD 70的上方，以及然后实施诸如CMP的平坦化操作。如图9A和图9B中所示，在CMP中，实施CMP以暴露出金属栅电极140的上表面。换言之，金属栅电极层140用作CMP工艺的阻挡件。通过平坦化操作，形成分离插塞170。
例如，分离插塞170是由诸如SiN、SiON、SiCN或SiOCN的基于氧化硅或氮化硅的材料制成的。
在本实施例中，在形成栅极介电层130和金属栅电极层140之后，形成开口160和分离插塞170。因此，如图9E所示，主金属层148与分离插塞的侧壁接触。此外，栅极介电层130沿Y方向的最上部分位于鳍结构20之上，且金属栅电极140的沿Y方向的下面的层142、144和146也位于鳍结构20之上。沿X方向，金属栅电极层140和栅极介电层具有相同的高度。
如图7A至图8C所示，在前述实施例中，金属栅极结构被分离成两个金属栅电极层140，每个金属栅电极层140均具有栅极介电层130。然而，在其它实施例中，通过图案化操作，金属栅极结构被分离成两个以上栅电极层。在这样的情况下，如图10A所示，每个均包括金属栅电极层140和栅极介电层130的多个金属栅极结构对齐且通过分离插塞170分离。
此外，在分离操作之前，金属栅极结构在其纵向上具有两端。如图10A的区域B3所示，在一些实施例中，分离插塞170形成在这些端的至少一个中。在这样的情况下，包括金属栅电极层140和栅极介电层130的分开的栅极结构由两个分离插塞170相夹。
如图10A的区域B4所示，在其它实施例中，分离插塞170未形成在端的至少一个中。在这样的情况下，包括金属栅电极层140和栅极介电层130的栅极结构的一端具有分离插塞170且栅极结构的另一端具有图10B所示的结构。图10B是图10A的线B5的截面图。如图10B所示，栅极结构(特别地，栅极介电层130)与ILD 70接触且金属栅电极层140(特别地，主金属栅电极层148)不与ILD 70接触。
如果通过分隔开伪栅电极且填充分隔开的伪栅电极之间的开口首先形成分离插塞，以及然后由金属栅极材料填充通过去除分隔开的伪栅电极形成的间隔，那么诸如阻挡层、功函调整层和胶层的下面的金属层形成在分离插塞的侧表面上。在这样的情况下，如图9E示出的分离插塞和鳍结构之间的距离D1不能设置太小，因为太小的距离D1可能阻止主金属层148完全地填充分离插塞和鳍结构之间的间隔。
相比之下，在本实施例中，因为没有栅极介电层且没有下面的金属层形成在分离插塞的侧表面上，即使距离D1变小，主金属层148可以完全填充分离插塞170和鳍结构20之间的间隔。因此，缩小半导体器件是可能的。
在另一实施例中，栅极绝缘层105不是伪层且是由最后用于FET器件的介电材料制成的。在这样的情况下，可以使用上述的高k介电材料。当栅极绝缘层105不是伪层时，在形成金属栅电极层140之前不沉积栅极介电层130。
应当理解，图9A至图9E中示出的结构经历另外的CMOS工艺以形成诸如互连通孔、互连金属层、钝化层等的各种部件。
在以上实施例中，采用了FinFET。然而，如图11A和图11B所示，可以对平面型FET应用上述技术。如图11A和图11B所示，FET包括半导体衬底的沟道区域25和在沟道区域25上方形成的栅极结构，栅极结构包括栅极介电层130'和在栅极介电层130'上方形成的金属栅电极层140'。类似于栅极介电层130，栅极介电层130'包括界面层132'和介电材料134’的一层或多层。类似于金属栅电极层140，金属栅电极层140'包括按这个顺序堆叠的阻挡层142'、功函调整层144'和胶(粘合)层146'和主金属层148'。沟道区域由隔离绝缘层50分离，且两个栅极结构由分离插塞170分离。
本文描述的各个实施例或实例提供若干优于现有技术的优点。例如，因为没有栅极介电层且没有下面的金属层形成在分离插塞的侧表面上，将用金属栅极材料填充的栅极间隔的Y方向上的宽度可以变大。利用放大的栅极开口，诸如金属栅电极材料的金属栅极材料可以完全地填充在开口中而不形成空隙。进而，这使得分离插塞和鳍结构之间的距离更小，且缩小半导体器件是可能的。
应该理解，本文不必讨论所有优点，没有特定优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同优点。
根据本发明的一方面，一种半导体器件包括第一鳍场效应晶体管(FinFET)和第二FinFET。第一FinFET包括在第一方向上延伸的第一鳍结构以及包括第一栅极结构。第一栅极结构包括在第一鳍结构上方形成的第一栅极介电层和在第一栅极介电层上方形成的第一栅电极层，且第一栅极结构在垂直于第一方向的第二方向上延伸。第二FinFET包括在第一方向上延伸的第二鳍结构和第二栅极结构。第二栅极结构包括在第二鳍结构上方形成的第二栅极介电层和在第二栅极介电层上方形成的第二栅电极层，且第二栅极结构在第二方向上延伸。第一栅极结构和第二栅极结构沿着第二方向对准。第一栅极结构和第二栅极结构通过由绝缘材料制成的分离插塞分离。第一栅电极层与分离插塞的侧壁接触。
根据本发明的另一方面，一种半导体器件包括第一场效应晶体管(FET)和第二FET。第一FET包括半导体衬底的第一沟道区域以及包括第一栅极结构。第一栅极结构包括在第一沟道区域上方形成的第一栅极介电层和在第一栅极介电层上方形成的第一栅电极层，且第一栅极结构在第一方向上延伸。第二FET包括半导体衬底的第二沟道区域和第二栅极结构。第二栅极结构包括在第二沟道区域上方形成的第二栅极介电层和在第二栅极介电层上方形成的第二栅电极层，且第二栅极结构在第一方向上延伸。第一栅极结构和第二栅极结构沿着第一方向对准。第一栅极结构和第二栅极结构通过由绝缘材料制成的分离插塞分离。第一栅电极层与分离插塞的侧壁接触。
根据本发明的另一方面，一种用于制造半导体器件的方法包括在衬底上方形成的沟道区域上方形成伪栅极结构。伪栅极结构包括伪栅电极层。层间介电层形成在伪栅极结构的两侧处。在形成层间介电层之后，去除伪栅电极层从而形成电极间隔。在电极间隔中形成栅极结构。栅极结构包括栅电极层。图案化栅极结构使得栅极结构被分成至少两个分开的栅极结构(包括由开口分隔开的第一栅极结构和第二栅极结构)。通过用绝缘材料填充开口来形成分离隔塞。在第一栅极结构中的栅电极层与分离插塞的侧壁接触。
根据本发明的一个实施例，提供了一种半导体器件，包括：第一鳍场效应晶体管，包括在第一方向上延伸的第一鳍结构以及包括第一栅极结构，所述第一栅极结构包括在所述第一鳍结构上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在垂直于所述第一方向的第二方向上延伸；以及第二鳍场效应晶体管，包括在所述第一方向上延伸的第二鳍结构以及包括第二栅极结构，所述第二栅极结构包括在所述第二鳍结构上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第二方向上延伸；其中：所述第一栅极结构和所述第二栅极结构沿着所述第二方向对准，所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及所述第一栅电极层与所述分离插塞的侧壁接触。
在上述半导体器件中：所述第一栅电极层包括在所述第一鳍结构上方形成的下面的层和主金属电极层，以及所述主金属电极层与所述分离插塞的所述侧壁接触。
在上述半导体器件中，其中，所述分离插塞是由基于氮化硅的材料制成的。
在上述半导体器件中，其中：所述第二栅电极层包括在所述第二鳍结构上方形成的下面的层和主金属电极层，以及所述第二栅电极层的所述主金属电极层与所述分离插塞的侧壁接触。
5在上述半导体器件中，其中，所述第一栅极介电层的沿所述第二方向的最上部分位于所述第一鳍结构之上。
在上述半导体器件中，其中，所述下面的层的沿所述第二方向的最上部分位于所述第一鳍结构之上。
在上述半导体器件中，其中：所述第一栅极结构具有第一端和第二端，在所述第一端处提供所述分离插塞，以及在所述第二端处提供另一分离插塞。
在上述半导体器件中，其中：所述第一栅极结构具有第一端和第二端，在所述第一端处提供所述分离插塞，以及在所述第二端处不提供分离插塞。
在上述半导体器件中，其中：在所述第二端处，所述第一栅电极层不与所述分离插塞的侧壁接触。
根据本发明的另一实施例，还提供了一种半导体器件，包括：第一鳍场效应晶体管，包括半导体衬底的第一沟道区域以及包括第一栅极结构，所述第一栅极结构包括在所述第一沟道区域上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在第一方向上延伸；以及第二鳍场效应晶体管，包括所述半导体衬底的第二沟道区域以及包括第二栅极结构，所述第二栅极结构包括在所述第二沟道区域上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第一方向上延伸；其中所述第一栅极结构和所述第二栅极结构沿着所述第一方向对准，所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及所述第一栅电极层与所述分离插塞的侧壁接触。
在上述半导体器件中：所述第一栅电极层包括在所述第一沟道区域上方形成的下面的层和主金属电极层，以及所述主金属电极层与所述分离插塞的所述侧壁接触。
根据本发明的又一实施例，还提供了一种用于制造半导体器件的方法，包括：在形成在衬底上方的沟道区域上方形成伪栅极结构，所述伪栅极结构包括伪栅电极层；在所述伪栅极结构的两侧处形成层间介电层；在形成所述层间介电层之后，去除所述伪栅电极层从而形成电极间隔；在所述电极间隔中形成栅极结构，所述栅极结构包括栅电极层；图案化所述栅极结构从而将所述栅极结构分成包括由分离开口分隔开的第一栅极结构和第二栅极结构的至少两个分开的栅极结构；以及通过利用绝缘材料填充所述分离开口来形成分离插塞，其中，在所述第一栅极结构中的所述栅电极层与所述分离插塞的侧壁接触。
在上述方法中，在图案化所述栅极结构中，所述栅极结构被分成三个或更多分开的栅极结构。
在上述方法中，在形成所述分离开口之后，所述栅电极层暴露在所述分离开口中。
在上述方法中，图案化所述栅极结构包括：在所述栅极结构和所述层间介电层上方形成掩模层；图案化所述掩模层以形成开口图案；以及蚀刻所述栅极结构的位于所述开口图案下方的部分，从而形成所述分离开口。
在上述方法中，所述栅电极层包括在所述沟道区域上方形成的下面的层和主金属电极层，以及所述主金属电极层与所述分离插塞的所述侧壁接触。
在上述方法中，所述伪栅极结构还包括伪栅极介电层和设置在所述伪栅电极层的两侧上的侧壁间隔件层，以及通过去除所述伪栅电极层和所述伪栅极介电层形成所述电极间隔。
在上述方法中，在所述电极间隔中形成所述栅极结构，所述栅极结构包括栅极介电层。
在上述方法中，其中：所述栅极结构在被分开之前具有第一端和第二端，所述第一栅极结构包括所述第一端，所述第一端是与形成所述分离插塞处相对的端，以及在所述第一端处形成另一分离插塞。
在上述方法中，所述栅极结构在被分开之前具有第一端和第二端，所述第一栅极结构包括所述第一端，所述第一端是与形成所述分离插塞处相对的端，以及在所述第一端处没有形成分离插塞。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一鳍场效应晶体管，包括在第一方向上延伸的第一鳍结构以及包括第一栅极结构，所述第一栅极结构包括在所述第一鳍结构上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在垂直于所述第一方向的第二方向上延伸；以及
第二鳍场效应晶体管，包括在所述第一方向上延伸的第二鳍结构以及包括第二栅极结构，所述第二栅极结构包括在所述第二鳍结构上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第二方向上延伸；其中：
所述第一栅极结构和所述第二栅极结构沿着所述第二方向对准，
所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及
所述第一栅电极层与所述分离插塞的侧壁接触。
2.根据权利要求1所述的半导体器件，其中：
所述第一栅电极层包括在所述第一鳍结构上方形成的下面的层和主金属电极层，以及
所述主金属电极层与所述分离插塞的所述侧壁接触。
3.根据权利要求1所述的半导体器件，其中，所述分离插塞是由基于氮化硅的材料制成的。
4.根据权利要求1所述的半导体器件，其中：
所述第二栅电极层包括在所述第二鳍结构上方形成的下面的层和主金属电极层，以及
所述第二栅电极层的所述主金属电极层与所述分离插塞的侧壁接触。
5.根据权利要求1所述的半导体器件，其中，所述第一栅极介电层的沿所述第二方向的最上部分位于所述第一鳍结构之上。
6.根据权利要求2所述的半导体器件，其中，所述下面的层的沿所述第二方向的最上部分位于所述第一鳍结构之上。
7.根据权利要求1所述的半导体器件，其中：
所述第一栅极结构具有第一端和第二端，
在所述第一端处提供所述分离插塞，以及
在所述第二端处提供另一分离插塞。
8.根据权利要求1所述的半导体器件，其中：
所述第一栅极结构具有第一端和第二端，
在所述第一端处提供所述分离插塞，以及
在所述第二端处不提供分离插塞。
9.一种半导体器件，包括：
第一鳍场效应晶体管，包括半导体衬底的第一沟道区域以及包括第一栅极结构，所述第一栅极结构包括在所述第一沟道区域上方形成的第一栅极介电层和在所述第一栅极介电层上方形成的第一栅电极层，且所述第一栅极结构在第一方向上延伸；以及
第二鳍场效应晶体管，包括所述半导体衬底的第二沟道区域以及包括第二栅极结构，所述第二栅极结构包括在所述第二沟道区域上方形成的第二栅极介电层和在所述第二栅极介电层上方形成的第二栅电极层，且所述第二栅极结构在所述第一方向上延伸；其中
所述第一栅极结构和所述第二栅极结构沿着所述第一方向对准，
所述第一栅极结构和所述第二栅极结构通过由绝缘材料制成的分离插塞分离，以及
所述第一栅电极层与所述分离插塞的侧壁接触。
10.一种用于制造半导体器件的方法，包括：
在形成在衬底上方的沟道区域上方形成伪栅极结构，所述伪栅极结构包括伪栅电极层；
在所述伪栅极结构的两侧处形成层间介电层；
在形成所述层间介电层之后，去除所述伪栅电极层从而形成电极间隔；
在所述电极间隔中形成栅极结构，所述栅极结构包括栅电极层；
图案化所述栅极结构从而将所述栅极结构分成包括由分离开口分隔开的第一栅极结构和第二栅极结构的至少两个分开的栅极结构；以及
通过利用绝缘材料填充所述分离开口来形成分离插塞，
其中，在所述第一栅极结构中的所述栅电极层与所述分离插塞的侧壁接触。
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