CN106505103A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN106505103A
CN106505103A CN201510860676.2A CN201510860676A CN106505103A CN 106505103 A CN106505103 A CN 106505103A CN 201510860676 A CN201510860676 A CN 201510860676A CN 106505103 A CN106505103 A CN 106505103A
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CN106505103B (zh
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王圣祯
杨世海
萧琮介
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置的制造方法，在上述方法中，一第一半导体层形成于一基底上方。一蚀刻停止层形成于第一半导体层上方。一虚置层形成于蚀刻停止层上方。多个隔离区形成于虚置层、蚀刻停止层及第一半导体层内。去除位于隔离区之间的虚置层及蚀刻停止层，以形成一空间。第一半导体层露出于空间内。一第二半导体层形成于空间内的第一半导体层上方。一第三半导体层形成于空间内的第二半导体层上方。下凹隔离区，以露出第三半导体层的一上部。本发明亦提供一种半导体装置。

Description

半导体装置及其制造方法
技术领域
本发明关于一种半导体积体电路，且特别是关于一种具有鳍式结构的半导体装置及其制造方法。
背景技术
随着半导体业寻求更高装置密度、更高效能及更低成本，已进展至纳米技术制程世代，由于制造与设计问题的挑战，因而发展出三维设计，例如，鳍式场效晶体管(Fin FET)。Fin FET装置通常包括具有高纵宽比的半导体鳍，且其中形成半导体装置的通道及源极/漏极区。栅极沿着鳍结构侧边而形成于上方(例如，包围)，利用增加通道及源极/漏极区的表面积的优势，产生更快速、更具可靠度及更好控制的半导体晶体管装置。在Fin FET装置中，鳍结构的上部作为通道，而鳍结构的下部作为阱区。另外，Fin FET的源极/漏极(S/D)部内利用选择性生长硅锗(SiGe)的应变材料，可用于增加载子迁移率。举例来说，施加于PMOS装置的通道的压缩应力，有益于增加通道内的空穴迁移率。相似地，施加于NMOS装置的通道的拉伸应力，有益于增加通道内的电子迁移率。
发明内容
根据一些实施例，本发明提供一种半导体装置的制造方法，包括︰形成一第一半导体层于一基底上方；形成一蚀刻停止层于第一半导体层上方；形成一虚置层于蚀刻停止层上方；形成多个隔离区于虚置层、蚀刻停止层及第一半导体层内；去除隔离区之间的虚置层及蚀刻停止层，以形成一空间，空间内露出第一半导体层；形成一第二半导体层于空间内的第一半导体层上方；形成一第三半导体层于空间内的第二半导体层上方；以及下凹隔离区，以露出第三半导体层的一上部。
根据一些实施例，本发明提供一种半导体装置的制造方法，包括︰形成一第一半导体层于一基底上；形成一蚀刻停止层于第一半导体层上方；形成一虚置层于蚀刻停止层上方；形成多个隔离区于虚置层、蚀刻停止层及第一半导体层内；去除隔离区之间的虚置层及蚀刻停止层，以于一第一区域形成一空间，而未去除位于一第二区域的虚置层及蚀刻停止层，空间内露出第一半导体层；形成一第二半导体层于第一区域的空间内的第一半导体层上方；形成一第三半导体层于第一区域的空间内的第二半导体层上方；以及下凹隔离区，以露出第三半导体层的一上部。
根据一些实施例，本发明提供一种半导体装置，包括︰多个装置区域，其内设置包括一鳍式场效晶体管的多个主动电路元件；以及一非装置区域，设置于装置区域之间或包括一切割道及包括一虚置结构。其中，鳍式场效晶体管包括：一鳍结构，具有包括一第一半导体层的一阱区、包括一第二半导体层的一应力源区以及包括一第三半导体层的一通道区；一隔离区，阱区埋入于其内，且自阱区露出通道区的至少一上部；以及一栅极结构，设置于一部分的鳍结构的上方。其中，位于非装置区域的虚置结构包括：一第一虚置层，形成于第一半导体层上方，且由不同于应力源区的材料制成；以及一第二虚置层，形成于第一虚置层上方，且由不同于通道区的材料制成。
附图说明
图1绘示出根据本发明一实施例的鳍式场效晶体管(Fin FET)装置立体示意图。
图2至9绘示出根据本发明一实施例的制造鳍式场效晶体管装置的连续制程剖面示意图。
图10至11绘示出根据本发明一实施例的制造鳍式场效晶体管装置的其中一制程剖面示意图。
【符号说明】
1、10 基底
2 隔离层
3 鳍结构
4 阱区
5 应力源区
6 通道区
7、80 栅极结构
20 (SiGe)第一半导体层
30 蚀刻停止层
40 虚置层
45 空间
50 隔离层/STI层
52 突出物
54 凹口
60 第二半导体层
70 第三半导体层
82 栅极介电层
84 功函数调整层
86 栅极电极层
b 层位
D 深度
DR 装置区域
H1、H2 高度
NDR 非装置区域
S 间隔
W 宽度
具体实施方式
可理解的是以下的公开内容提供许多不同的实施例或范例，以实施本发明的不同特征部件。而以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化本发明内容。当然，这些仅为范例说明并非用以限定本发明。举例来说，元件的尺寸大小并未局限于以下公开的范围或数值，但取决于制程条件及/或所需的装置特性。再者，若是以下的公开内容叙述了将一第一特征部件形成于一第二特征部件的上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。为了达到简化及明确目的，各种不同的特征部件可任意地依不同的尺寸比例绘示。
再者，在空间上的相关用语，例如＂之下＂、＂下方＂、＂下＂、＂上方＂、＂上＂等等在此处用以容易表达出本说明书中所绘示的附图中元件或特征部件与另外的元件或特征部件的关系。这些空间上的相关用语除了涵盖附图所绘示的方位外，还涵盖装置于使用或操作中的不同方位。此装置可具有不同方位(旋转90度或其他方位)且此处所使用的空间上的相关符号同样有相应的解释。另外，＂由…制成＂的用语也意指＂包括＂或＂由…组成＂。
图1绘示出根据本发明一实施例的鳍式场效晶体管(Fin FET)装置立体示意图。
Fin FET装置包括在其他特征部件之中的一基底1、一隔离层2、一鳍结构3及一栅极结构7。
多个鳍结构3设置于基底1上方。每一鳍结构3包括一阱区4、一应力源(stressor)区5及一通道区6。应力源区5施加一适当的应力(拉伸或压缩)于通道区6。
鳍结构3的阱区4由相同于基底1的材料制成且字基底1连续性延伸。在其他实施例中，阱区形成于基底1上方。
在图1中，三个鳍结构3设置于基底1上方。然而，鳍结构的数量并未局限于三个。上述数量可少至一个或多至三个以上。另外，一或多个虚置鳍结构可设置于邻近鳍结构3的两侧，以在图案画制程中改善图案精确性(pattern fidelity)。在一些实施例中，鳍结构3的宽度W约在5nm至50nm的范围，或在其他实施例中约在5nm至20nm的范围。在一些实施例中，鳍结构3的高度H1约在100nm至300nm的范围，或在其他实施例中约在50nm至100nm的范围。
鳍结构3之间的空间及/或单一鳍结构与形成于基底1上的另一元件之间的空间填入一隔离绝缘层2(或称为浅沟槽隔离(STI)层)，其包括一绝缘材料。
位于栅极结构7下方的鳍结构3的下部称为一阱区4，且鳍结构3的上部称为一通道区6。在本发明的一实施例中，鳍结构3更包括一应力源区5位于阱区4与通道区6之间。在栅极结构7下方，阱区4及应力源区5埋入一隔离绝缘层2内，且通道区6自隔离绝缘层2突出。通道区6的一下部也可埋入隔离绝缘层2至约1nm至5nm范围的一深度D。在一些实施例中，通道区6的高度H2约在20nm至100nm的范围，或在其他实施例中约在30nm至60nm的范围。
一栅极结构覆盖自隔离绝缘层2突出的通道区6，且栅极结构包括覆盖有栅极电极(未绘示)的一栅极介电层。未被栅极结构7覆盖的部分的通道区6作为MOS FET的源极及/或漏极。
通过掺杂适合的杂质于源极及漏极区内，以于未被栅极结构7覆盖的的通道区6内形成源极及漏极区。硅或锗的合金及一金属(例如，Co、Ni、W、Ti或Ta)形成于源极及漏极区上。
再者，一内层绝缘层(未绘示)覆盖栅极结构7及源极/漏极区，且设置必须的接线及/或介层(via)/接触(contact)孔，以完成半导体装置。
图2至9绘示出根据本发明一实施例的制造鳍式场效晶体管装置的连续制程剖面示意图。除了鳍结构数量以外，第2至9图对应图1中a-a线的剖面示意图。可以理解的是可在第2至9图所示的制程进行之前、期间及之后进行其他操作步骤，且在上述方法的其他实施例中，可取代或省略以下所述的某些操作步骤。操作步骤/制程的顺序可相互交换。
图2绘示出具有鳍结构的半导体FET(Fin FET)的其中一制造情形的剖面示意图。
在图2中，一第一半导体层20形成于一基底10上方。在本发明一实施例中，第一半导体层20包括Si1-xGex，其中x为0.1至0.9，或在其他实施例中，x约在0.4至0.9的范围。在本发明中，Si1-xGex可简称为SiGe。
基底10可为一p型硅基底，其具有一杂质浓度且约在1×1015cm-3至5×1015cm-3的范围。在其他实施例中，基底10可为一n型硅基底，其具有一杂质浓度且约在1×1015cm-3至5×1015cm-3的范围。
另外，基底10可包括其他元素半导体，例如锗；化合物半导体，包括IV-IV族化合物半导体(例如，SiC及SiCGe)、III-V族化合物半导体(例如，GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)；或其组合。在一实施例中，基底10为绝缘层上覆硅(SOI)基底上的一硅层。基底10可包括不同的区域，其已掺杂适合的杂质(例如，p型或n型导电物)。
SiGe第一半导体层20外延生长于Si基底10上方。在一些实施例中，为了抑制差排或其他缺陷，SiGe第一半导体层20内Ge的含量(x)约在0.15至0.3的范围。在一些实施例中，第一半导体层20的厚度约在500nm至2000nm的范围，或在其他实施例中，约在1000nm至1500nm的范围。适当地掺杂杂质于SiGe第一半导体层20内。杂质可于外延生长期间导入或于生长SiGe第一半导体层20之后通过使用离子注入方法导入。掺杂物可为用于n型Fin FET的硼(BF2)或用于p型Fin FET的磷。SiGe第一半导体层20将成为Fin FET的阱区。
若基底10由SiGe制成，SiGe第一半导体层20可为SiGe基底的一上部。
如图2所示，一蚀刻停止层30形成于SiGe第一半导体层20上方。再者，一虚置层40形成蚀刻停止层30上方。
蚀刻停止层30由对虚置层40及一隔离层50(参见图3)具有适合蚀刻选择比(例如，10或以上)的材料制成。蚀刻停止层30由一或多层的绝缘材料制成。在本发明的一实施例中，蚀刻停止层30包括SiN、SiON、SiCN或SiOCN。在一些实施例中，蚀刻停止层30可包括氧化硅。在一些实施例中，蚀刻停止层30的厚度约在2nm至20nm的范围，或在其他实施例中，约在5nm至10nm的范围。在其他实施例中，蚀刻停止层30可包括导电材料或半导体材料(例如，锗)。
蚀刻停止层30可通过物理气相沉积(physical vapor deposition,PVD)(例如，溅镀法)、化学气相沉积(chemical vapor deposition,CVD)、等离子体辅助化学气相沉积(plasma enhanced CVD,PECVD)、常压化学气相沉积(atmospheric pressure CVD,APCVD)、低压化学气相沉积(low-pressure CVD,LPCVD)、高密度等离子体化学气相沉积(high densityplasma CVD,HDPCVD)、原子层沉积(atomic layer deposition,ALD)及/或其他制程形成。
虚置层40由对蚀刻停止层30及一隔离层50具有适合蚀刻选择比(例如，10或以上)的材料制成。在一实施例中，虚置层40由Si或Si基化合物制成。当使用Si时，Si虚置层40为多晶Si层或非晶Si层。取决于蚀刻停止层30的材料，Si虚置层40可为结晶Si。在其他实施例中，虚置层40由其他半导体材料制成，例如SiGe或Ge，或由绝缘材料制成，例如氧化物或氮化物。虚置层40可由金属材料或金属化合物(例如，Ti、Ta、TiN及TaN)制成。在一些实施例中，虚置层40的厚度约在20nm至100nm的范围，或在其他实施例中，约在30nm至60nm的范围。
可通过PVD、PECVD、APCVD、LPCVD、HDPCVD及/或ALD及/或其他制程形成虚置层40。
如图3所示，形成隔离层50。在一实施例中，隔离层50为浅沟槽隔离(STI)层。
为了形成隔离层50，通过使用微影操作步骤形成一阻剂图案于虚置层40上方。接着，利用阻剂图案作为蚀刻掩模，进行一图案化操作步骤，以在虚置层40、蚀刻停止层30及第一半导体层20内形成多个沟槽。在一些实施例中，沟槽延伸至基底10。在一些实施例中，相邻沟槽之间的间隔S(其将定义出Fin FET的通道宽度)约在5nm至50nm的范围，或在其他实施例中约在5nm至20nm的范围。沟槽通常为锥型，其具有较小的下部及较大的上部。
形成沟槽之后，填入一或多层绝缘材料于沟槽内。举例来说，绝缘材料包括由LPCVD、等离子体CVD(plasma CVD)或流动式CVD(flowable CVD)所形成的二氧化硅。在流动式CVD中，以流动的介电材料取代氧化硅进行沉积。顾名思义，流动式介电材料为沉积期间可＂流动＂，以填入高深宽比的间隙或空间。通常各种不同的化学物质加入于含硅前驱物中，以容许沉积膜层流动。在一些实施例中，加入氮氢化物键结。流动式介电前驱物的范例，特别是流动式氧化硅前驱物，包括硅酸盐、硅氧烷(siloxane)、甲基硅酸盐类(methyl silsequioxane,MSQ)、氢硅倍半氧烷(hydrogen silsequioxane,HSQ)、MSQ/HSQ、全氢硅氮烷(perhydrosilazane,PSZ)、全氢聚硅氮烷(perhydro-polysilazane,PHPS)、四乙氧基硅烷(tetraethoxysilane,TEOS)或甲硅烷基胺(silyl-amine)(例如，三甲硅烷基胺(trisilylamine,TSA))。这些流动式氧化硅材料形成于一多重操作(multiple-operation)制程。在沉积流动式膜层之后，进行固化并接着进行退火，以去除不需要的元素而形成氧化硅。当去除不需要的元素时，流动式膜层变得致密并收缩。在一些实施例中，导入多重退火制程。流动式膜层进行一次以上的固化及退火，其温度可约在300℃至800℃的范围，或约在300℃至500℃的范围。在一些实施例中，绝缘材料可包括SOG、SiO、SiON、SiOCN及/或氟掺杂硅玻璃(FSG)形成。
绝缘材料形成于沟槽内，并且位于虚置层40上表面上。进行一平坦化操作步骤，例如化学机械研磨(chemical mechanical polishing,CMP)法及/或回蚀刻制程，而得到如图3所示的浅沟槽隔离(STI)层50。
接下来，如图4所示，去除位于STI层50之间的虚置层40，以形成空间45。实施干蚀刻及/或湿蚀刻，以去除虚置层40。由于蚀刻停止层30形成于虚置层40的底部，因此可进行一适合的过蚀刻，使蚀刻停止层30的表面上实质上未余留虚置层。
接着，图5所示，去除蚀刻停止层30。实施干蚀刻及/或湿蚀刻，以去除蚀刻停止层30。当蚀刻停止层30由氮化物基材料(例如，SiN)制成，且STI层50由氧化物基材料制成时，使用H3PO4的湿蚀刻可去除对STI层50及SiGe第一半导体层20具有高蚀刻选择比的蚀刻停止层30。
如图6所示，在去除蚀刻停止层30且露出第一半导体层20的表面之后，一第二半导体层60形成于第一半导体层20上方，接着形成一第三半导体层70于第二半导体层60上方。
在一实施例中，第二半导体层60为硅或硅基化合物半导体(例如，SiGe)。当使用SiGe作为第二半导体层60，第二半导体层60的Ge含量小于SiGe第一半导体层20中的Ge含量。在一些实施例中，第二半导体层60的Ge含量(SixGe1-x中的x)为0.1或0.1以下。第二半导体层60作为一应力源区，以施加应力至通道区。
第二半导体层60外延生长于空间45(通过去除虚置层40所形成)内的第一半导体层20上。可通过使用SiH4及/或SiH2Cl2及/或GeH4作为气体源，且约在300℃至800℃的温度范围及约在10Torr至100Torr的压力范围下进行Si或SiGe第二半导体层60的外延生长。在一些实施例中，第二半导体层60的厚度约在10nm至30nm的范围，或在其他实施例中约在13nm至20nm的范围。
第三半导体层70由锗或锗基半导体(例如，SiGe)制成。在一些实施例中，当使用SiGe作为第三半导体层70，第三半导体层70的Ge含量(SixGe1-x中的x)约在0.4至0.8的范围。
第三半导体层70外延生长于空间45内的第二半导体层60上。可通过使用SiH4及/或SiH2Cl2及/或GeH4作为气体源，且约在500℃至700℃的温度范围及约在10Torr至100Torr的压力范围下进行Si或SiGe第三半导体层70的外延生长。
再者，进行一平坦化操作步骤，例如CMP及/或回蚀刻制程，以去除位于STI层50上方的第三半导体层70的部分而得到如图7所示的结构。
接下来，如图8所示，通过去除局部的STI层50而露出第三半导体层70的上部，以得到Fin FET的通道区。可利用一回蚀刻制程以去除(下凹)局部的STI层50。通过调整蚀刻时间，余留的STI层50可得到所需厚度。在图8中，第二半导体层60并未露出且埋入于STI层50内。然而，在一些实施例中，第二半导体层60的上部稍微露出于STI层50上方。
在局部露出第三半导体层70的上部之后，一栅极结构80形成于露出的第三半导体层70上方，如图9所示。一栅极介电材料及一栅极电极材料形成于STI层50及通道区(露出的第三半导体层)上方，接着进行图案化操作步骤而得到包括一栅极电极层86及一栅极介电层82的栅极结构80。在一实施例中，栅极电极层86为多晶硅。在一些实施例中，可通过使用包括氮化硅层及氧化层的硬式掩模来进行多晶硅层的图案化。栅极介电层可为氧化硅且通过CVD、PVD、ALD、电子束蒸镀或其他适合的制程形成。在一些实施例中，栅极结构80的宽度约在30nm至60nm的范围。
在某些实施例中，栅极介电层82包括一或多层的介电材料，例如氧化硅、氮化硅或高介电常数(high-k)介电材料、其他适合的介电材料及/或其组合。高介电常数介电材料的范例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适合的高介电常数介电材料及/或其组合。
栅极电极层86包括一或多层的导电材料，例如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他适合材料及/或其组合。栅极结构可使用先栅极或取代栅极(后栅极)技术形成。
在某些实施例中，一或多层功函数调整层84夹设于栅极介电层82与栅极电极层86之间。功函数调整层84可由导电材料制成，例如单层的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC或为这些材料的二或二层以上所构成的多层结构。对于n通道Fin FET而言，一或多层的TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi作为功函数调整层，且对于p通道Fin FET而言，一或多层的TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co作为功函数调整层。功函数调整层可通过ALD、PVD、CVD、电子束蒸镀、或其他适合制程形成。再者，可使用不同金属材料各自形成n型通道Fin FET及p型通道Fin FET的功函数调整层。
也可使用具有应变材料的上升外延结构来制作源极及漏极区。
在本实施例中，在虚置层40、蚀刻停止层30及第一半导体层20的沟槽蚀刻以形成STI层50(参见图3)期间，取决于蚀刻停止层30的蚀刻条件及/或材料，沟槽侧壁在蚀刻停止层30的层位变得不平坦。举例来说，若蚀刻停止层30在蚀刻期间的蚀刻多于虚置层40及第一半导体层20，沟槽具有一突出物位于蚀刻停止层30的层位b，因而在STI层50形成一突出物52，如图10所示。若蚀刻停止层30在蚀刻期间的蚀刻少于虚置层40及第一半导体层20，沟槽具有一凹口位于蚀刻停止层30的层位b，因而在STI层50形成一凹口54，如图10所示。
再者，图2至9绘示出一装置区域DR(参见图11)位于基底上，其中形成包括Fin FET的主动电路元件。然而，一或多个非装置区域NDR(参见图11)设置于基底上。非装置区域NDR不包括主动电路元件且可包括位于装置区、切割道区或制程监测区之间的区域。在上述非装置区域，不同于图4至5，虚置层40及蚀刻停止层30可不需去除。在上述情形中，如图11所示，非装置区域可包括一区域，其中虚置层40及蚀刻停止层30余留于第一半导体层20上方。须注意的是余留的虚置层40及蚀刻停止层30(连同虚置层)可在形成STI层50所进行的CMP制程期间抑制凹陷问题。
可理解的是Fin FET可进一步进行CMOS制程而形成不同的特征部件，例如接触接触(contact)/导孔(via)、内连接金属层、介电层及钝化护层等等。
此处所述的各个不同的实施例或范例提供优于现行技艺的几个优点。举例来说，在本发明中，形成蚀刻停止层30及虚置层40于第一半导体层20上方、形成沟槽及STI层50、去除虚置层40及蚀刻停止层30、接着形成具有所需厚度的第二半导体层60。由于此操作步骤，因此可精确控制第二半导体层的厚度而具有高均匀性。第二半导体层的厚度均匀性(变异)小于5％。
可以理解的是此处并未述及所有优点，且没有特定的优点是所有实施例或范例所需的，且其他实施例或范例可提供不同的优点。
根据本发明的一方式，一种半导体装置的制造方法，包括︰形成一第一半导体层于一基底上方。形成一蚀刻停止层于第一半导体层上方。形成一虚置层于蚀刻停止层上方。形成多个隔离区于虚置层、蚀刻停止层及第一半导体层内。去除隔离区之间的虚置层及蚀刻停止层，以形成一空间。此空间内露出第一半导体层。形成一第二半导体层于此空间内的第一半导体层上方。形成一第三半导体层于此空间内的第二半导体层上方。下凹隔离区，以露出第三半导体层的一上部。
根据本发明的另一方式，一种半导体装置的制造方法，包括︰形成一第一半导体层于一基底上。形成一蚀刻停止层于第一半导体层上方。形成一虚置层于蚀刻停止层上方。形成多个隔离区于虚置层、蚀刻停止层及第一半导体层内。去除隔离区之间的虚置层及蚀刻停止层，以于一第一区域形成一空间，而未去除位于一第二区域的虚置层及蚀刻停止层。此空间内露出第一半导体层。形成一第二半导体层于第一区域的空间内的第一半导体层上方。形成一第三半导体层于第一区域的空间内的第二半导体层上方。下凹隔离区，以露出第三半导体层的一上部。
根据本发明的另一方式，一种半导体装置，包括︰多个装置区域，其内设置包括一鳍式场效晶体管的多个主动电路元件；以及一非装置区域，设置于装置区域之间或包括一切割道及包括一虚置结构。鳍式场效晶体管包括：一鳍结构，具有包括一第一半导体层的一阱区、包括一第二半导体层的一应力源区以及包括一第三半导体层的一通道区。鳍式场效晶体管更包括：一隔离区，阱区埋入于其内，且自阱区露出通道区的至少一上部；以及一栅极结构，设置于一部分的鳍结构的上方。位于非装置区域的虚置结构包括：形成于第一半导体层上方的一第一虚置层以及形成于第一虚置层上方的一第二虚置层。
以上概略说明了本发明数个实施例的特征，使所属技术领域中具有通常知识者对于本发明的方式可更为容易理解。任何所属技术领域中具有通常知识者应了解到可轻易利用本发明作为其它制程或结构的变更或设计基础，以进行相同于此处所述实施例的目的及/或获得相同的优点。任何所属技术领域中具有通常知识者也可理解与上述等同的结构并未脱离本发明的精神和保护范围内，且可在不脱离本发明的精神和范围内，当可作更动、替代与润饰。

Claims (10)

1.一种半导体装置的制造方法，包括︰
形成一第一半导体层于一基底上方；
形成一蚀刻停止层于该第一半导体层上方；
形成一虚置层于该蚀刻停止层上方；
形成多个隔离区于该虚置层、该蚀刻停止层及该第一半导体层内；
去除该等隔离区之间的该虚置层及该蚀刻停止层，以形成一空间，该空间内露出该第一半导体层；
形成一第二半导体层于该空间内的该第一半导体层上方；
形成一第三半导体层于该空间内的该第二半导体层上方；以及
下凹该等隔离区，以露出该第三半导体层的一上部。
2.如权利要求1所述的半导体装置的制造方法，更包括：
形成一栅极结构于露出的该第三半导体层的该上部。
3.如权利要求1所述的半导体装置的制造方法，其中该第一半导体层包括一第一锗基半导体材料，该第二半导体层包括一硅或硅基半导体材料，且该第三半导体层包括一第二锗基半导体材料，且其中该第一及该第二锗基半导体材料的锗含量大于该第二半导体层的一锗含量。
4.如权利要求1所述的半导体装置的制造方法，其中该蚀刻停止层包括SiN、SiON、SiCN及SiOCN的其中至少一者，且该虚置层包括一多晶硅或一非晶硅。
5.如权利要求1所述的半导体装置的制造方法，其中该第二半导体层外延生长于该空间内的该第一半导体层上方，使第二半导体层的一上表面低于该空间的最上部。
6.一种半导体装置的制造方法，包括︰
形成一第一半导体层于一基底上；
形成一蚀刻停止层于该第一半导体层上方；
形成一虚置层于该蚀刻停止层上方；
形成多个隔离区于该虚置层、该蚀刻停止层及该第一半导体层内；
去除该等隔离区之间的该虚置层及该蚀刻停止层，以于一第一区域形成一空间，而未去除位于一第二区域的该虚置层及该蚀刻停止层，该空间内露出该第一半导体层；
形成一第二半导体层于该第一区域的该空间内的该第一半导体层上方；
形成一第三半导体层于该第一区域的该空间内的该第二半导体层上方；以及
下凹该等隔离区，以露出该第三半导体层的一上部。
7.如权利要求6所述的半导体装置的制造方法，其中形成该等隔离区的步骤包括：
于该虚置层、该蚀刻停止层及该第一半导体层内形成多个沟槽；
形成绝缘材料于该等沟槽内及其上方；以及
去除形成于该等沟槽上方的该绝缘材料。
8.如权利要求6所述的半导体装置的制造方法，其中该第一半导体层包括一第一锗基半导体材料，该第二半导体层包括一硅或硅基半导体材料，且该第三半导体层包括一第二锗基半导体材料，且其中该第一及该第二锗基半导体材料的锗含量大于该第二半导体层的一锗含量。
9.一种半导体装置，包括︰
多个装置区域，其内设置包括一鳍式场效晶体管的多个主动电路元件；以及
一非装置区域，设置于该等装置区域之间或包括一切割道及包括一虚置结构，其中：
该鳍式场效晶体管包括：
一鳍结构，具有包括一第一半导体层的一阱区、包括一第二半导体层的一应力源区以及包括一第三半导体层的一通道区；
一隔离区，该阱区埋入于其内，且自该阱区露出该通道区的至少一上部；以及
一栅极结构，设置于一部分的该鳍结构的上方；以及
位于该非装置区域的该虚置结构包括：
一第一虚置层，形成于该第一半导体层上方，且由不同于该应力源区的材料制成；以及
一第二虚置层，形成于该第一虚置层上方，且由不同于该通道区的材料制成。
10.如权利要求9所述的半导体装置，其中该第一虚置层包括SiN、SiON、SiCN及SiOCN的其中至少一者，且该第二虚置层包括一多晶硅或一非晶硅。
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