TW201711092A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201711092A TW201711092A TW104139593A TW104139593A TW201711092A TW 201711092 A TW201711092 A TW 201711092A TW 104139593 A TW104139593 A TW 104139593A TW 104139593 A TW104139593 A TW 104139593A TW 201711092 A TW201711092 A TW 201711092A
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Classifications
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- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
本揭露提供一種半導體裝置之製造方法,在上述方法中,一第一半導體層形成於一基底上方。一蝕刻停止層形成於第一半導體層上方。一虛置層形成於蝕刻停止層上方。多個隔離區形成於虛置層、蝕刻停止層及第一半導體層內。去除位於隔離區之間的虛置層及蝕刻停止層,以形成一空間。第一半導體層露出於空間內。一第二半導體層形成於空間內的第一半導體層上方。一第三半導體層形成於空間內的第二半導體層上方。下凹隔離區,以露出第三半導體層的一上部。本揭露亦提供一種半導體裝置。
Description
本揭露係關於一種半導體積體電路,且特別是關於一種具有鰭式結構的半導體裝置及其製造方法。
隨著半導體業尋求更高裝置密度、更高效能及更低成本,已進展至奈米技術製程世代,由於製造與設計問題的挑戰,因而發展出三維設計,例如,鰭式場效電晶體(Fin FET)。Fin FET裝置通常包括具有高縱寬比的半導體鰭,且其中形成半導體裝置的通道及源極/汲極區。閘極沿著鰭結構側邊而形成於上方(例如,包圍),利用增加通道及源極/汲極區的表面積的優勢,產生更快速、更具可靠度及更好控制的半導體電晶體裝置。在Fin FET裝置中,鰭結構的上部作為通道,而鰭結構的下部作為井區。另外,Fin FET的源極/汲極(S/D)部內利用選擇性生長矽鍺(SiGe)的應變材料,可用於增加載子遷移率。舉例來說,施加於PMOS裝置的通道的壓縮應力,有益於增加通道內的電洞遷移率。相似地,施加於NMOS裝置的通道的拉伸應力,有益於增加通道內的電子遷移率。
根據一些實施例,本揭露提供一種半導體裝置之製造方法,包括:形成一第一半導體層於一基底上方;形成一
蝕刻停止層於第一半導體層上方;形成一虛置層於蝕刻停止層上方;形成多個隔離區於虛置層、蝕刻停止層及第一半導體層內;去除隔離區之間的虛置層及蝕刻停止層,以形成一空間,空間內露出第一半導體層;形成一第二半導體層於空間內的第一半導體層上方;形成一第三半導體層於空間內的第二半導體層上方;以及下凹隔離區,以露出第三半導體層的一上部。
根據一些實施例,本揭露提供一種半導體裝置之
製造方法,包括:形成一第一半導體層於一基底上;形成一蝕刻停止層於第一半導體層上方;形成一虛置層於蝕刻停止層上方;形成多個隔離區於虛置層、蝕刻停止層及第一半導體層內;去除隔離區之間的虛置層及蝕刻停止層,以於一第一區域形成一空間,而未去除位於一第二區域的虛置層及蝕刻停止層,空間內露出第一半導體層;形成一第二半導體層於第一區域的空間內的第一半導體層上方;形成一第三半導體層於第一區域的空間內的第二半導體層上方;以及下凹隔離區,以露出第三半導體層的一上部。
根據一些實施例,本揭露提供一種半導體裝置,
包括:多個裝置區域,其內設置包括一鰭式場效電晶體的多個主動電路元件;以及一非裝置區域,設置於裝置區域之間或包括一切割道及包括一虛置結構。其中,鰭式場效電晶體包括:一鰭結構,具有包括一第一半導體層的一井區、包括一第二半導體層的一應力源區以及包括一第三半導體層的一通道區;一隔離區,井區埋入於其內,且自井區露出通道區的至少一上部;以及一閘極結構,設置於一部分的鰭結構的上方。其中,
位於非裝置區域的虛置結構包括:一第一虛置層,形成於第一半導體層上方,且由不同於應力源區的材料製成;以及一第二虛置層,形成於第一虛置層上方,且由不同於通道區的材料製成。
1、10‧‧‧基底
2‧‧‧隔離層
3‧‧‧鰭結構
4‧‧‧井區
5‧‧‧應力源區
6‧‧‧通道區
7、80‧‧‧閘極結構
20‧‧‧(SiGe)第一半導體層
30‧‧‧蝕刻停止層
40‧‧‧虛置層
45‧‧‧空間
50‧‧‧隔離層/STI層
52‧‧‧突出物
54‧‧‧凹口
60‧‧‧第二半導體層
70‧‧‧第三半導體層
82‧‧‧閘極介電層
84‧‧‧功函數調整層
86‧‧‧閘極電極層
b‧‧‧層位
D‧‧‧深度
DR‧‧‧裝置區域
H1、H2‧‧‧高度
NDR‧‧‧非裝置區域
S‧‧‧間隔
W‧‧‧寬度
第1圖係繪示出根據本揭露一實施例之鰭式場效電晶體(Fin FET)裝置立體示意圖。
第2至9圖係繪示出根據本揭露一實施例之製造鰭式場效電晶體裝置之連續製程剖面示意圖。
第10至11圖繪示出根據本揭露一實施例之製造鰭式場效電晶體裝置之其中一製程剖面示意圖。
可理解的是以下的揭露內容提供許多不同的實施
例或範例,以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化本揭露內容。當然,這些僅為範例說明並非用以限定本發明。舉例來說,元件的尺寸大小並未局限於以下揭露的範圍或數值,但取決於製程條件及/或所需的裝置特性。再者,若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方,即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施
例。為了達到簡化及明確目的,各種不同的特徵部件可任意地依不同的尺寸比例繪示。
再者,在空間上的相關用語,例如”之下”、”
下方”、”下”、”上方”、”上”等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外,還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位(旋轉90度或其他方位)且此處所使用的空間上的相關符號同樣有相應的解釋。另外,”由...製成”之用語也意指”包括”或”由...組成”。
第1圖係繪示出根據本揭露一實施例之鰭式場效
電晶體(Fin FET)裝置立體示意圖。
Fin FET裝置包括在其他特徵部件之中的一基底
1、一隔離層2、一鰭結構3及一閘極結構7。
多個鰭結構3設置於基底1上方。每一鰭結構3包括
一井區4、一應力源(stressor)區5及一通道區6。應力源區5施加一適當的應力(拉伸或壓縮)於通道區6。
鰭結構3的井區4由相同於基底1的材料製成且字
基底1連續性延伸。在其他實施例中,井區形成於基底1上方。
在第1圖中,三個鰭結構3設置於基底1上方。然
而,鰭結構的數量並未侷限於三個。上述數量可少至一個或多至三個以上。另外,一或多個虛置鰭結構可設置於鄰近鰭結構3的兩側,以在圖案畫製程中改善圖案精確性(pattern fidelity)。在一些實施例中,鰭結構3的寬度W約在5nm至50nm
的範圍,或在其他實施例中約在5nm至20nm的範圍。在一些實施例中,鰭結構3的高度H1約在100nm至300nm的範圍,或在其他實施例中約在50nm至100nm的範圍。
鰭結構3之間的空間及/或單一鰭結構與形成於基
底1上的另一元件之間的空間係填入一隔離絕緣層2(或稱為淺溝槽隔離(STI)層),其包括一絕緣材料。
位於閘極結構7下方的鰭結構3的下部稱為一井區
4,且鰭結構3的上部稱為一通道區6。在本揭露的一實施例中,鰭結構3更包括一應力源區5位於井區4與通道區6之間。在閘極結構7下方,井區4及應力源區5埋入一隔離絕緣層2內,且通道區6自隔離絕緣層2突出。通道區6的一下部也可埋入隔離絕緣層2至約1nm至5nm範圍的一深度D。在一些實施例中,通道區6的高度H2約在20nm至100nm的範圍,或在其他實施例中約在30nm至60nm的範圍。
一閘極結構覆蓋自隔離絕緣層2突出的通道區6,
且閘極結構包括覆蓋有閘極電極(未繪示)的一閘極介電層。
未被閘極結構7覆蓋的部分的通道區6作為MOS FET的源極及/或汲極。
藉由摻雜適合的雜質於源極及汲極區內,以於未
被閘極結構7覆蓋的的通道區6內形成源極及汲極區。矽或鍺的合金及一金屬(例如,Co、Ni、W、Ti或Ta)形成於源極及汲極區上。
再者,一內層絕緣層(未繪示)覆蓋閘極結構7及
源極/汲極區,且設置必須的接線及/或介層(via)/接觸
(contact)孔,以完成半導體裝置。
第2至9圖係繪示出根據本揭露一實施例之製造鰭
式場效電晶體裝置之連續製程剖面示意圖。除了鰭結構數量以外,第2至9圖係對應第1圖中a-a線的剖面示意圖。可以理解的是可在第2至9圖所示的製程進行之前、期間及之後進行其他操作步驟,且在上述方法的其他實施例中,可取代或省略以下所述的某些操作步驟。操作步驟/製程的順序可相互交換。
第2圖係繪示出具有鰭結構的半導體FET(Fin
FET)的其中一製造情形的剖面示意圖。
在第2圖中,一第一半導體層20形成於一基底10上
方。在本揭露一實施例中,第一半導體層20包括Si1-xGex,其中x為0.1至0.9,或在其他實施例中,x約在0.4至0.9的範圍。在本揭露中,Si1-xGex可簡稱為SiGe。
基底10可為一p型矽基底,其具有一雜質濃度且約
在1×1015cm-3至5×1015cm-3的範圍。在其他實施例中,基底10可為一n型矽基底,其具有一雜質濃度且約在1×1015cm-3至5×1015cm-3的範圍。
另外,基底10可包括其他元素半導體,例如鍺;
化合物半導體,包括IV-IV族化合物半導體(例如,SiC及SiCGe)、III-V族化合物半導體(例如,GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP);或其組合。在一實施例中,基底10為絕緣層上覆矽(SOI)基底上的一矽層。基底10可包括不同的區域,其已摻雜適合的雜質(例如,p型或n型導電物)。
SiGe第一半導體層20係磊晶生長於Si基底10上
方。在一些實施例中,為了抑制差排或其他缺陷,SiGe第一半導體層20內Ge的含量(x)約在0.15至0.3的範圍。在一些實施例中,第一半導體層20的厚度約在500nm至2000nm的範圍,或在其他實施例中,約在1000nm至1500nm的範圍。適當地摻雜雜質於SiGe第一半導體層20內。雜質可於磊晶生長期間導入或於生長SiGe第一半導體層20之後藉由使用離子佈植方法導入。摻雜物可為用於n型Fin FET的硼(BF2)或用於p型Fin FET的磷。SiGe第一半導體層20將成為Fin FET的井區。
若基底10由SiGe製成,SiGe第一半導體層20可為
SiGe基底的一上部。
如第2圖所示,一蝕刻停止層30形成於SiGe第一半
導體層20上方。再者,一虛置層40形成蝕刻停止層30上方。
蝕刻停止層30由對虛置層40及一隔離層50(參見
第3圖)具有適合蝕刻選擇比(例如,10或以上)的材料製成。
蝕刻停止層30由一或多層的絕緣材料製成。在本揭露的一實施例中,蝕刻停止層30包括SiN、SiON、SiCN或SiOCN。在一些實施例中,蝕刻停止層30可包括氧化矽。在一些實施例中,蝕刻停止層30的厚度約在2nm至20nm的範圍,或在其他實施例中,約在5nm至10nm的範圍。在其他實施例中,蝕刻停止層30可包括導電材料或半導體材料(例如,鍺)。
蝕刻停止層30可藉由物理氣相沉積(physical
vapor deposition,PVD)(例如,濺鍍法)、化學氣相沉積(chemical vapor deposition,CVD)、電漿輔助化學氣相沉積
(plasma enhanced CVD,PECVD)、常壓化學氣相沉積(atmospheric pressure CVD,APCVD)、低壓化學氣相沉積(low-pressure CVD,LPCVD)、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)、原子層沉積(atomic layer deposition,ALD)及/或其他製程形成。
虛置層40由對蝕刻停止層30及一隔離層50具有適
合蝕刻選擇比(例如,10或以上)的材料製成。在一實施例中,虛置層40由Si或Si基化合物製成。當使用Si時,Si虛置層40為多晶Si層或非晶Si層。取決於蝕刻停止層30的材料,Si虛置層40可為結晶Si。在其他實施例中,虛置層40由其他半導體材料製成,例如SiGe或Ge,或由絕緣材料製成,例如氧化物或氮化物。虛置層40可由金屬材料或金屬化合物(例如,Ti、Ta、TiN及TaN)製成。在一些實施例中,虛置層40的厚度約在20nm至100nm的範圍,或在其他實施例中,約在30nm至60nm的範圍。
可藉由PVD、PECVD、APCVD、LPCVD、HDPCVD
及/或ALD及/或其他製程形成虛置層40。
如第3圖所示,形成隔離層50。在一實施例中,隔
離層50為淺溝槽隔離(STI)層。
為了形成隔離層50,藉由使用微影操作步驟形成
一阻劑圖案於虛置層40上方。接著,利用阻劑圖案作為蝕刻罩幕,進行一圖案化操作步驟,以在虛置層40、蝕刻停止層30及第一半導體層20內形成多個溝槽。在一些實施例中,溝槽延伸至基底10。在一些實施例中,相鄰溝槽之間的間隔S(其將定
義出Fin FET的通道寬度)約在5nm至50nm的範圍,或在其他實施例中約在5nm至20nm的範圍。溝槽通常為錐型,其具有較小的下部及較大的上部。
形成溝槽之後,填入一或多層絕緣材料於溝槽
內。舉例來說,絕緣材料包括由LPCVD、電漿CVD(plasma CVD)或流動式CVD(flowable CVD)所形成的二氧化矽。在流動式CVD中,以流動的介電材料取代氧化矽進行沉積。顧名思義,流動式介電材料為沉積期間可”流動”,以填入高深寬比的間隙或空間。通常各種不同的化學物質係加入於含矽前驅物中,以容許沉積膜層流動。在一些實施例中,加入氮氫化物鍵結。
流動式介電前驅物的範例,特別是流動式氧化矽前驅物,包括矽酸鹽、矽氧烷(siloxane)、甲基矽酸鹽類(methyl silsequioxane,MSQ)、含氫矽酸鹽類(hydrogen silsequioxane,HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane,PSZ)、全氫聚矽氮烷(perhydro-polysilazane,PHPS)、四乙氧基矽烷(tetraethoxysilane,TEOS)或甲矽烷基胺(silyl-amine)(例如,三甲矽烷基胺(trisilylamine,TSA))。這些流動式氧化矽材料係形成於一多重操作(multiple-operation)製程。在沉積流動式膜層之後,進行固化並接著進行退火,以去除不需要的元素而形成氧化矽。當去除不需要的元素時,流動式膜層變得緻密並收縮。在一些實施例中,導入多重退火製程。流動式膜層進行一次以上的固化及退火,其溫度可約在300℃至800℃的範圍,或約在300℃至500℃的範圍。在一些實施例中,絕緣材料可包括SOG、SiO、SiON、SiOCN及/或氟摻雜矽玻璃(FSG)
形成。
絕緣材料形成於溝槽內,並且位於虛置層40上表
面上。進行一平坦化操作步驟,例如化學機械研磨(chemical mechanical polishing,CMP)法及/或回蝕刻製程,而得到如第3圖所示的淺溝槽隔離(STI)層50。
接下來,如第4圖所示,去除位於STI層50之間的
虛置層40,以形成空間45。實施乾蝕刻及/或濕蝕刻,以去除虛置層40。由於蝕刻停止層30形成於虛置層40的底部,因此可進行一適合的過蝕刻,使蝕刻停止層30的表面上實質上未餘留虛置層。
接著,第5圖所示,去除蝕刻停止層30。實施乾蝕
刻及/或濕蝕刻,以去除蝕刻停止層30。當蝕刻停止層30由氮化物基材料(例如,SiN)製成,且STI層50由氧化物基材料製成時,使用H3PO4的濕蝕刻可去除對STI層50及SiGe第一半導體層20具有高蝕刻選擇比的蝕刻停止層30。
如第6圖所示,在去除蝕刻停止層30且露出第一半
導體層20的表面之後,一第二半導體層60形成於第一半導體層20上方,接著形成一第三半導體層70於第二半導體層60上方。
在一實施例中,第二半導體層60為矽或矽基化合
物半導體(例如,SiGe)。當使用SiGe作為第二半導體層60,第二半導體層60的Ge含量小於SiGe第一半導體層20中的Ge含量。在一些實施例中,第二半導體層60的Ge含量(SixGe1-x中的x)為0.1或0.1以下。第二半導體層60作為一應力源區,以施加應力至通道區。
第二半導體層60係磊晶生長於空間45(藉由去除
虛置層40所形成)內的第一半導體層20上。可藉由使用SiH4及/或SiH2Cl2及/或GeH4作為氣體源,且約在300℃至800℃的溫度範圍及約在10Torr至100Torr的壓力範圍下進行Si或SiGe第二半導體層60的磊晶生長。在一些實施例中,第二半導體層60的厚度約在10nm至30nm的範圍,或在其他實施例中約在13nm至20nm的範圍。
第三半導體層70由鍺或鍺基半導體(例如,SiGe)
製成。在一些實施例中,當使用SiGe作為第三半導體層70,第三半導體層70的Ge含量(SixGe1-x中的x)約在0.4至0.8的範圍。
第三半導體層70係磊晶生長於空間45內的第二半
導體層60上。可藉由使用SiH4及/或SiH2Cl2及/或GeH4作為氣體源,且約在500℃至700℃的溫度範圍及約在10Torr至100Torr的壓力範圍下進行Si或SiGe第三半導體層70的磊晶生長。
再者,進行一平坦化操作步驟,例如CMP及/或回
蝕刻製程,以去除位於STI層50上方的第三半導體層70的部分而得到如第7圖所示的結構。
接下來,如第8圖所示,藉由去除局部的STI層50
而露出第三半導體層70的上部,以得到Fin FET的通道區。可利用一回蝕刻製程以去除(下凹)局部的STI層50。藉由調整蝕刻時間,餘留的STI層50可得到所需厚度。在第8圖中,第二半導體層60並未露出且埋入於STI層50內。然而,在一些實施例中,第二半導體層60的上部稍微露出於STI層50上方。
在局部露出第三半導體層70的上部之後,一閘極
結構80形成於露出的第三半導體層70上方,如第9圖所示。一閘極介電材料及一閘極電極材料形成於STI層50及通道區(露出的第三半導體層)上方,接著進行圖案化操作步驟而得到包括一閘極電極層86及一閘極介電層82的閘極結構80。在一實施例中,閘極電極層86為多晶矽。在一些實施例中,可藉由使用包括氮化矽層及氧化層的硬式罩幕來進行多晶矽層的圖案化。閘極介電層可為氧化矽且藉由CVD、PVD、ALD、電子束蒸鍍或其他適合的製程形成。在一些實施例中,閘極結構80的寬度約在30nm至60nm的範圍。
在某些實施例中,閘極介電層82包括一或多層的
介電材料,例如氧化矽、氮化矽或高介電常數(high-k)介電材料、其他適合的介電材料及/或其組合。high-k介電材料的範例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的high-k介電材料及/或其組合。
閘極電極層86包括一或多層的導電材料,例如多
晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他適合材料及/或其組合。閘極結構可使用先閘極或取代閘極(後閘極)技術形成。
在某些實施例中,一或多層功函數調整層84夾設
於閘極介電層82與閘極電極層86之間。功函數調整層84可由導電材料製成,例如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC或為這些材料的二或二層
以上所構成的多層結構。對於n通道Fin FET而言,一或多層的TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi係作為功函數調整層,且對於p通道Fin FET而言,一或多層的TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co係作為功函數調整層。
功函數調整層可藉由ALD、PVD、CVD、電子束蒸鍍、或其他適合製程形成。再者,可使用不同金屬材料各自形成n型通道Fin FET及p型通道Fin FET的功函數調整層。
也可使用具有應變材料的上升磊晶結構來製作源
極及汲極區。
在本實施例中,在虛置層40、蝕刻停止層30及第
一半導體層20的溝槽蝕刻以形成STI層50(參見第3圖)期間,取決於蝕刻停止層30的蝕刻條件及/或材料,溝槽側壁在蝕刻停止層30的層位變得不平坦。舉例來說,若蝕刻停止層30在蝕刻期間的蝕刻多於虛置層40及第一半導體層20,溝槽具有一突出物位於蝕刻停止層30的層位b,因而在STI層50形成一突出物52,如第10圖所示。若蝕刻停止層30在蝕刻期間的蝕刻少於虛置層40及第一半導體層20,溝槽具有一凹口位於蝕刻停止層30的層位b,因而在STI層50形成一凹口54,如第10圖所示。
再者,第2至9圖繪示出一裝置區域DR(參見第11
圖)位於基底上,其中形成包括Fin FET的主動電路元件。然而,一或多個非裝置區域NDR(參見第11圖)設置於基底上。
非裝置區域NDR不包括主動電路元件且可包括位於裝置區、切割道區或製程監測區之間的區域。在上述非裝置區域,不同於第4至5圖,虛置層40及蝕刻停止層30可不需去除。在上述情形
中,如第11圖所示,非裝置區域可包括一區域,其中虛置層40及蝕刻停止層30餘留於第一半導體層20上方。須注意的是餘留的虛置層40及蝕刻停止層30(連同虛置層)可在形成STI層50所進行的CMP製程期間抑制碟化問題。
可理解的是Fin FET可進一步進行CMOS製程而形
成不同的特徵部件,例如接觸連接窗(contact)/介層連接窗(via)、內連接金屬層、介電層及鈍化護層等等。
此處所述的各個不同的實施例或範例提供優於現
行技藝的幾個優點。舉例來說,在本揭露中,形成蝕刻停止層30及虛置層40於第一半導體層20上方、形成溝槽及STI層50、去除虛置層40及蝕刻停止層30、接著形成具有所需厚度的第二半導體層60。由於此操作步驟,因此可精確控制第二半導體層的厚度而具有高均勻性。第二半導體層的厚度均勻性(變異)小於5%。
可以理解的是此處並未述及所有優點,且沒有特
定的優點是所有實施例或範例所需的,且其他實施例或範例可提供不同的優點。
根據本揭露之一型態,一種半導體裝置之製造方
法,包括:形成一第一半導體層於一基底上方。形成一蝕刻停止層於第一半導體層上方。形成一虛置層於蝕刻停止層上方。
形成多個隔離區於虛置層、蝕刻停止層及第一半導體層內。去除隔離區之間的虛置層及蝕刻停止層,以形成一空間。此空間內露出第一半導體層。形成一第二半導體層於此空間內的第一半導體層上方。形成一第三半導體層於此空間內的第二半導體
層上方。下凹隔離區,以露出第三半導體層的一上部。
根據本揭露之另一型態,一種半導體裝置之製造
方法,包括:形成一第一半導體層於一基底上。形成一蝕刻停止層於第一半導體層上方。形成一虛置層於蝕刻停止層上方。
形成多個隔離區於虛置層、蝕刻停止層及第一半導體層內。去除隔離區之間的虛置層及蝕刻停止層,以於一第一區域形成一空間,而未去除位於一第二區域的虛置層及蝕刻停止層。此空間內露出第一半導體層。形成一第二半導體層於第一區域的空間內的第一半導體層上方。形成一第三半導體層於第一區域的空間內的第二半導體層上方。下凹隔離區,以露出第三半導體層的一上部。
根據本揭露之另一型態,一種半導體裝置,包括:
多個裝置區域,其內設置包括一鰭式場效電晶體的多個主動電路元件;以及一非裝置區域,設置於裝置區域之間或包括一切割道及包括一虛置結構。鰭式場效電晶體包括:一鰭結構,具有包括一第一半導體層的一井區、包括一第二半導體層的一應力源區以及包括一第三半導體層的一通道區。鰭式場效電晶體更包括:一隔離區,井區埋入於其內,且自井區露出通道區的至少一上部;以及一閘極結構,設置於一部分的鰭結構的上方。位於非裝置區域的虛置結構包括:形成於第一半導體層上方的一第一虛置層以及形成於第一虛置層上方的一第二虛置層。
以上概略說明了本發明數個實施例的特徵,使所
屬技術領域中具有通常知識者對於本揭露的型態可更為容易
理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎,以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內,且可在不脫離本揭露之精神和範圍內,當可作更動、替代與潤飾。
20‧‧‧(SiGe)第一半導體層
30‧‧‧蝕刻停止層
40‧‧‧虛置層
50‧‧‧隔離層/STI層
60‧‧‧第二半導體層
70‧‧‧第三半導體層
DR‧‧‧裝置區域
NDR‧‧‧非裝置區域
Claims (10)
- 一種半導體裝置之製造方法,包括:形成一第一半導體層於一基底上方;形成一蝕刻停止層於該第一半導體層上方;形成一虛置層於該蝕刻停止層上方;形成多個隔離區於該虛置層、該蝕刻停止層及該第一半導體層內;去除該等隔離區之間的該虛置層及該蝕刻停止層,以形成一空間,該空間內露出該第一半導體層;形成一第二半導體層於該空間內的該第一半導體層上方;形成一第三半導體層於該空間內的該第二半導體層上方;以及下凹該等隔離區,以露出該第三半導體層的一上部。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,更包括:形成一閘極結構於露出的該第三半導體層的該上部。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第一半導體層包括一第一鍺基半導體材料,該第二半導體層包括一矽或矽基半導體材料,且該第三半導體層包括一第二鍺基半導體材料,且其中該第一及該第二鍺基半導體材料的鍺含量大於該第二半導體層的一鍺含量。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該蝕刻停止層包括SiN、SiON、SiCN及SiOCN的其中至少一者,且該虛置層包括一多晶矽或一非晶矽。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第二半導體層磊晶生長於該空間內的該第一半導體層上方,史第二半導體層的一上表面低於該空間的最上部。
- 一種半導體裝置之製造方法,包括:形成一第一半導體層於一基底上;形成一蝕刻停止層於該第一半導體層上方;形成一虛置層於該蝕刻停止層上方;形成多個隔離區於該虛置層、該蝕刻停止層及該第一半導體層內;去除該等隔離區之間的該虛置層及該蝕刻停止層,以於一第一區域形成一空間,而未去除位於一第二區域的該虛置層及該蝕刻停止層,該空間內露出該第一半導體層;形成一第二半導體層於該第一區域的該空間內的該第一半導體層上方;形成一第三半導體層於該第一區域的該空間內的該第二半導體層上方;以及下凹該等隔離區,以露出該第三半導體層的一上部。
- 如申請專利範圍第6項所述之半導體裝置之製造方法,其中形成該等隔離區的步驟包括:於該虛置層、該蝕刻停止層及該第一半導體層內形成多個溝槽;形成絕緣材料於該等溝槽內及其上方;以及去除形成於該等溝槽上方的該絕緣材料。
- 如申請專利範圍第6項所述之半導體裝置之製造方法,其中 該第一半導體層包括一第一鍺基半導體材料,該第二半導體層包括一矽或矽基半導體材料,且該第三半導體層包括一第二鍺基半導體材料,且其中該第一及該第二鍺基半導體材料的鍺含量大於該第二半導體層的一鍺含量。
- 一種半導體裝置,包括:多個裝置區域,其內設置包括一鰭式場效電晶體的多個主動電路元件;以及一非裝置區域,設置於該等裝置區域之間或包括一切割道及包括一虛置結構,其中:該鰭式場效電晶體包括:一鰭結構,具有包括一第一半導體層的一井區、包括一第二半導體層的一應力源區以及包括一第三半導體層的一通道區;一隔離區,該井區埋入於其內,且自該井區露出該通道區的至少一上部;一閘極結構,設置於一部分的該鰭結構的上方;以及位於該非裝置區域的該虛置結構包括:一第一虛置層,形成於該第一半導體層上方,且由不同於該應力源區的材料製成;以及一第二虛置層,形成於該第一虛置層上方,且由不同於該通道區的材料製成。
- 如申請專利範圍第9項所述之半導體裝置,其中該第一虛置層包括SiN、SiON、SiCN及SiOCN的其中至少一者,且該第二虛置層包括一多晶矽或一非晶矽。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10978351B2 (en) | 2017-11-17 | 2021-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer between substrate and isolation structure |
TWI805623B (zh) * | 2017-11-30 | 2023-06-21 | 美商英特爾股份有限公司 | 用於先進積體電路結構製造之具有單閘極間隙的鰭部修整隔離技術 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106486377B (zh) * | 2015-09-01 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | 鳍片式半导体器件及其制造方法 |
US9472620B1 (en) | 2015-09-04 | 2016-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
CN106611787A (zh) * | 2015-10-26 | 2017-05-03 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US9704966B1 (en) * | 2016-07-25 | 2017-07-11 | Globalfoundries Inc. | Fin-based RF diodes |
TWI746673B (zh) | 2016-12-15 | 2021-11-21 | 台灣積體電路製造股份有限公司 | 鰭式場效電晶體裝置及其共形傳遞摻雜方法 |
US10276691B2 (en) | 2016-12-15 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conformal transfer doping method for fin-like field effect transistor |
US10680084B2 (en) | 2017-11-10 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial structures for fin-like field effect transistors |
CN110581102B (zh) * | 2018-06-07 | 2021-11-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US11437472B2 (en) * | 2018-06-28 | 2022-09-06 | Intel Corporation | Integrated circuit structures having germanium-based channels |
KR20210043842A (ko) | 2019-10-14 | 2021-04-22 | 삼성전자주식회사 | 반도체 장치 |
US11837651B2 (en) * | 2020-04-28 | 2023-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having isolation fins |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
CN101142203A (zh) * | 2005-01-21 | 2008-03-12 | 詹森药业有限公司 | 用作离子通道开放剂的新香豆素衍生物 |
US7425740B2 (en) | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
US7879659B2 (en) | 2007-07-17 | 2011-02-01 | Micron Technology, Inc. | Methods of fabricating semiconductor devices including dual fin structures |
US8048723B2 (en) | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
US8776734B1 (en) | 2008-05-19 | 2014-07-15 | Innovative Environmental Solutions, Llc | Remedial system: a pollution control device for utilizing and abating volatile organic compounds |
KR101061178B1 (ko) | 2008-12-30 | 2011-09-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
US8053299B2 (en) | 2009-04-17 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8143121B2 (en) | 2009-10-01 | 2012-03-27 | Nanya Technology Corp. | DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof |
US8415718B2 (en) | 2009-10-30 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming epi film in substrate trench |
US8395195B2 (en) | 2010-02-09 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-notched SiGe FinFET formation using condensation |
US8637359B2 (en) | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US8618556B2 (en) | 2011-06-30 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design and method of fabricating same |
US8609518B2 (en) | 2011-07-22 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-growing source/drain regions from un-relaxed silicon layer |
US8580643B2 (en) * | 2011-08-24 | 2013-11-12 | Globalfoundries Inc. | Threshold voltage adjustment in a Fin transistor by corner implantation |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US8742509B2 (en) | 2012-03-01 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for FinFETs |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US8860148B2 (en) * | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US8673718B2 (en) * | 2012-07-09 | 2014-03-18 | Globalfoundries Inc. | Methods of forming FinFET devices with alternative channel materials |
US8633516B1 (en) | 2012-09-28 | 2014-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain stack stressor for semiconductor device |
US8497177B1 (en) | 2012-10-04 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9006786B2 (en) * | 2013-07-03 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of semiconductor device |
US9306069B2 (en) | 2013-09-11 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure of fin field effect transistor |
US8921191B2 (en) * | 2013-02-05 | 2014-12-30 | GlobalFoundries, Inc. | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8927373B2 (en) * | 2013-03-13 | 2015-01-06 | Samsung Electronics Co, Ltd. | Methods of fabricating non-planar transistors including current enhancing structures |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
US9331176B2 (en) | 2013-04-25 | 2016-05-03 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors, including forming source and drain regions in recesses of semiconductor fins |
US8796666B1 (en) | 2013-04-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
US9006842B2 (en) | 2013-05-30 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning strain in semiconductor devices |
US9099570B2 (en) | 2013-12-05 | 2015-08-04 | Stmicroelectronics, Inc. | Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices |
US9472620B1 (en) * | 2015-09-04 | 2016-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
-
2015
- 2015-09-04 US US14/846,404 patent/US9472620B1/en active Active
- 2015-11-27 TW TW104139593A patent/TWI604516B/zh active
- 2015-11-30 CN CN201510860676.2A patent/CN106505103B/zh active Active
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10978351B2 (en) | 2017-11-17 | 2021-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer between substrate and isolation structure |
US10991628B2 (en) | 2017-11-17 | 2021-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer between substrate and isolation structure |
US11948842B2 (en) | 2017-11-17 | 2024-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer between substrate and isolation structure |
TWI805623B (zh) * | 2017-11-30 | 2023-06-21 | 美商英特爾股份有限公司 | 用於先進積體電路結構製造之具有單閘極間隙的鰭部修整隔離技術 |
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