CN106158854B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN106158854B
CN106158854B CN201510777698.2A CN201510777698A CN106158854B CN 106158854 B CN106158854 B CN 106158854B CN 201510777698 A CN201510777698 A CN 201510777698A CN 106158854 B CN106158854 B CN 106158854B
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layer
gate electrode
batcher
grid
fin
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CN106158854A (zh
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林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供一种半导体器件，包括第一和第二FinFET以及由绝缘材料制成并且设置在第一和第二FinFET之间的分隔塞。第一FinFET包括在第一方向上延伸的第一鳍结构，在第一鳍结构上方形成的第一栅极电介质和在第一栅极电介质上方形成并且在垂直于第一方向的第二方向上延伸的第一栅电极。第二FinFET包括第二鳍结构，在第二鳍结构上方形成的第二栅极电介质和在第一栅极电介质上方形成并且在第二方向上延伸的第二栅电极。当从上面看时，分隔塞的端部形状呈凹形的弧形形状，而邻接分隔塞的第一栅电极的端部呈凸形的弧形形状。本发明实施例涉及半导体集成电路，更具体地，涉及具有鳍结构的半导体器件及其制造工艺。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体集成电路，更具体地，涉及具有鳍结构的半导体器件及其制造工艺。
背景技术
随着半导体工业已经进入纳米技术工艺节点，以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战导致了三维设计的发展，三维设计诸如鳍式场效应晶体管(FinFET)。通常地，FinFET器件包括具有高深宽比的半导体鳍并且在FinFET器件中形成半导体晶体管器件的沟道和源极/漏极区域。利用沟道和源极/漏极区域的增加的表面面积的优势，在鳍结构的侧的上方和沿着鳍结构的侧(例如，包裹)形成栅极以产生更快、更可靠以及更好控制的半导体晶体管器件。金属栅极结构和具有高电介电常数的高k栅极电介质通常用于FinFET器件，并且通过栅极替换技术制造。
发明内容
根据本发明的一个实施例，提供了一种半导体器件，包括：第一FinFET，所述第一FinFET包括第一鳍结构、第一栅极电介质以及第一栅电极，所述第一鳍结构在第一方向上延伸，所述第一栅极电介质形成在所述第一鳍结构上方，所述第一栅电极形成在所述第一栅极电介质上方并且在垂直于所述第一方向的第二方向上延伸；第二FinFET，所述第二FinFET包括第二鳍结构、第二栅极电介质和第二栅电极，所述第二栅极电介质形成在所述第二鳍结构上方，以及所述第二栅电极形成在所述第一栅极电介质上方并且在所述第二方向上延伸；以及分隔塞，由绝缘材料制成并且设置在所述第一FinFET和所述第二FinFET之间，其中，当从上面看时，所述分隔塞的端部形状具有凹形的弧形形状，而所述第一栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
根据本发明的另一实施例，还提供了一种用于制造半导器件的方法，包括：形成伪电极结构以及层间介电层，所述伪电极结构包括伪栅电极层和侧壁绝缘层，所述侧壁绝缘层设置在所述伪栅电极层的两个主侧处，以及所述层间介电层设置在所述伪电极层的两个主侧处；去除所述伪栅电极层的部分使得在所述侧壁绝缘层之间形成第一间隔和第二间隔，所述第一电极间隔和所述第二电极间隔通过柱分隔开，所述柱是所述伪栅电极层的剩余部分；在所述第一电极间隔和所述第二电极间隔中分别形成第一栅极结构和第二栅极结构；去除所述柱使得在所述第一栅极结构和所述第二栅极结构之间形成开口；以及通过利用绝缘材料填充所述开口来形成分隔塞。
根据本发明的又另一实施例，还提供了一种半导体器件，包括：FET，所述FET包括第一栅极介电层和金属栅电极；以及分隔塞，由绝缘材料制成并且相邻所述FET设置，其中，当从上面看时，所述分隔塞的端部具有凹形的弧形形状，而所述金属栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明。应该强调，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
根据本发明的一个实施例，图1A是具有鳍结构(FinFET)的半导体FET器件的示例性截面图，图1B是具有鳍结构的半导体FET器件的示例性顶视图，以及图1C是对应于图1B中封闭部分的具有鳍结构的半导体FET器件的示例性立体图。
图2至图12C示出了根据本发明的一个实施例的用于制造FinFET器件的示例性工艺。
图13A和图13B示出了FinFET器件的比较实例。
具体实施方式
应该理解，以下公开内容提供了许多不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定的实施例或实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，元件的尺寸不限制于公开的范围和数值，但是可以取决于工艺条件和/或器件的期望的特性。另外，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触而形成的实施例，也可以包括第一部件和第二部件之间可以形成附加部件使得第一部件和第二部件可以不直接接触的实施例。另外，为了简化和清楚的目的，可以任意地画出不同尺寸的各个部件。
而且，为便于描述，本文可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。另外，术语“由……组成”可以是“包括”，也可以是“由……构成”的意思。
根据本发明的一个实施例，图1A是具有鳍结构(FinFET)的半导体FET器件的示例性截面图，图1B是具有鳍结构的半导体FET器件的示例性顶视图，以及图1C是具有鳍结构的半导体FET器件的示例性立体图。图1A是沿图1B中的线X-X的截面图，以及图1C对应于图1B中的封闭部分A。在这些图中，为了简化省略了一些层/部件。图1A至图1C示出了已经形成金属栅极结构之后的器件结构。
FinFET器件1包括第一器件区1A和第二器件区1B。第一器件区1A包括一个或多个第一FinFET器件，并且第二器件区包括一个或多个第二FinFET器件。第一FinFET的沟道类型与第二FinFET的沟道类型相同或不同。
在一个实施例中，第一器件区1A包括p型MOSFET和第二器件区1B包括n型MOSFET。在其他实施例中，第一器件区和第二器件区包括p型MOSFET，第一器件区和第二器件区包括n型MOSFET，或第一器件区和第二器件区包括p型MOSFET和n型MOSFET。
FinFET器件1包括，除了其他部件，衬底10、鳍结构20、栅极电介质30和栅电极40。在本实施例中，衬底10是硅衬底。可选地，衬底10可以包括另一个元素半导体，诸如锗；包括IV-IV族化合物半导体(诸如SiC和SiGe)、III-V族化合物半导体(诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP)的化合物半导体；或它们的组合。在一个实施例中，衬底10可以是SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时，鳍结构可以从SOI衬底的硅层突出或可以从SOI衬底的绝缘层突出。在后一种情况下，SOI衬底的硅层可以用于形成鳍结构。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料也可以用作衬底10。衬底10可以包括已经适当地掺杂有杂质的各个区域(例如，p型或n型导电性)。
鳍结构20设置在衬底10上方。鳍结构20可以由与衬底10相同的材料组成并且可以连续地从衬底10延伸。在本实施例中，鳍结构由Si组成。鳍结构20的硅层可以是本征的，或适当地掺杂有n型杂质或p型杂质。
在图1A中，在第一器件区1A中和第二器件区1B中分别设置有两个鳍结构20。但是，鳍结构的数量不限制于两个(或四个)。数量可以是一个、两个、三个或五个或更多。此外，多个伪鳍结构中的一个可以相邻鳍结构20的两侧设置以改进在图案化工艺中的图案保真度。在一些实施例中，鳍结构20的宽度W1是在约5nm至约40nm的范围内，并且在特定的实施例中，鳍结构20的宽度W1可以在约7nm至约15nm的范围内。在一些实施例中，鳍结构20的高度是在约100nm至约300nm的范围内，并且在其他实施例中，鳍结构20的高度是在约50nm至100nm的范围内。
鳍结构20的位于栅电极40下方的下部称为阱层并且鳍结构20的上部称为沟道层。在栅电极40下方，阱层嵌入在隔离绝缘层50中，并且沟道层从隔离绝缘层50突出。沟道层的下部也可以嵌入在隔离绝缘层50中至约1nm至约5nm的深度。
在一些实施例中，阱层的高度是在约60nm至100nm的范围内，并且沟道层的高度是在约40nm至60nm的范围内。
此外，鳍结构20之间的间隔和/或一个鳍结构与另一个在衬底10上方形成的元件之间的间隔由包括绝缘材料的隔离绝缘层50(或称为“浅沟槽隔离(STI)”层)填充，并且层间介电层70设置在隔离绝缘层50上方。用于隔离绝缘层50和层间介电层70的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料的一层或多层。用于隔离绝缘层50的绝缘材料可以与用于层间介电层70的绝缘材料相同或不同。
鳍结构20的从隔离绝缘层50突出的沟道层被栅极介电层30覆盖，并且栅极介电层30进一步由栅电极40覆盖。沟道层的未被栅电极40覆盖的部分用作MOSFET(见图1B)的源极和/或漏极。鳍结构20在第一方向上延伸并且栅电极40在垂直于第一方向的第二方向上延伸。
在特定的实施例中，栅极介电层30包括介电材料(诸如氧化硅、氮化硅或高k介电材料)、其他合适的介电材料和/或它们的组合的一层或多层。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层30可以包括由二氧化硅制成的界面层。
栅电极40包括任何合适的材料(诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合)的一层或多层。在特定的实施例中，栅电极包括金属栅极层45。
在本发明的特定实施例中，一个或多个功函数调整层42也可以设置在栅极介电层30和金属栅极层45之间。功函数调整层可以包括单层或可选地多层结构，诸如具有选择性的功函数以提高器件性能的金属层(功函数金属层)、衬垫层、润湿层、粘合层、金属合金或金属硅化物的各个组合。功函数调整层由导电材料组成，导电材料诸如Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、或其他合适的金属材料的单层，或两个以上这些材料的多层。对于n沟道FinFET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi的一个或多个用作功函数调整层，并且对于p沟道FinFET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一个或多个用作功函数调整层。在一些实施例中，功函数调整层可以包括用于p沟道FinFET的第一金属材料(例如，在第一器件区1A中)和用于n沟道FinFET的第二金属材料(例如，在第二器件区1B中)。例如，用于p沟道FinFET的第一金属材料可以包括具有功函数的金属，该功函数基本上与衬底导电带的功函数对准，或至少基本上与鳍结构20的沟道层的导电带的功函数对准。同样地，例如，用于n沟道FinFET的第二金属材料可以包括具有功函数的金属，该功函数基本上与衬底价带的功函数对准，或至少基本上与鳍结构20的沟道层的价带的功函数对准。在一些实施例中，功函数调整层可以可选地包括多晶硅层。功函数调整层可以通过ALD(原子层沉积)、PVD、CVD、电子束蒸发或其他合适的工艺形成。另外，可以使用不同的金属层分别地形成用于n沟道FinFET和p沟道FinFET的功函数调整层。
通过在源极和漏极区中适当的掺杂杂质，在未被栅电极40覆盖的鳍结构中也可以形成源极和漏极区。Si或Ge的合金以及诸如Co、Ni、W、Ti或Ta的金属可以形成在源极和漏极区上。Si层和/或SiGe层可以外延地形成在源极-漏极区中以形成凸起的源极-漏极结构并且对沟道层施加适当的应力。
此外，侧壁绝缘层80设置在栅电极40的两侧处。栅电极40和源极/漏极区由层间介电层70覆盖并且设置必要的配线和/或通孔/接触孔以使半导体器件完整。
在一些实施例中，包括功能函数调整层42和金属栅极层45的栅电极40的宽度W2是在约20nm至40nm的范围内。在一些实施例中，当多个栅电极40在宽度方向上布置时(见图1B)，栅电极的间距是在约60nm至100nm的范围内。
如图1A至图1C所示，相邻的栅电极40通过由绝缘材料制成的分隔塞60彼此分隔开。在图1A所示的横截面中，分隔塞60呈具有较小的顶部尺寸(宽度)和较大的底部尺寸(宽度)的锥形。在特定的实施例中，在分隔塞的顶部处的宽度W3小于约20nm，并且在一些实施例中，宽度W3可以是在约5nm至约15nm的范围内。在特定的实施例中，在分隔塞的底部处的宽度W4小于约35nm，并且在一些实施例中，宽度W4可以是在约10nm至约30nm的范围内。此处，分隔塞的顶部对应于栅电极40的上表面并且分隔塞60的底部对应于栅极介电层30的底部或对应于隔离绝缘层50和层间介电层70之间的界面。用于分隔塞60的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺的硅酸盐玻璃(FSG)或低K介电材料，并且可以与用于隔离绝缘层50和/或层间介电层70的绝缘材料相同或不同。
用于分隔塞60的绝缘材料可以与用于隔离绝缘层50和/或层间介电层70的绝缘材料相同或不同。
图2至图12C示出了根据本发明的一个实施例的制造FinFET器件的示例性的有序工艺的截面图。应该理解，可以在如图2至图12C所示的工艺之前、期间和之后提供额外的操作，并且对于本方法的额外的实施例，可以替换或删除下述的一些操作。操作/工艺的顺序可以互换。另外，在公告号为第2013/0161762号的美国专利中公开通过栅极替换技术，用于在鳍结构上方制造金属栅极结构的一般性操作，该专利的全部内容结合于此作为参考。
为了制造鳍结构，通过，例如，热氧化工艺和/或化学汽相沉积(CVD)工艺在衬底10上方形成掩模层。例如，衬底10是具有杂质的p型硅衬底，该杂质的浓度在约1×1015cm-3和约1×1018cm-3的范围内。在其他实施例中，衬底10是具有杂质的n型硅衬底，该杂质的浓度在约1×1015cm-3和约1×1018cm-3的范围内。例如，在一些实施例中，掩模层包括垫氧化物(例如，氧化硅)层和氮化硅掩模层。
可以通过使用热氧化或CVD工艺形成垫氧化物层。可以通过诸如溅射方法的物理汽相沉积(PVD)、CVD、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)和/或其他工艺形成氮化硅掩模层。
在一些实施例中，垫氧化物层的厚度是在约2nm至约15nm的范围内，并且氮化硅掩模层的厚度是在约2nm至约50nm的范围内。在掩模层上方进一步形成掩模图案。例如，掩模图案是通过光刻形成的光刻胶图案。
通过将掩模图案用作蚀刻掩模，形成垫氧化物层106和氮化硅掩模层107的硬掩模图案100。在一些实施例中，硬掩模图案的宽度是在约5nm至约40nm的范围内。在特定的实施例中，硬掩模图案的宽度是在约7nm至约12nm的范围内。
如图2所示，通过将硬掩模图案用作蚀刻掩模，通过使用干蚀刻方法和/或湿蚀刻方法的沟槽蚀刻将衬底10图案化为鳍结构20。鳍结构20的高度是在约100nm至约300nm的范围内。在特定的实施例中，鳍结构20的高度是在约50nm至约100nm的范围内。当鳍结构的高度不均匀时，从衬底的高度可以从对应于鳍结构的平均高度的平面测得。
在本实施例中，块状硅晶圆可以用作起始材料并且构成衬底10。但是，在一些实施例中，其他类型的衬底可以用作衬底10。例如，绝缘体上硅(SOI)晶圆可以用作起始材料，并且SOI晶圆的绝缘层构成衬底10以及SOI晶圆的硅层用作鳍结构20。
如图3所示，隔离绝缘层50形成在衬底10上方以全面地覆盖鳍结构20。
隔离绝缘层50包括诸如氧化硅、氮氧化硅或氮化硅的绝缘材料的一层或多层，绝缘材料的一层或多层通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动的CVD形成。在可流动的CVD中，沉积除了氧化硅的可流动的介电材料。可流动的介电材料，如名字显示的，在沉积期间可以“流动”以填充具有高深宽比的间隙和间隔。通常地，将各个化学物质添加到含硅前体中以允许沉积的膜流动。在一些实施例中，添加氮氢键。可流动的介电前体的实例，特别是可流动的氧化硅前体包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、原硅酸四乙酯(TEOS)或诸如三甲硅烷基胺(TSA)的硅烷胺。这些可流动的氧化硅在多重操作工艺中形成。在沉积可流动的膜之后，对其固化并且然后退火以去除不期望的元素以形成氧化硅。当去除不期望的元素时，可流动的膜致密化和收缩。在一些实施例中，进行多重退火工艺。多次固化和退火可流动的膜。可流动的膜可以掺杂有硼和/或磷。在一些实施例中，隔离绝缘层50可以由SOG、SiO、SiON、SiOCN和/或氟掺的硅酸盐玻璃(FSG)的一层或多层形成。
在形成隔离绝缘层50之后，实施平坦化操作以去除隔离绝缘层50的部分和掩模层100，掩模层100包括垫氧化物层106和氮化硅掩模层107。然后，进一步去除隔离绝缘层50以暴露出将要变成沟道层的鳍结构20的上部，如图4所示。
在形成隔离绝缘层50之后，可以实施例如退火工艺的热工艺以提高隔离绝缘层50的质量。在特定的实施例中，在例如N2、Ar或He的惰性气体环境中，在约900℃至约1050℃的范围内的温度下，使用快速热退火(RTA)实施热工艺持续约1.5秒至10秒。
栅极氧化物层105和多晶硅层形成在隔离绝缘层50和暴露的鳍结构20上方，并且然后实施图案化操作以获得由多晶硅组成的多晶硅栅极层110。栅极氧化物层105可以是通过CVD、PVD、ALD、电子束蒸发或其他合适的工艺形成的氧化硅。在一些实施例中，多晶硅层的厚度是在约5nm至约100nm的范围内。多晶硅栅极层110和栅极氧化物层105是伪层，在栅极替换技术中最终被去除。
侧壁绝缘层80也形成在多晶硅栅极层110的两侧处。
此外，层间介电层70形成在多晶硅栅极层110之间的间隔中、侧壁绝缘层80之间，并且形成在多晶硅栅极层110上方。实施诸如回蚀刻工艺和/或化学机械抛光(CMP)工艺的平坦化操作以获得图5A至图5C中所示的结构。图5A是多晶硅栅极层110和层间介电层70形成之后的FinFET器件的截面图，图5B是多晶硅栅极层110和层间介电层70形成之后的FinFET器件的顶视图以及图5C是多晶硅栅极层110和层间介电层70形成之后的FinFET器件的多晶硅栅极层110和层间介电层70形成之后的FinFET器件的立体图。图5A是沿图5B中线X-X的截面图，以及图5C对应于图5B中的封闭部分B。
如图5B和图5C所示，在特定的实施例中，多晶硅栅极层110成线和间隔布置的形成，在一个具有等间距的方向上延伸。多晶硅栅极层110可以包括在平行于一个方向上延伸的另一线和间隔布置。
如图6所示，掩模图案120形成在图5C中示出的结构上方。例如，掩模图案由光刻胶层形成。在一些实施例中，形成的掩模图案120的宽度是在约20nm至约120nm的范围内，并且在其他实施例中，该宽度可以在约40nm至约60nm的范围内。
在一些实施例中，除了光刻胶层，掩模层120可以是硬掩模，在多晶硅蚀刻期间，硬掩模是由具有高蚀刻电阻抵抗力的材料形成的。硬掩模材料包括氧化硅、氮氧化硅或氮化硅或金属材料。
如图7所示，通过使用干蚀刻操作减小掩模图案120的宽度以获得期望的宽度。在一些实施例中，在干蚀刻之后，掩模图案120的宽度是在约5nm至约100nm的范围内，并且在其他实施例中，掩模图案120的宽度可以是在约10nm至约30nm的范围内。除了减小掩模图案的宽度，可以直接形成具有期望的宽度的掩模图案120。
如图8所示，通过使用掩模图案120，蚀刻多晶硅栅极层110的部分从而形成间隔125。在图8中以及后文中，省略层间介电层70的一个层70A以示出蚀刻的多晶硅栅极层110和间隔125，同时仍然示出其他层70B和70C。在一些实施例中，在3毫托至20毫托的压力下，通过使用气体的等离子体蚀刻对多晶硅栅极层实施蚀刻，气体包括CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2和/或He。通过去除多晶硅栅极层110的部分，在间隔125之间形成多晶硅柱110P。
如图9A所示，通过灰化工艺和/或湿洗工艺去除掩模图案120(例如，光刻胶图案)。
在图8中示出的多晶硅蚀刻中，多晶硅栅极层110的中心处的蚀刻率相对地高于在多晶硅栅极层110和侧壁绝缘层80之间的界面处的蚀刻率。相应地，从上面看多晶硅柱的端部形状具有凹形的弧形形状，如图9B中所示。换句话说，间隔125在多晶硅柱110P处具有凸形的弧形形状。
此外，在多晶硅蚀刻之后，多晶硅柱110P具有如图9C中示出的锥形，图9C是沿着图9A的线Y-Y’的截面图。测量的多晶硅柱110P的底部处与隔离绝缘层50的表面(或设置在鳍结构之间的栅极氧化物层105的表面)所成的锥角θ为90度或更大，并且在特定的实施例中，锥角θ可以是在约93度至约100度的范围内。在一些实施例中，在多晶硅蚀刻之后可以实施额外的蚀刻操作以调整多晶硅柱110P的形状/锥角。
如图10所示，金属栅极结构形成在多晶硅栅极柱110P之间的间隔125中，金属栅极结构包括金属栅电极40和栅极介电层30(在图10中未示出)。通过CVD、ALD或其他合适的膜形成方法来形成栅极介电层30。通过CVD、PVD(包括溅射)、ALD、电镀或其他合适的金属膜形成方法形成金属栅电极40。由于间隔125在其端部具有凸形的弧形形状，因此可以将用于金属栅电极40的金属材料填充至间隔125中，而不形成间隙或缝隙。
如图11所示，通过蚀刻操作去除多晶硅柱110P，进而形成开口130。蚀刻操作可以包括干蚀刻和/或湿蚀刻。
在去除多晶硅柱110P之后，通过使用，例如，CVD工艺在如图11所示的结构上方形成绝缘材料，并且用绝缘材料填充开口130。CVD工艺可以包括LPCVD工艺、等离子体CVD工艺和/或可流动的CVD工艺。在一些实施例中，在可流动的CVD工艺中，可以使用包括SiH4、NH3、N2、O2、N2O、Cl2和/或NO2的气体并且在约200℃至约1000℃的范围内的温度下实施沉积。
如图12A至图12C所示，在金属栅电极40上方形成绝缘材料的部分之后，通过平坦化操作去除侧壁绝缘层80和层间介电层70，获得分隔塞60。平坦化操作可以包括CMP和/或回蚀刻工艺。图12A是示例性的立体图，图12B是沿着图12A的线Y-Y’的示例性的截面图，以及图12C是在形成分隔塞60之后的示例性的顶视图。
如图12A和图12C所示，从上面看，分隔塞60的端部形状62具有凹形的弧形形状，而金属栅电极40的端部具有凸形的弧形形状。如图12B所示，分隔塞60呈锥形，并且测量的分隔塞60的底部处与隔离绝缘层50的表面(或设置在鳍结构之间的栅极氧化物层105的表面)所成的锥角θ为90度或更大。在一些实施例中，锥角θ是在约90度至约100度的范围内。
应该理解，FinFET可以经历进一步CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件。
另外，可以对平面型FET施加上述的栅极替换技术。
本文中描述的各个实施例或实例提供了优于现有技术的几个优势。如上述解释的，在本发明中，在金属栅电极40形成之后形成分隔塞。金属栅电极40的端部具有朝向分隔塞60的凸形的弧形形状，并且分隔塞60呈锥形。相反地，如图13A所示，当在金属栅电极形成之前形成分隔塞时，分隔塞的形状将呈倒锥形，并且如图13B所示，分隔塞的端部将呈凸形。在这种情况下，当形成用于金属栅电极的金属材料时，在分隔塞附近将出现空隙或缝隙。
但是，如上文所述，在图1A至图12C中所示的工艺中，将用于金属栅电极40的金属材料填充至间隔125中，而未形成间隙或缝隙。
可以理解，并非所有的优势都已经在本文中进行了必要的讨论，没有特别的优势需要用于所有的实施例或实例，并且其他实施例或实例可以提供不同的优势。
根据本发明的一个方面，半导体器件包括第一FinFET和第二FinFET，以及分隔塞，分隔塞由绝缘材料组成并且设置在第一FinFET和第二FinFET之间的。第一FinFET包括：第一鳍结构、第一栅极电介质和第一栅电极，其中，第一鳍结构在第一方向上延伸、第一栅极电介质形成在第一鳍结构上方，以及第一栅电极形成在第一栅极介电层上方并且在垂直于第一方向的第二方向上延伸。第二FinFET包括：第二鳍结构、第二栅极电介质和第二栅电极，其中，第二栅极电介质形成在第二鳍结构上方，以及第二栅电极形成在第一栅极电介质上方并且在第二方向上延伸。当从上面看时，分隔塞的端部形状具有凹形的弧形形状，而邻接分隔塞的第一栅电极的端部具有凸形的弧形形状。
根据本发明的另一方面，在用于制造半导体器件的方法中，形成伪电极结构和层间介电层。伪电极结构包括：伪栅电极层和侧壁绝缘层，侧壁绝缘层设置在伪栅电极层的两个主侧处。层间介电层设置在伪电极层的两个主侧处。去除伪栅电极层的部分以在侧壁绝缘层之间形成第一间隔和第二间隔。第一电极间隔和第二电极间隔由柱分隔开，该柱是伪栅电极层的剩余部分。第一栅极结构和第二栅极结构分别形成在第一电极间隔和第二电极间隔中。去除柱使得在第一栅极结构和第二栅极结构之间形成开口。通过用绝缘材料填充开口来形成分隔塞。
根据本发明的另一方面，半导体器件包括FET，FET包括：第一栅极介电层和金属栅电极以及分隔塞，分隔塞由绝缘材料组成并且邻近FET设置。当从上面看时，分隔塞的端部形状具有凹形的弧形形状，而金属栅电极的邻接分隔塞的端部具有凸形的弧形形状。
根据本发明的一个实施例，提供了一种半导体器件，包括：第一FinFET，所述第一FinFET包括第一鳍结构、第一栅极电介质以及第一栅电极，所述第一鳍结构在第一方向上延伸，所述第一栅极电介质形成在所述第一鳍结构上方，所述第一栅电极形成在所述第一栅极电介质上方并且在垂直于所述第一方向的第二方向上延伸；第二FinFET，所述第二FinFET包括第二鳍结构、第二栅极电介质和第二栅电极，所述第二栅极电介质形成在所述第二鳍结构上方，以及所述第二栅电极形成在所述第一栅极电介质上方并且在所述第二方向上延伸；以及分隔塞，由绝缘材料制成并且设置在所述第一FinFET和所述第二FinFET之间，其中，当从上面看时，所述分隔塞的端部形状具有凹形的弧形形状，而所述第一栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
在上述半导体器件中，在沿着所述第二方向并且横跨所述第一栅电极的横截面中，所述分隔塞具有锥形形状，所述锥形形状具有小于底部宽度的顶部宽度。
在上述半导体器件中，还包括：隔离绝缘层，至少设置在所述第一鳍结构和所述第二鳍结构之间，其中：所述分隔塞设置在所述隔离绝缘层上方，以及测量的所述分隔塞的底部处与所述隔离绝缘层的表面所成的所述分隔塞的锥角为90度或更大。
在上述半导体器件中，所述第一栅电极包括第一金属栅极材料，以及所述第二栅电极包括第二金属栅极材料。
在上述半导体器件中，所述第一栅电极还包括设置在所述第一栅极介电层和所述第一金属栅极材料之间的第一功函数调整金属的一层或多层，以及所述第二栅电极还包括设置在所述第二栅极介电层和所述第二金属栅极材料之间的第二功函数调整金属的一层或多层。
在上述半导体器件中，所述第一FinFET和所述第二FinFET具有相同的沟道类型。
在上述半导体器件中，所述第一FinFET的沟道类型不同于所述第二FinFET的沟道类型。
在上述半导体器件中，在所述第一FinFET中包括两个以上的所述第一鳍结构。
根据本发明的另一实施例，还提供了一种用于制造半导器件的方法，包括：形成伪电极结构以及层间介电层，所述伪电极结构包括伪栅电极层和侧壁绝缘层，所述侧壁绝缘层设置在所述伪栅电极层的两个主侧处，以及所述层间介电层设置在所述伪电极层的两个主侧处；去除所述伪栅电极层的部分使得在所述侧壁绝缘层之间形成第一间隔和第二间隔，所述第一电极间隔和所述第二电极间隔通过柱分隔开，所述柱是所述伪栅电极层的剩余部分；在所述第一电极间隔和所述第二电极间隔中分别形成第一栅极结构和第二栅极结构；去除所述柱使得在所述第一栅极结构和所述第二栅极结构之间形成开口；以及通过利用绝缘材料填充所述开口来形成分隔塞。
在方法中，当从上面看时，所述分隔塞的端部具有凹形的弧形形状，而所述第一栅极结构的邻接所述分隔塞的端部具有凸形的弧形形状。
在方法中，在沿着所述第二方向和横跨所述第一栅电极层的横截面中，所述分隔塞具有锥形形状，所述锥形形状具有小于底部宽度的顶面宽度。
在方法中，还包括：至少在所述第一鳍结构和所述第二鳍结构之间形成隔离绝缘层，其中：所述分隔塞设置在所述隔离绝缘层上方，以及测量的所述分隔塞的底部处与所述隔离绝缘层的表面所成的所述分隔塞的锥角为90度或更大。
在方法中，去除所述伪栅电极层的部分包括：在对应于所述柱的区域上形成掩模图案；以及通过使用所述掩模图案蚀刻所述伪栅电极层。
在方法中，所述掩模图案是由氧化硅、氮氧化硅和氮化硅中的至少一种制成。
在方法中，还包括减小所述掩模图案的宽度，其中，通过使用具有所述减小的宽度的所述掩模图案对所述伪栅电极层实施蚀刻。
在方法中，形成所述分隔塞包括：在所述第一栅极结构和所述第二栅极结构上方以及在所述开口中形成所述绝缘材料；以及去除所述绝缘材料的部分，从而形成由填充在所述开口中的所述绝缘材料形成的所述分隔塞。
在方法中，形成所述伪电极结构包括：形成鳍结构；形成隔离层使得所述鳍结构的下部嵌入在所述隔离层中；在所述鳍结构上方形成第一介电层；以及在所述第一介电层上方形成所述伪电极层。
在方法中，所述伪栅电极层包括多晶硅。
在方法中，形成所述第一栅极结构和所述第二栅极结构包括：形成第二介电层；在所述第二介电层上方形成用于所述第一栅极结构的第一功函数调整金属的一层或多层；在所述第二介电层上方形成用于所述第二栅极结构的第二功函数调整金属的一层或多层；在所述第一功函数调整金属的一层或多层上方形成第一金属栅极材料；以及在所述第二功函数调整金属的一层或多层上方形成第二栅极材料。
根据本发明的又另一实施例，还提供了一种半导体器件，包括：FET，所述FET包括第一栅极介电层和金属栅电极；以及分隔塞，由绝缘材料制成并且相邻所述FET设置，其中，当从上面看时，所述分隔塞的端部具有凹形的弧形形状，而所述金属栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种半导体器件，包括：
第一鳍式场效应晶体管，所述第一鳍式场效应晶体管包括第一鳍结构、第一栅极电介质以及第一栅电极，所述第一鳍结构在第一方向上延伸，所述第一栅极电介质形成在所述第一鳍结构上方，所述第一栅电极形成在所述第一栅极电介质上方并且在垂直于所述第一方向的第二方向上延伸；
第二鳍式场效应晶体管，所述第二鳍式场效应晶体管包括第二鳍结构、第二栅极电介质和第二栅电极，所述第二栅极电介质形成在所述第二鳍结构上方，以及所述第二栅电极形成在所述第一栅极电介质上方并且在所述第二方向上延伸；以及
分隔塞，由绝缘材料制成并且设置在所述第一鳍式场效应晶体管和所述第二鳍式场效应晶体管之间，
其中，当从上面看时，所述分隔塞的端部形状具有凹形的弧形形状，而所述第一栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
2.根据权利要求1所述的半导体器件，其中，在沿着所述第二方向并且横跨所述第一栅电极的横截面中，所述分隔塞具有锥形形状，所述锥形形状具有小于底部宽度的顶部宽度。
3.根据权利要求2所述的半导体器件，还包括：隔离绝缘层，至少设置在所述第一鳍结构和所述第二鳍结构之间，其中：
所述分隔塞设置在所述隔离绝缘层上方，以及
测量的所述分隔塞的底部处与所述隔离绝缘层的表面所成的所述分隔塞的锥角为90度或更大。
4.根据权利要求1所述的半导体器件，其中：
所述第一栅电极包括第一金属栅极材料，以及
所述第二栅电极包括第二金属栅极材料。
5.根据权利要求4所述的半导体器件，其中：
所述第一栅电极还包括设置在所述第一栅极介电层和所述第一金属栅极材料之间的第一功函数调整金属的一层或多层，以及
所述第二栅电极还包括设置在所述第二栅极介电层和所述第二金属栅极材料之间的第二功函数调整金属的一层或多层。
6.根据权利要求1所述的半导体器件，其中，所述第一鳍式场效应晶体管和所述第二鳍式场效应晶体管具有相同的沟道类型。
7.根据权利要求1所述的半导体器件，其中，所述第一鳍式场效应晶体管的沟道类型不同于所述第二鳍式场效应晶体管的沟道类型。
8.根据权利要求1所述的半导体器件，其中，在所述第一鳍式场效应晶体管中包括两个以上的所述第一鳍结构。
9.一种用于制造半导器件的方法，包括：
形成伪电极结构以及层间介电层，所述伪电极结构包括伪栅电极层和侧壁绝缘层，所述侧壁绝缘层设置在所述伪栅电极层的两个主侧处，以及所述层间介电层设置在所述伪栅电极层的两个主侧处；
去除所述伪栅电极层的部分使得在所述侧壁绝缘层之间形成第一电极间隔和第二电极间隔，所述第一电极间隔和所述第二电极间隔通过柱分隔开，所述柱是所述伪栅电极层的剩余部分；
在所述第一电极间隔和所述第二电极间隔中分别形成第一栅极结构和第二栅极结构；
去除所述柱使得在所述第一栅极结构和所述第二栅极结构之间形成开口；以及
通过利用绝缘材料填充所述开口来形成分隔塞；
其中，当从上面看时，所述分隔塞的端部具有凹形的弧形形状，而所述第一栅极结构的邻接所述分隔塞的端部具有凸形的弧形形状。
10.根据权利要求9所述的方法，其中，在沿着第二方向和横跨所述第一栅电极层的横截面中，所述分隔塞具有锥形形状，所述锥形形状具有小于底部宽度的顶面宽度。
11.根据权利要求10所述的方法，还包括：至少在第一鳍结构和第二鳍结构之间形成隔离绝缘层，其中：
所述分隔塞设置在所述隔离绝缘层上方，以及
测量的所述分隔塞的底部处与所述隔离绝缘层的表面所成的所述分隔塞的锥角为90度或更大。
12.根据权利要求9所述的方法，其中，去除所述伪栅电极层的部分包括：
在对应于所述柱的区域上形成掩模图案；以及
通过使用所述掩模图案蚀刻所述伪栅电极层。
13.根据权利要求12所述的方法，其中，所述掩模图案是由氧化硅、氮氧化硅和氮化硅中的至少一种制成。
14.根据权利要求12所述的方法，还包括减小所述掩模图案的宽度，
其中，通过使用具有所述减小的宽度的所述掩模图案对所述伪栅电极层实施蚀刻。
15.根据权利要求9所述的方法，其中，形成所述分隔塞包括：
在所述第一栅极结构和所述第二栅极结构上方以及在所述开口中形成所述绝缘材料；以及
去除所述绝缘材料的部分，从而形成由填充在所述开口中的所述绝缘材料形成的所述分隔塞。
16.根据权利要求9所述的方法，其中，形成所述伪电极结构包括：
形成鳍结构；
形成隔离层使得所述鳍结构的下部嵌入在所述隔离层中；
在所述鳍结构上方形成第一介电层；以及
在所述第一介电层上方形成所述伪栅电极层。
17.根据权利要求9所述的方法，其中，所述伪栅电极层包括多晶硅。
18.根据权利要求16所述的方法，其中，形成所述第一栅极结构和所述第二栅极结构包括：
形成第二介电层；
在所述第二介电层上方形成用于所述第一栅极结构的第一功函数调整金属的一层或多层；
在所述第二介电层上方形成用于所述第二栅极结构的第二功函数调整金属的一层或多层；
在所述第一功函数调整金属的一层或多层上方形成第一金属栅极材料；以及
在所述第二功函数调整金属的一层或多层上方形成第二栅极材料。
19.一种半导体器件，包括：
场效应晶体管，所述场效应晶体管包括第一栅极介电层和金属栅电极；以及
分隔塞，由绝缘材料制成并且相邻所述场效应晶体管设置，
其中，当从上面看时，所述分隔塞的端部具有凹形的弧形形状，而所述金属栅电极的邻接所述分隔塞的端部具有凸形的弧形形状。
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