CN105845578A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN105845578A
CN105845578A CN201510464936.4A CN201510464936A CN105845578A CN 105845578 A CN105845578 A CN 105845578A CN 201510464936 A CN201510464936 A CN 201510464936A CN 105845578 A CN105845578 A CN 105845578A
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electrode
layer
connector
pseudo
separation connector
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CN105845578B (zh
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张哲诚
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括：第一和第二FinFET晶体管以及由绝缘材料制成并且设置在第一和第二FinFET晶体管之间的分离插塞。第一FinFET晶体管包括在第一方向上延伸的第一鳍结构、形成在第一鳍结构上方的第一栅极电介质和形成在第一栅极电介质上方并且在与第一方向垂直的第二方向上延伸的第一栅电极。第二FinFET晶体管包括第二鳍结构、形成在第二鳍结构上方的第二栅极电介质和形成在第二栅极电介质上方并且在第二方向上延伸的第二栅电极。在沿着第二方向并且横穿第一栅电极、第二栅电极和分离插塞的截面中，分离插塞具有顶部尺寸小于底部尺寸的锥形形状。本发明涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路，更具体地，涉及具有鳍结构的半导体器件及其制造工艺。
背景技术
随着半导体产业已步入到纳米技术工艺节点以追求更高的器件密度、更高的性能和较低的成本，来自制造和设计问题的挑战已导致诸如鳍式场效应晶体管(Fin FET)的三维设计的发展。Fin FET器件通常包括具有高纵横比的半导体鳍并且在其中形成半导体晶体管器件的沟道和源极/漏极区。利用沟道和源极/漏极区的增大的表面面积的优势沿着鳍结构的侧边并且在鳍结构的侧边上方(例如，包裹)形成栅极，以产生更快、更可靠和更好控制的半导体晶体管器件。通常在FinFET器件中一起使用金属栅极结构和具有高介电常数的高k栅极电介质，并且通过栅极替换技术制备金属栅极结构。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：第一FinFET晶体管，包括在第一方向上延伸的第一鳍结构、形成在所述第一鳍结构上方的第一栅极电介质和形成在所述第一栅极电介质上方并且在与所述第一方向垂直的第二方向上延伸的第一栅电极；第二FinFET晶体管，包括第二鳍结构、形成在所述第二鳍结构上方的第二栅极电介质和形成在所述第二栅极电介质上方并且在所述第二方向上延伸的第二栅电极；以及分离插塞，由绝缘材料制成并且设置在所述第一FinFET晶体管和所述第二FinFET晶体管之间，其中，在沿着所述第二方向并且横穿所述第一栅电极、所述第二栅电极和所述分离插塞的截面中，所述分离插塞的最大宽度位于高度Hb处，所述高度Hb小于所述分离插塞的高度Ha的3/4。
在上述半导体器件中，在所述截面中，所述分离插塞具有锥形形状，所述锥形形状的顶部宽度小于底部宽度。
在上述半导体器件中，所述分离插塞在所述分离插塞的底部处的锥角是90度以上。
在上述半导体器件中，所述第一栅电极包括一层或多层第一功函调整金属和第一金属栅极材料，以及所述第二栅电极包括一层或多层第二功函调整金属和第二金属栅极材料。
在上述半导体器件中，所述第一FinFET晶体管和所述第二FinFET晶体管具有相同的沟道类型。
在上述半导体器件中，所述第一FinFET晶体管的沟道类型与所述第二FinFET晶体管的沟道类型不同。
在上述半导体器件中，所述第一FinFET晶体管包括两个以上的所述第一鳍结构。
根据本发明的另一方面，还提供了一种用于制造半导体器件的方法，包括：形成伪电极结构，所述伪电极结构包括伪电极层和设置在所述伪电极层的两侧处的层间介电层；图案化所述伪电极层，从而将所述伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极；通过用绝缘材料填充所述开口形成分离插塞；去除所述第一伪电极和所述第二伪电极，从而形成第一电极空间和第二电极空间，并且所述分离插塞暴露在所述第一电极空间和所述第二电极空间之间；蚀刻暴露的所述分离插塞；以及分别在所述第一电极空间和所述第二电极空间中形成第一栅极结构和第二栅极结构，其中，在蚀刻暴露的所述分离插塞之后，在横穿所述第一电极空间、所述第二电极空间和所述分离插塞的截面中，所述分离插塞的最大宽度位于高度Hb处，所述高度Hb小于所述分离插塞的高度Ha的3/4。
在上述方法中，在蚀刻暴露的所述分离插塞之后，在所述截面中，所述分离插塞具有锥形形状，所述锥形形状的顶部宽度小于底部宽度。
在上述方法中，在蚀刻暴露的所述分离插塞之后，所述分离插塞在所述分离插塞的底部处的锥角是90度以上。
在上述方法中，形成所述分离插塞包括：在图案化的伪电极上方和在所述开口中形成所述绝缘材料；以及去除所述绝缘材料的一部分，从而形成填充在所述开口中的所述绝缘材料的所述分离插塞。
在上述方法中，在去除所述绝缘材料的一部分的步骤中使用化学机械抛光方法。
在上述方法中，形成所述伪电极结构包括：形成鳍结构；形成隔离层，从而使得所述鳍结构的下部嵌入在所述隔离层中；在所述鳍结构上方形成第一介电层；以及在所述第一介电层上方形成所述伪电极层。
在上述方法中，在蚀刻暴露的所述分离插塞的步骤中，去除所述第一介电层。
在上述方法中，形成所述第一栅极结构和所述第二栅极结构包括：形成第二介电层；在所述第二介电层上方形成用于所述第一栅极结构的一层或多层第一功函调整金属；在所述第二介电层上方形成用于所述第二栅极结构的一层或多层第二功函调整金属；在所述一层或多层第一功函调整金属上方形成第一金属栅极材料；以及在所述一层或多层第二功函调整金属上方形成第二金属栅极材料。
根据本发明的又一方面，还提供了一种用于制造半导体器件的方法，包括：形成伪电极结构，所述伪电极结构包括伪电极层和设置在所述伪电极层的两侧处的层间介电层；图案化所述伪电极层，从而将所述伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极；通过用绝缘材料填充所述开口形成分离插塞；去除所述第一伪电极和所述第二伪电极，从而形成第一电极空间和第二电极空间，并且所述分离插塞暴露在所述第一电极空间和所述第二电极空间之间；以及分别在所述第一电极空间和所述第二电极空间中形成第一栅极结构和第二栅极结构，其中，在形成所述分离插塞之前，所述开口的形状具有锥形形状，所述锥形形状的所述开口的顶部宽度小于所述开口的底部宽度。
在上述方法中，在所述开口中测量的所述开口在所述开口的底部处的锥角是90度以下。
在上述方法中，图案化所述伪电极层包括：在所述伪电极结构上方形成氧化硅层；图案化所述氧化硅层；以及通过将图案化的所述氧化硅层用作掩模来蚀刻所述伪电极层。
在上述方法中，形成所述分离插塞包括：在图案化的伪电极上方和在所述开口中形成所述绝缘材料；以及去除所述绝缘材料的一部分并且将图案化的所述氧化硅层用作掩模，从而形成填充在所述开口中的所述绝缘材料的所述分离插塞。
在上述方法中，在去除所述绝缘材料的一部分并且将图案化的所述氧化硅层用作掩模的步骤中，使用化学机械抛光方法。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明。应该注意，根据工业中的标准实践，各个部件未按比例绘制并且仅用于示出的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A是根据本发明的一个实施例的具有鳍结构的半导体FET器件(FinFET)的示例性截面图，图1B是具有鳍结构的半导体FET器件的示例性顶视图，以及图1C是对应于图1B中的封闭部分的具有鳍结构的半导体FET器件的示例性透视图；
图2至图12E示出了根据本发明的一个实施例的用于制造FinFET器件的示例性工艺；以及
图13至图18示出了根据本发明的另一个实施例的制造FinFET器件的示例性顺序工艺的截面图。
具体实施方式
应当理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限制于公开的范围或数值，但是可以取决于工艺条件和/或期望的器件性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚，可以以不同的尺寸任意地绘制各个部件。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。此外，术语“由…制成”意为“包括”或者“由…组成”。
图1A是具有鳍结构的半导体FET器件(FinFET)的示例性截面图，图1B是具有鳍结构的半导体FET器件的示例性顶视图，以及图1C是根据本发明的一个实施例的具有鳍结构的半导体FET器件的示例性透视图。图1A是沿着图1B中的线X-X截取的截面图，并且图1C对应于图1B中的封闭部分A。在这些图中，为了简化，省略了一些层/部件。图1A至图1C示出了在已经形成金属栅极结构之后的器件结构。
FinFET器件1包括第一器件区1A和第二器件区1B。第一器件区1A包括一个或多个第一FinFET器件，和第二器件区包括一个或多个第二FinFET器件。第一FinFET晶体管的沟道类型与第二FinFET晶体管的沟道类型相同或不同。
在一个实施例中，第一器件区1A包括p型MOSFET，并且第二器件区1B包括n型MOSFET。在其他实施例中，第一和第二器件区域包括p型MOSFET、第一和第二器件区域包括n型MOSFET或第一和第二器件区域均包括p型和n型MOSFET。
除其他部件之外，FinFET器件1包括衬底10、鳍结构20、栅极电介质30和栅电极40。在这个实施例中，衬底10是硅衬底。可选地，衬底10可以包括其他元素半导体，诸如锗；化合物半导体，包括诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体；或它们的组合。在一个实施例中，衬底10是SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时，鳍结构可以从SOI衬底的硅层突出或可以从SOI衬底的绝缘层突出。在后者的情况下，SOI衬底的硅层用于形成鳍结构。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料也可以用作衬底10。衬底10可以包括已适当地掺杂杂质(例如，p型或n型导电性)的各种区域。
鳍结构20设置在衬底10上方。鳍结构20可以由与衬底10相同的材料制成并且可以从衬底10连续地延伸。在这个实施例中，鳍结构由Si制成。鳍结构20的硅层可以是本征的或适当地掺杂有n型杂质或p型杂质。
在图1A中，分别在第一器件区1A和第二器件区1B中设置两个鳍结构20。然而，鳍结构的数量不限制于两个(或四个)。数量可以是一个、两个、三个或五个以上。此外，可以邻近鳍结构20的两侧设置多个伪鳍结构的一个以在图案化工艺中改进图案保真度。在一些实施例中，鳍结构20的宽度W1在约5nm到约40nm的范围内，并且在特定实施例中，鳍结构20的宽度W1可以在约7nm到约15nm的范围内。在一些实施例中，鳍结构20的高度在约100nm到约300nm的范围内，并且在其他实施例中，可以在约50nm到100nm的范围内。
位于栅电极40下方的鳍结构20的下部被称为阱层，和鳍结构20的上部被称为沟道层。在栅电极40下方，阱层嵌入在隔离绝缘层50中，和沟道层从隔离绝缘层50突出。沟道层的下部也可以嵌入在隔离绝缘层50中至约1nm到约5nm的深度。
在一些实施例中，阱层的高度在约60nm到100nm的范围内，并且沟道层的高度在约40nm到60nm的范围内。
进一步，鳍结构20之间的空间和/或一个鳍结构与形成在衬底10上方的另一元件之间的空间由包括绝缘材料的隔离绝缘层50(或所谓的“浅沟槽隔离(STI)”层)和设置在隔离绝缘层50上方的层间介电层70填充。用于隔离绝缘层50和层间介电层70的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)、或低k介电材料。隔离绝缘层50的绝缘材料可以与层间介电层70的绝缘材料相同或不同。
从隔离绝缘层50突出的鳍结构20的沟道层被栅极介电层30覆盖，并且栅极介电层30进一步被栅电极40覆盖。沟道层的未被栅电极40覆盖的部分用作MOSFET的源极和/或漏极(见图1B)。鳍结构20在第一方向上延伸并且栅电极40在与第一方向垂直的第二方向上延伸。
在特定实施例中，栅极介电层30包括介电材料，诸如氧化硅、氮化硅、高k介电材料或其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。
栅电极40包括任何适合的材料，诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合。在特定实施例中，栅电极包括金属栅极层45。
在本发明的特定实施例中，还可以在栅极介电层30和金属栅极层45之间设置一个或多个功函调整层。功函调整层可以包括单层或可选地多层结构，诸如具有选择的功函数以提高器件性能的金属层(功函金属层)、衬垫层、润湿层、粘合层、金属合金或金属硅化物的各种组合。功函调整层由诸如Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合适的金属材料的单层或两种以上的这些材料的多层的导电材料制成。在一些实施例中，功函调整层可以包括用于P沟道FinFET的第一金属材料(例如，在第一器件区1A中)和用于n沟道FinFET的第二金属材料(例如，在第二器件区1B中)。例如，用于n沟道FinFET的第一金属材料可以包括具有与衬底导带的功函数基本上对准或与鳍结构20的沟道层的导带的功函数至少基本上对准的功函数的金属。同样的，例如，用于p沟道FinFET的第二金属材料可以包括具有与衬底价带的功函数基本上对准或与鳍结构20的沟道层的价带的功函数至少基本上对准的功函数的金属。在一些实施例中，功函调整层可以可选地包括多晶硅层。功函调整层可以通过ALD、PVD、CVD、电子束蒸发、或其他合适的工艺形成。此外，可以单独地形成用于n沟道FinFET和p沟道FinFET的功函调整层，其可以使用不同的金属层。
通过在源极和漏极区中适当地掺杂杂质，还在未被栅电极40覆盖的鳍结构中形成源极和漏极区。可以在源极和漏极区25上形成Si或Ge的合金和诸如Co、Ni、W、Ti或Ta的金属。可以在源极-漏极区中外延地形成Si和/或SiGe层以形成突起的源极-漏极结构并且以对沟道层施加适当的应力。
此外，侧壁绝缘层80设置在栅电极40的两侧。栅电极40和源极/漏极区被层间介电层70覆盖，并且设置必要的布线和/或通孔/接触孔以完成半导体器件。
在一些实施例中，包括功函调整层42和金属栅极层45的栅电极40的宽度W2在约20nm到40nm的范围内。在一些实施例中，当多个栅电极40在宽度方向上布置时(见图1B)，栅电极的间距在约60nm到100nm的范围内。
如图1A至图1C所示，邻近的栅电极40通过分离插塞60彼此分离，分离插塞60由绝缘材料制成。在图1A所示的截面图中，分离插塞60具有锥形形状，该锥形形状具有较小的顶部尺寸(宽度)和较大的底部尺寸(宽度)。在特定实施例中，在分离插塞的顶部处的宽度W3小于约20nm，并且在一些实施例中可以在约5nm到约15nm范围内。在特定实施例中，在分离插塞的底部处的宽度W4小于约35nm，并且在一些实施例中可以在约10nm到约30nm范围内。在这里，分离插塞的顶部对应于栅电极40的上表面，并且分离插塞60的底部对应于栅极介电层30的底部或隔离绝缘层50和层间介电层70之间的界面。用于分离插塞70的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)、或低K介电材料，并且可以与用于隔离绝缘层50和/或层间介电层70的绝缘材料的材料相同或不同。
用于分离插塞70的绝缘材料可以与用于隔离绝缘层50和/或层间介电层70的绝缘材料相同或不同。
图2至图12E示出了根据本发明的一个实施例的制造FinFET器件的示例性顺序工艺的截面图。应当理解，可以在图2至图12E示出的工艺之前、期间和之后提供额外的操作，并且对于该方法的额外实施例，下文描述的一些操作可以被替换或消除。操作/工艺的顺序可以互换。此外，在美国专利公开号为2013/0161762中已经公开了用于在鳍结构上方通过栅极替代技术制造金属栅极结构的一般操作，其全部内容通过引用结合于此作为参考。
为了制造鳍结构，例如，通过热氧化工艺和/或化学汽相沉积(CVD)工艺在衬底10上方形成掩模层。例如，衬底10是具有在约1.12×1015cm-3和约1.68×1015cm-3范围内的杂质浓度的p型硅衬底。在其他实施例中，衬底10是具有在约0.905×1015cm-3和约2.34×1015cm-3范围内的杂质浓度的n型硅衬底。例如，在一些实施例中，掩模层包括衬垫氧化物(例如，氧化硅)层和氮化硅掩模层。
可以通过使用热氧化或CVD工艺形成衬垫氧化物层。可以通过物理汽相沉积(PVD)(诸如溅射方法)、CVD、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)，和/或其他工艺形成氮化硅掩模层。
在一些实施例中，衬垫氧化物层的厚度在约2nm至约15nm的范围内，并且氮化硅掩模层的厚度在约2nm至约50nm的范围内。在掩模层上方进一步形成掩模图案。例如，掩模图案是通过光刻形成的光刻胶图案。
通过将掩模图案用作蚀刻掩模，形成衬垫氧化物层106和氮化硅掩模层107的硬掩模图案100。在一些实施例中，硬掩模图案的宽度在约5nm至约40nm的范围内。在特定实施例中，硬掩模图案的宽度在约7nm至约12nm的范围内。
如图2所示，通过将掩模图案用作蚀刻掩模，通过使用干蚀刻方法或湿蚀刻方法的沟槽蚀刻将衬底10图案化成鳍结构20。鳍结构20的高度在约100nm到约300nm的范围内。在特定实施例中，鳍结构20的高度在约50nm到约100nm的范围内。当鳍结构的高度不均匀时，可以从对应于鳍结构的平均高度的平面测量从衬底的高度。
在这个实施例中，块状硅晶圆用作起始材料并且组成衬底10。然而，在一些实施例中，其他类型的衬底可用作衬底10。例如，绝缘体上硅(SOI)晶圆可用作起始材料，并且SOI晶圆的绝缘层构成衬底10，并且SOI晶圆的硅层用于鳍结构20。
如图3所示，在衬底10上方形成隔离绝缘层50以完全覆盖鳍结构20。
例如，隔离绝缘层50由通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的二氧化硅制成。在可流动CVD中，沉积可流动介电材料，而不是氧化硅。正如它们的名字所表明的，可流动介电材料在沉积期间可以“流动”以填充具有高纵横比的间隙或空间。通常，将各种化学物质加入到含硅前体以允许沉积的膜流动。在一些实施例中，添加氮氢键合物。可流动介电前体的实例，特别地可流动氧化硅前体的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺，诸如三甲硅烷基胺(TSA)。在多操作工艺中形成这些可流动氧化硅材料。在沉积可流动膜之后，对可流动膜进行固化和然后退火以去除非期望的元素以形成氧化硅。当去除非期望的元素后，可流动膜变得致密和收缩。在一些实施例中，进行多个退火工艺。在诸如约1000℃至约1200℃的范围内的温度下对可流动膜固化和退火不止一次，并且共持续诸如30小时以上的时间段。可以通过使用SOG形成隔离绝缘层50。在一些实施例中，SiO、SiON、SiOCN或氟掺杂的硅酸盐玻璃(FSG)可用作隔离绝缘层50。
在形成隔离绝缘层50之后，实施平坦化操作以去除隔离绝缘层50的部分和去除包括衬垫氧化物层106和氮化硅掩模层107的掩模层100。然后，进一步去除隔离绝缘层50，从而如图4所示，暴露出鳍结构20的将变成沟道层的上部。
在形成隔离绝缘层50之后，可以实施热工艺(例如，退火工艺)以改进隔离绝缘层50的质量。在特定实施例中，通过使用快速热退火(RTA)来实施热工艺，快速热退火(RTA)的实施条件为：在惰性气体环境中(例如，N2、Ar或He环境中)，在约900℃至约1050℃的范围内的温度下并且持续时间为1.5秒至约10秒。
在隔离绝缘层50和暴露的鳍结构20上方形成栅极氧化物层105和多晶硅层，和然后实施图案化操作以获得由多晶硅制成的多晶硅栅极层110。栅极氧化物层105可以是通过CVD、PVD、ALD、电子束蒸发或其他合适的工艺形成的氧化硅。在一些实施例中，多晶硅层的厚度在约5nm至约100nm的范围内。
侧壁绝缘层80也形成在多晶硅栅极层110的两侧。
此外，层间介电层70形成在多晶硅栅极层110、侧壁绝缘层80之间的空间中以及多晶硅栅极层110上方。实施诸如回蚀刻工艺和/或化学机械抛光(CMP)工艺的平坦化操作，以获得在图5A至图5C中示出的结构。图5A是在形成多晶硅栅极层110和层间介电层70之后的FinFET器件的截面图，图5B是在形成多晶硅栅极层110和层间介电层70之后的FinFET器件的顶视图，以及图5C是在形成多晶硅栅极层110和层间介电层70之后的FinFET器件的透视图。图5A是沿着图5B中的线X-X截取的截面图，以及图5C对应于图5B中的封闭部分B。
如图5B和图5C所示，在特定实施例中，以恒定间距在一方向上延伸的线和空间布置形成多晶硅栅极层110。多晶硅栅极层110可以包括在垂直于上述一方向的另一方向上延伸的另一线和空间布置。
如图6所示，掩模图案120形成在图5C中所示的结构上方。例如，通过具有狭缝125的光刻胶层形成掩模图案120。在一些实施例中，狭缝125的宽度在约5nm到约100nm的范围内。
如图7所示，通过使用掩模图案120，蚀刻多晶硅栅极层的一部分。在图7中和此后，省略层间介电层70的一层70A以示出蚀刻的多晶硅栅极层110，而仍然示出其他层70B和70C。在一些实施例中，通过等离子体蚀刻实施多晶硅栅极层的蚀刻，等离子体蚀刻使用包括处于3毫托至20毫托的压力下的CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2和/或He的气体。
通过灰化工艺和/或湿清洗工艺去除掩模图案120(光刻胶图案)。
图8示出了在形成使多晶硅栅极层110分隔开的开口130之后的产生的结构。在图8中，开口130的顶部形状是圆形的。然而，取决于结构的尺寸、掩模图案120的图案化条件和/或多晶硅栅极层110的蚀刻条件，该形状可以是矩形、具有圆角的矩形或椭圆形。
也应当指出的是，开口130的截面图具有锥形形状，该锥形形状具有较大的顶部尺寸和较小的底部尺寸。
例如，通过使用CVD工艺在图8中所示的结构上方形成绝缘材料，并且用绝缘材料填充开口130。CVD工艺可以包括LPCVD工艺、等离子体CVD工艺和/或可流动CVD工艺。在一些实施例中，在可流动CVD工艺中，可以使用包括SiH4、NH3、N2、O2、N2O、Cl2和/或NO2的气体并且在约200℃至约1000℃的范围内的温度下实施沉积。
在多晶硅栅极层上方形成绝缘材料的非必须部分之后，通过平坦化操作去除侧壁绝缘层和层间介电层，获得如图9中所示的分离插塞60。平坦化操作可以包括CMP和/或回蚀刻工艺。
在形成分离插塞60后，通过干蚀刻和/或湿蚀刻去除多晶硅栅极层110。如图10所示，通过去除多晶硅栅极层110，暴露出分离插塞60。由于鳍结构20的上部被栅极氧化物105覆盖，鳍结构20在多晶硅栅极蚀刻工艺中未被蚀刻。
在这里，由于开口130的截面图具有锥形形状，该锥形形状具有较大的顶部尺寸和较小的底部尺寸，暴露的分离插塞60具有倒锥形形状，该倒锥形形状具有较大的顶部尺寸和较小的底部尺寸。
如图11所示，对暴露的分离插塞60实施额外的蚀刻工艺以使得分离插塞的截面具有较小的顶部尺寸和较大的底部尺寸的锥形形状。在一些实施例中，通过等离子体蚀刻实施分离插塞的额外的蚀刻，等离子体蚀刻使用包括处于3毫托至20毫托的压力下的CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2和/或He的气体。分离插塞的等离子体蚀刻可以包括各向异性蚀刻以及之后的各向同性蚀刻。
图12A至图12E示出了额外的蚀刻操作的具体细节和变化。在去除多晶硅栅极层110之后，暴露出倒锥形的分离插塞60。在分离插塞60的底部处的锥角θ为在约80度至约87度的范围内的锐角(小于90度)。
如图12B所示，通过实施额外的蚀刻操作，减小了分离插塞的上部的宽度，并且获得锥形形状的分离插塞60。在分离插塞60的底部处的锥角θ为90度或90度以上。在一些实施例中，锥角θ在约93度至约100度的范围内。
如图12C至图12D所示，在一些实施例中，取决于额外的蚀刻操作的条件，分离插塞60在截面中的形状可以具有圆形、六边形或圆桶形。在图12C至图12D中，截面中的最大宽度位于高度Hb处，高度Hb小于分离插塞的高度Ha的3/4。在一些实施例中，Hb小于Ha的1/2。
在分离插塞60的形状的这些变化中，由于暴露的分离插塞的顶部的宽度减小，开口区域OA变得更宽。更宽的开口OA使得用于金属栅极结构的金属材料更共形地填充由去除多晶硅栅极层110形成的空间成为可能。
在图11的操作之后，在分离插塞之间的空间中形成金属栅极结构，分离插塞之间的空间是通过去除多晶硅栅极层110创建的，从而获得图1A至图1C中示出的结构。
图13至图18示出了根据本发明的另一个实施例的制造FinFET器件的示例性顺序工艺的截面图。应当理解，可以在图13至图18示出的工艺之前、期间和之后提供额外的操作，并且对于该方法的额外实施例，下文描述的一些操作可以被替换或消除。操作/工艺的顺序可以互换。
在形成图5A至图5C中示出的结构之后，在多晶硅栅极层110、侧壁绝缘层80和层间绝缘层70上方形成掩模层200。掩模层是针对多晶硅具有高蚀刻选择性的材料。在特定例子中，掩模层200是具有在约10nm至约300nm的范围内的厚度的氧化硅。如图13所示，在掩模层200上，形成具有开口的光刻胶图案210。
如图14所示，通过将光刻胶图案210用作掩模，图案化掩模层200。
如图15所示，通过将图案化的掩模层200用作蚀刻掩模，图案化多晶硅栅极层110，从而使得开口135具有倒锥形形状。在一些实施例中，在开口中测量的处于开口135的底部处的锥角θ’为90度以下，并且可以在约80度至约87度的范围内。
为了形成开口135，可以使用等离子体蚀刻。在一些实施例中，可以将处于约10Pa至约100Pa的压力下的氟碳化合物气体、氯碳化合物气体、含氯氟烃气体或它们的混合物用作蚀刻气体。
如图16所示，例如，通过使用CVD工艺在图15中所示的结构上方形成绝缘材料，并且用绝缘材料填充开口135。
如图17所示，通过包括CMP和/或回蚀刻工艺的平坦化操作去除绝缘材料的一部分和掩模层200，从而获得具有锥形形状的分离插塞60。
在形成分离插塞60之后，通过干蚀刻和/或湿蚀刻去除多晶硅栅极层110。如图18所示，通过去除多晶硅栅极层110，暴露出分离插塞60。
在图18中，在分离插塞60的底部处的锥角θ为90度以上。在一些实施例中，锥角θ在约93度至约100度的范围内。
在图18中的操作之后，金属栅极结构形成在分离插塞之间的空间中，分离插塞之间的空间是通过去除多晶硅栅极层110创建的，从而获得图1A至图1C所示的结构。
本文中描述的各个实施例或实例提供了优于现有技术的若干优势。例如，由于分离插塞的顶部的宽度被减小为具有小于底部宽度的顶部宽度，在去除多晶硅栅极层之后的开口区域变得更宽，和更具体地，顶部宽度变得更宽。该更宽的开口使得用于金属栅极结构的金属材料更共形地填充由去除多晶硅栅极层形成的空间成为可能。
此外，由于蚀刻分离插塞，整个分离插塞的宽度变得更小。因此，两个相邻的鳍结构之间的距离(图1所示的鳍结构20A和20B)变得更小。
应当理解的是，不是所有的优势必须在本文中论述，没有特定的优势是所有的实施例或实例所需的，和其他实施例或实例可以提供不同的优势。
根据本发明的一个方面，一种半导体器件包括：第一FinFET晶体管、第二FinFET晶体管以及设置在第一FinFET晶体管和第二FinFET晶体管之间的分离插塞。第一FinFET晶体管包括在第一方向上延伸的第一鳍结构、形成在第一鳍结构上方的第一栅极电介质和形成在第一栅极电介质上方并且在与第一方向垂直的第二方向上延伸的第一栅电极。第二FinFET晶体管包括第二鳍结构、形成在第二鳍结构上方的第二栅极电介质和形成在第二栅极电介质上方并且在第二方向上延伸的第二栅电极。分离插塞由绝缘材料制成。在沿着第二方向并且横穿第一栅电极、第二栅电极和分离插塞的截面中，分离插塞的最大宽度位于高度Hb处，高度Hb小于分离插塞的高度Ha的3/4。
根据本发明的另一方面，一种用于制造半导体器件的方法包括：形成包括伪电极层和设置在伪电极层的两侧处的层间介电层的伪电极结构。图案化伪电极层，从而将伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极。通过用绝缘材料填充开口形成分离插塞。去除第一伪电极和第二伪电极，从而形成第一电极空间和第二电极空间，并且分离插塞暴露在第一电极空间和第二电极空间之间。蚀刻暴露的分离插塞，从而在横穿第一电极空间、第二电极空间和分离插塞的截面中，分离插塞的最大宽度位于高度Hb处，高度Hb小于分离插塞的高度Ha的3/4。第一栅极结构和第二栅极结构分别形成在第一电极空间和第二电极空间中。
根据本发明的另一方面，一种用于制造半导体器件的方法包括：形成包括伪电极层和设置在伪电极层的两侧处的层间介电层的伪电极结构。图案化伪电极层，从而将伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极。通过用绝缘材料填充开口形成分离插塞。去除第一伪电极和第二伪电极，从而形成第一电极空间和第二电极空间，并且分离插塞暴露在第一电极空间和第二电极空间之间。分别在第一电极空间和第二电极空间中形成第一栅极结构和第二栅极结构。在形成分离插塞之前的开口的形状具有锥形形状，该锥形形状具有小于开口的底部尺寸(宽度)的开口的顶部尺寸(宽度)。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一FinFET晶体管，包括在第一方向上延伸的第一鳍结构、形成在所述第一鳍结构上方的第一栅极电介质和形成在所述第一栅极电介质上方并且在与所述第一方向垂直的第二方向上延伸的第一栅电极；
第二FinFET晶体管，包括第二鳍结构、形成在所述第二鳍结构上方的第二栅极电介质和形成在所述第二栅极电介质上方并且在所述第二方向上延伸的第二栅电极；以及
分离插塞，由绝缘材料制成并且设置在所述第一FinFET晶体管和所述第二FinFET晶体管之间，
其中，在沿着所述第二方向并且横穿所述第一栅电极、所述第二栅电极和所述分离插塞的截面中，所述分离插塞的最大宽度位于高度Hb处，所述高度Hb小于所述分离插塞的高度Ha的3/4。
2.根据权利要求1所述的半导体器件，其中，在所述截面中，所述分离插塞具有锥形形状，所述锥形形状的顶部宽度小于底部宽度。
3.根据权利要求2所述的半导体器件，其中，所述分离插塞在所述分离插塞的底部处的锥角是90度以上。
4.根据权利要求1所述的半导体器件，其中：
所述第一栅电极包括一层或多层第一功函调整金属和第一金属栅极材料，以及
所述第二栅电极包括一层或多层第二功函调整金属和第二金属栅极材料。
5.根据权利要求1所述的半导体器件，其中，所述第一FinFET晶体管和所述第二FinFET晶体管具有相同的沟道类型。
6.根据权利要求1所述的半导体器件，其中，所述第一FinFET晶体管的沟道类型与所述第二FinFET晶体管的沟道类型不同。
7.根据权利要求1所述的半导体器件，其中，所述第一FinFET晶体管包括两个以上的所述第一鳍结构。
8.一种用于制造半导体器件的方法，包括：
形成伪电极结构，所述伪电极结构包括伪电极层和设置在所述伪电极层的两侧处的层间介电层；
图案化所述伪电极层，从而将所述伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极；
通过用绝缘材料填充所述开口形成分离插塞；
去除所述第一伪电极和所述第二伪电极，从而形成第一电极空间和第二电极空间，并且所述分离插塞暴露在所述第一电极空间和所述第二电极空间之间；
蚀刻暴露的所述分离插塞；以及
分别在所述第一电极空间和所述第二电极空间中形成第一栅极结构和第二栅极结构，
其中，在蚀刻暴露的所述分离插塞之后，在横穿所述第一电极空间、所述第二电极空间和所述分离插塞的截面中，所述分离插塞的最大宽度位于高度Hb处，所述高度Hb小于所述分离插塞的高度Ha的3/4。
9.根据权利要求8所述的方法，其中，在蚀刻暴露的所述分离插塞之后，在所述截面中，所述分离插塞具有锥形形状，所述锥形形状的顶部宽度小于底部宽度。
10.一种用于制造半导体器件的方法，包括：
形成伪电极结构，所述伪电极结构包括伪电极层和设置在所述伪电极层的两侧处的层间介电层；
图案化所述伪电极层，从而将所述伪电极层分成通过开口分隔开的至少第一伪电极和第二伪电极；
通过用绝缘材料填充所述开口形成分离插塞；
去除所述第一伪电极和所述第二伪电极，从而形成第一电极空间和第二电极空间，并且所述分离插塞暴露在所述第一电极空间和所述第二电极空间之间；以及
分别在所述第一电极空间和所述第二电极空间中形成第一栅极结构和第二栅极结构，
其中，在形成所述分离插塞之前，所述开口的形状具有锥形形状，所述锥形形状的所述开口的顶部宽度小于所述开口的底部宽度。
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