CN108573927B - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- CN108573927B CN108573927B CN201710131234.3A CN201710131234A CN108573927B CN 108573927 B CN108573927 B CN 108573927B CN 201710131234 A CN201710131234 A CN 201710131234A CN 108573927 B CN108573927 B CN 108573927B
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
一种半导体结构及其形成方法,其中方法包括:提供基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;形成从第一区延伸到第二区的伪栅结构,所述伪栅结构贯穿所述第三区;分别在所述第一区伪栅结构两侧的基底内形成第一源漏掺杂区;分别在所述第二区伪栅结构两侧的基底内形成第二源漏掺杂区;形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口,所述介质开口暴露出所述第三区的基底;在所述介质开口内形成层间介质层,所述层间介质层的顶部表面与伪栅结构的顶部表面齐平。所述方法能够降低在介质开口内形成层间介质层的难度。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体器件集成度的提高,静态随机存储器(Static Random AccessMemory,SRAM)的关键尺寸不断减小。
现有技术中的SRAM单元通常为6T结构。一种常见6T结构的SRAM单元通常包括存储单元和两个读写单元。其中存储单元包括两个上拉晶体管和两个下拉晶体管,两个上拉晶体管与字线相连,两个下拉晶体管与地线相连,存储单元有两个存储节点和两个打开节点,用于存储1或0信号;两个读写单元为两个传输晶体管,每个传输晶体管一端与存储单元的一个存储节点和一个打开节点相连,另一端与位线相连,用于对存储单元进行读写操作。
然而,静态随机存储器的关键尺寸减小,使得静态随机存储器的制造难度较大。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法,能够改善半导体结构性能。
为解决上述技术问题,本发明实施例提供一种半导体结构的形成方法,包括:提供基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;形成从第一区延伸到第二区的伪栅结构,所述伪栅结构贯穿所述第三区;分别在所述第一区伪栅结构两侧的基底内形成第一源漏掺杂区;分别在所述第二区伪栅结构两侧的基底内形成第二源漏掺杂区;形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口,所述介质开口暴露出所述第三区的基底;在所述介质开口内形成层间介质层,所述层间介质层的顶部表面与伪栅结构的顶部表面齐平。
可选的,形成所述第一源漏掺杂区之前,还包括:在所述第二区基、第三区基底底、第三区伪栅结构和第二区伪栅结构上形成第一保护层;所述第一保护层的厚度为:6纳米~10纳米。
可选的,所述第一保护层的形成步骤包括:在所述第一区、第二区和第三区的基底以及伪栅结构上形成第一保护膜;去除位于所述第一区基底以及第一区伪栅结构上的第一保护膜,形成第一保护层。
可选的,所述第一源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第一区伪栅结构两侧的基底内形成第一开口;采用选择性外延沉积工艺在所述第一开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第一源漏掺杂区。
可选的,形成所述第二源漏掺杂区之前,还包括:在所述第一区基底、第三区基底、第一区伪栅结构和第三区伪栅结构上形成第二保护层;所述第二保护层的厚度为:6纳米~10纳米。
可选的,所述第二保护层的形成步骤包括:在所述第一区、第二区和第三区的基底以及伪栅结构上形成第二保护膜;去除位于所述第二区基底以及第二区伪栅结构上的第二保护膜,形成第二保护层。
可选的,所述第二源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第二区伪栅结构两侧的基底内形成第二开口;采用选择性外延沉积工艺在所述第二开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第二源漏掺杂区。
可选的,所述介质开口沿伪栅结构延伸方向上的尺寸为:20纳米~40纳米。
可选的,形成所述层间介质层之后,还包括:去除伪栅结构形成伪栅开口。
可选的,所述伪栅结构包括:伪栅极层;去除所述伪栅结构的步骤包括:去除伪栅极层。
可选的,所述伪栅结构还包括:伪栅介质层;所述伪栅极层位于所述伪栅介质层上;去除所述伪栅结构的步骤还包括:去除伪栅极层之后,去除伪栅介质层。
可选的,在形成层间介质层之前,还包括:在所述介质开口的侧壁形成第一侧墙。
可选的,所述第一侧墙的材料包括:氮化硅;所述第一侧墙的厚度为:2纳米~3纳米。
可选的,形成所述第一侧墙之前,还包括:在所述介质开口侧壁上形成第二侧墙。
可选的,所述第二侧墙的材料包括:氧化硅;所述第二侧墙的厚度包括:10埃~50埃。
可选的,所述伪栅结构包括:伪栅介质层以及位于伪栅介质层上的伪栅极层;形成所述层间介质层之后,还包括:去除伪栅极层和伪栅介质层形成伪栅开口,且在去除伪栅介质层时去除所述第二侧墙。
可选的,所述第一区用于形成上拉晶体管,所述第二区用于形成输出晶体管,所述第三区用于形成位于所述上拉晶体管的栅极结构与输出晶体管的栅极结构之间的层间介质层。
可选的,所述上拉晶体管栅极结构的形成步骤包括:去除第一区伪栅结构形成第一伪栅开口;在所述第一伪栅开口内形成第一栅极材料层;平坦化所述第一栅极材料层,直至暴露出层间介质层表面;所述输出晶体管栅极结构的形成步骤包括:去除第二区伪栅结构形成第二伪栅开口;在所述第二伪栅开口内形成第二栅极材料层;平坦化所述第二栅极材料层,直至暴露出层间介质层表面。
可选的,所述基底包括:衬底以及位于所述衬底上的鳍部,所述鳍部之间的衬底上具有隔离结构,所述隔离结构的顶部表面低于所述鳍部的顶部表面,且覆盖所述鳍部的部分侧壁,横跨所述鳍部的伪栅结构,所述伪栅结构覆盖所述鳍部的部分侧壁和顶部表面;所述介质开口暴露出第三区隔离结构的顶部表面。
相应的,本发明还提供一种采用上述方法形成的一种半导体结构,包括:基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;从第一区延伸到第二区的伪栅结构,所述伪栅结构贯穿所述第三区,位于所述第一区伪栅结构两侧基底内的第一源漏掺杂区,位于所述第二区伪栅结构两侧基底内的第二源漏掺杂区;贯穿所述伪栅结构的层间介质层,所述层间介质层暴露出所述第三区基底,所述层间介质层的顶部表面与伪栅开口的顶部表面齐平。
与现有技术相比,本发明实施例的技术方案具有以下有益效果:
本发明技术方案提供的半导体结构的形成方法中,形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口。即,在形成所述第一源漏掺杂区和第二源漏掺杂区的过程中,所述介质开口并未形成,因此,在形成第一源漏掺杂区和第二源漏掺杂区时,不影响后续形成的介质开口沿伪栅结构延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内易于形成质量良好的层间介质层的前提下,由于所述介质开口沿伪栅结构延伸方向上的尺寸并未受到第一源漏掺杂区和第二源漏掺杂区的制造工艺的影响,使介质开口无需过度做大。当所述介质开口和伪栅结构总制造空间一定的情况下,所述介质开口沿伪栅结构延伸方向的尺寸较小时,使得用于形成伪栅结构的制造空间较大。而在后栅工艺中,通常去除所述伪栅结构形成伪栅开口,后续在伪栅开口内形成栅极结构。由于伪栅结构的空间尺寸较大,使得去除伪栅结构形成的伪栅开口的空间尺寸较大,因此,在所述伪栅开口内形成栅极结构较容易,且形成的栅极结构性能良好。
进一步,形成所述第一源漏掺杂层之前,在所述第二区基底、第三区基底以及第三区伪栅结构和第二区伪栅结构上形成第一保护层,所述第一保护层在形成介质开口之前形成。即,在形成所述第一保护层的过程中,介质开口并未形成,因此,所述第一保护层不影响后续形成的介质开口沿伪栅结构延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内能够形成层间介质层的前提下,由于所述介质开口的侧壁和底部并无第一保护层的覆盖,因此,能够有效地避免介质开口过度做大。
进一步,形成所述第二源漏掺杂区之前,在所述第一区基底、第三区基底以及第一区伪栅结构和第三区伪栅结构上形成第二保护层,所述第二保护层在形成介质开口之前形成。即,在形成所述第二保护层的过程中,介质开口并未形成,因此,所述第二保护层不影响后续形成的介质开口沿伪栅结构延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内能够形成层间介质层的前提下,由于所述介质开口的侧壁和底部无第二保护层的覆盖,因此,能够有效地避免介质开口过度做大。
进一步,对于静态随机存储器来说,当上拉晶体管、输出晶体管与位于所述上拉晶体管的栅极结构与输出晶体管的栅极结构之间的层间介质层的总制造空间一定的情况下,用于形成层间介质层的介质开口不能过大,否则会使用于形成上拉晶体管和输出晶体管的空间过小。后续去除第一区伪栅结构形成第一伪栅开口,所述第一伪栅开口用于形成上拉晶体管的栅极结构。所述第一伪栅开口沿伪栅结构延伸方向的尺寸较大,使得后续在所述第一伪栅开口内形成上拉晶体管的栅极结构较容易,且形成的所述上拉晶体管的栅极结构性能良好。后续去除第二区伪栅结构形成第二伪栅开口,所述第二伪栅开口用于形成输出晶体管的栅极结构。所述第二伪栅开口沿伪栅结构延伸方向的尺寸较大,使得后续在所述第二伪栅开口内形成输出晶体管的栅极结构较容易,且形成的所述输出晶体管的栅极结构性能良好,从而提高静态随机存储器的性能。
本发明技术方案提供的半导体结构中,所述第一区伪栅结构用于形成上拉晶体管的栅极结构,所述第二区伪栅结构用于形成输出晶体管的栅极结构,位于所述第三区的层间介质层用于隔离所述上拉晶体管的栅极结构与所述输出晶体管的栅极结构的隔离性能较好,因此,静态随机存储器的性能较好。
附图说明
图1至图2是一种半导体结构的形成方法各步骤的结构示意图;
图3至图13是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
正如背景技术所述,现有技术中静态随机存储器的制造难度较大。
图1至图2是一种半导体结构的形成方法各步骤的结构示意图。
请参考图1,提供基底,所述基底包括:第一区A、第二区B和第三区C,所述第三区C位于所述第一区A和第二区B之间;在所述第一区A的基底上形成第一伪栅结构100,在所述第二区B的基底上形成第二伪栅结构101;在所述第三区C的基底上形成介质开口102,所述介质开口102暴露出第三区C的基底。
所述第一区A用于形成上拉晶体管,所述第二区B用于形成输出晶体管,所述第三区C用于形成位于所述上拉晶体管的栅极结构与所述输出晶体管的栅极结构之间的层间介质层。
请参考图2,形成所述介质开口102之后,在所述第一伪栅结构100两侧的基底内形成第一源漏掺杂区;在所述第二伪栅结构101两侧的基底内形成第二源漏掺杂区。
形成所述第一源漏掺杂区之前,还包括:在所述介质开口102内以及第二伪栅结构101上形成第一保护层103。所述第一保护层103的形成步骤包括:在所述基底、第一伪栅结构100、第二伪栅结构101上以及介质开口102内形成第一保护膜;去除位于所述第一区A基底、第一伪栅结构100上的第一保护膜,形成第一保护层103。
所述第一源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第一伪栅结构100两侧的基底内形成第一开口;采用选择性外延沉积工艺在所述第一开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第一源漏掺杂区。
形成所述第二源漏掺杂区之前,还包括:在所述第一伪栅结构100、介质开口102内形成第二保护层104。所述第二保护层104的形成步骤包括:在所述基底、第一伪栅结构100上、第一保护层103上形成第二保护膜;去除位于所述第二区B基底以及第二区伪栅结构101上的第一保护膜和第二保护膜,形成第二保护层104。
所述第二源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第二伪栅结构101两侧的基底内形成第二开口;采用选择性外延沉积工艺在所述第二开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第二源漏掺杂区。
后续的步骤还包括:在所述介质开口102内形成层间介质层。
然而,采用上述方法制备的半导体性能较差,原因在于:
上述方法中,所述介质开口102在形成所述第一源漏掺杂区和第二源漏掺杂区之前形成。而在形成所述介质开口102之后,形成所述第一源漏掺杂区之前,在所述第二区B基底、第三区C基底、介质开口102内以及第二伪栅结构101上形成第一保护层103。在形成所述第一源漏掺杂层区的过程中,采用刻蚀工艺在所述第一伪栅结构100两侧的基底内形成第一开口。在形成所述第一开口的过程中,所述第一保护层103用于保护所述第二区B基底、第三区C基底、介质开口102和第二伪栅结构101,因此,所述第一保护层103的厚度不能太薄,否则,所述第一保护层103对所述第二区B基底、第三区C基底、介质开口102以及第二伪栅结构101的保护力度不够。覆盖在所述介质开口102内的所述第一保护层103使得所述介质开口102沿第一伪栅结构100延伸方向上的尺寸减小,进而使得后续在所述介质开口102内形成层间介质层变得困难。
形成所述第一源漏掺杂区之后,形成所述第二源漏掺杂区。在形成所述第二源漏掺杂区之前,在所述第一区A基底、第三区C基底、介质开口102内以及第一伪栅结构100上形成第二保护层104。在形成所述第二源漏掺杂区的过程中,采用刻蚀工艺在所述第二伪栅结构101两侧的基底内形成第二开口。在形成所述第二开口的过程中,所述第二保护层104用于保护所述第一区A基底、第三区C基底、介质开口102和第一伪栅结构100,因此,所述第一保护层104的厚度不能太薄,否则,所述第二保护层104对所述第一区A基底、第三区C基底、介质开口102以及第一伪栅结构100的保护力度不够。覆盖在所述介质开口102内第一保护层103上的所述第二保护层104使得所述介质开口102沿第一伪栅结构100延伸方向上的尺寸进一步减小,使得后续在所述介质开口102内形成层间介质层变得更加困难。
为了减小在所述介质开口102内形成层间介质层的难度,一种方法是扩大所述介质开口102沿第一伪栅结构100延伸方向上的尺寸。然而,对于静态随机存储器来说,当上拉晶体管、输出晶体管以及位于所述上拉晶体管的栅极结构与输出晶体管的栅极结构之间的层间介质层的总制造空间一定的情况下,用于形成层间介质层的介质开口102沿第一伪栅结构100延伸方向上的尺寸过大,使得用于形成上拉晶体管的栅极结构和输出晶体管的栅极结构的空间过小。
后续去除第一伪栅结构100形成第一伪栅开口,所述第一伪栅开口用于形成上拉晶体管的栅极结构。所述第一伪栅开口沿所述第一伪栅结构100延伸方向上的尺寸过小,使得后续在所述第一伪栅开口内形成上拉晶体管的栅极结构较困难,从而使得形成的上拉晶体管的栅极结构性能较差,进而影响静态随机存储器的性能。
后续去除第二伪栅结构101形成第二伪栅开口,所述第二伪栅开口用于形成输出晶体管的栅极结构。所述第二伪栅开口沿所述第二伪栅结构101延伸方向上的尺寸过小,使得后续在所述第二伪栅开口内形成输出晶体管的栅极结构较困难,从而使得形成的输出晶体管的栅极结构性能较差,进而影响静态随机存储器的性能。
为解决所述技术问题,本发明提供了一种半导体结构的形成方法,包括:提供基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;形成从第一区延伸至第二区的伪栅结构,所述伪栅结构贯穿所述第三区;分别在所述第一区伪栅结构两侧的基底内形成第一源漏掺杂区;分别在所述第二区伪栅结构两侧的基底内形成第二源漏掺杂区;形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口,所述介质开口暴露出所述第三区的基底;在所述介质开口内形成层间介质层,所述层间介质层的顶部表面与伪栅结构的顶部表面齐平。
所述方法中,形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口。即,在形成所述第一源漏掺杂区和第二源漏掺杂区的过程中,所述介质开口并未形成,因此,在形成第一源漏掺杂区和第二源漏掺杂区时,不影响后续形成的介质开口沿伪栅结构延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内易于形成质量良好的层间介质层的前提下,由于所述介质开口沿伪栅结构延伸方向上的尺寸并未受到第一源漏掺杂区和第二源漏掺杂区的制造工艺的影响,使介质开口无需过度做大。当所述介质开口和伪栅结构总制造空间一定的情况下,所述介质开口沿伪栅结构延伸方向的尺寸较小时,使得用于形成伪栅结构的制造空间较大。而在后栅工艺中,通常去除所述伪栅结构形成伪栅开口,后续在伪栅开口内形成栅极结构。由于伪栅结构的空间尺寸较大,使得去除伪栅结构形成的伪栅开口的空间尺寸较大,因此,在所述伪栅开口内形成栅极结构较容易,且形成的栅极结构性能良好。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图3至图13是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图3,提供基底200,所述基底200包括第一区Ⅰ、第二区Ⅱ和第三区Ⅲ,所述第三区Ⅲ位于所述第一区Ⅰ和第二区Ⅱ之间。
在本实施例中,所述基底200包括:衬底201以及位于所述衬底201上的鳍部202。所述衬底201和鳍部202为后续工艺提供工作平台。
在其它实施例,所述基底为平面式的半导体衬底。
所述半导体衬底201以及所述鳍部202的形成步骤包括:提供初始衬底;在所述初始衬底表面形成图形化掩膜层;以所述图形化掩膜层为掩膜,刻蚀所述初始衬底,形成所述半导体衬底201和位于所述半导体衬底201上的鳍部202。
本实施例中,所述初始衬底的材料为硅。在其他实施例中,所述初始衬底还可以为锗衬底、硅锗衬底、绝缘体上硅或绝缘体上锗等半导体衬底。
在本实施例中,所述基底200还包括:隔离结构203。
所述隔离结构203的形成步骤包括:在半导体衬底201和鳍部202上形成隔离材料层;采用化学机械磨平工艺对所述隔离材料层进行平坦化;刻蚀去除部分所述隔离材料层,形成隔离结构203。所述隔离结构203位于所述鳍部202之间的半导体衬底201上,并覆盖所述鳍部202部分侧壁表面,且所述隔离结构203的顶部表面低于所述鳍部202的顶部表面。
所述隔离材料层的形成方法包括:化学气相沉积工艺。
所述隔离结构203的材料包括:氧化硅。在其他实施例中,所述隔离层的材料还可以为氮氧化硅、氮化硅。
所述隔离结构203用于实现不同半导体器件之间的电绝缘。
在本实施例中,所形成的半导体结构用于形成静态随机存储器;所述第一区Ⅰ用于形成上拉晶体管,所述第二区Ⅱ用于形成输出晶体管,所述第三区Ⅲ用于形成位于所述上拉晶体管与输出晶体管之间的层间介质层。
在其它实施例中,所述第一区用于形成PMOS晶体管,所述第二区用于形成NMOS晶体管,所述第三区用于层间介质层。
请参考图4和图5,图5是图4沿A-A’线的剖面结构示意图,形成从第一区Ⅰ延伸至第二区Ⅱ的伪栅结构204,所述伪栅结构204贯穿所述第三区Ⅲ。
所述伪栅结构204横跨所述鳍部202,所述伪栅结构204包括:伪栅介质层以及位于伪栅介质层上的伪栅极层。所述伪栅介质层覆盖所述鳍部202部分侧壁和顶部表面;所述伪栅极层位于所述伪栅介质层表面。
本实施例中,所述伪栅介质层的材料为氧化硅。在其他实施例中,所述伪栅介质层的材料还可以为氮化硅或氮氧化硅。
本实施例中,所述伪栅极层的材料为多晶硅。
在本实施例中,所述伪栅结构204的顶部表面具有掩膜层(图中未标出),所述掩膜层的材料包括氮化硅,所述掩膜层作为刻蚀形成所述伪栅极层的掩膜。
所述伪栅结构具有伪栅侧墙205,所述伪栅侧墙205的形成步骤包括:在所述伪栅介质层的侧壁、所述伪栅极层的顶部和侧壁以及所述伪栅极层两侧的鳍部202上形成伪栅侧墙膜;去除所述伪栅极层的顶部以及所述伪栅极层两侧的鳍部202上的伪栅侧墙膜,形成伪栅侧墙205。
形成所述伪栅侧墙膜的工艺包括:化学气相沉积工艺。
所述伪栅侧墙膜的材料与所述伪栅侧墙205的材料一致,所述伪栅侧墙205的材料包括:氮化硅。
所述伪栅侧墙205的作用为:用于定义后续形成的第一源漏掺杂区与伪栅结构204的相对位置以及第二源漏掺杂区与所述伪栅结构204的相对位置。
去除所述伪栅极层的顶部以及所述伪栅极层两侧的鳍部202上的伪栅侧墙膜的工艺包括:干法刻蚀工艺或湿法刻蚀工艺。
请参考图6,分别在所述第一区Ⅰ伪栅结构204两侧的鳍部202内形成第一源漏掺杂区(图中未示出);分别在所述第二区Ⅱ伪栅结构204两侧的鳍部202内形成第二源漏掺杂区207。
需要说明的是,图6与图5的剖面方向一致。
在本实施例中,形成所述第一源漏掺杂区之后,形成所述第二源漏掺杂区207;或者,形成所述第一源漏掺杂区之前,形成所述第二源漏掺杂区207。
形成所述第一源漏掺杂区之前,还包括:在所述第二区Ⅱ基底200、第三区Ⅲ基底200以及第三区Ⅲ栅极结构204和第二区Ⅱ伪栅结构204上形成第一保护层(图中未标出)。
所述第一保护层的形成步骤包括:在所述第一区Ⅰ、第二区Ⅱ和第三区Ⅲ的基底以及伪栅结构204上形成第一保护膜;去除位于所述第一区Ⅰ基底200以及第一区Ⅰ伪栅结构204上的第一保护膜,形成第一保护层。
所述第一保护层的厚度为:6纳米~10纳米。选择所述第一保护层的厚度的意义在于:后续在形成第一源漏掺杂区的过程中,所述第一保护层用于保护所述第二区Ⅱ基底200、第三区Ⅲ基底200以及从第三区Ⅲ延伸到第二区Ⅱ伪栅结构204,若所述第一保护层的厚度小于6纳米,所述第一保护层对所述第二区Ⅱ基底200、第三区Ⅲ基底200以及从第三区Ⅲ延伸到第二区Ⅱ伪栅结构204的保护力度不够,从而造成所述第二区Ⅱ基底200、第三区Ⅲ基底200以及第二区Ⅱ伪栅结构204的损伤,进而影响后续工艺;若所述第一保护层的厚度大于10纳米,增加后续去除第二区Ⅱ伪栅结构204上的第一保护层的难度。
所述第一保护层在后续形成的介质开口之前形成,即,在形成所述第一保护层的过程中,介质开口并未形成,因此,所述第一保护层不影响后续形成的介质开口沿伪栅结构204延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内能够形成层间介质层的前提下,由于所述介质开口的侧壁和底部并不无第一保护层的覆盖,因此,能够有效地避免介质开口过度做大。
在所述第二区Ⅱ基底200、第三区Ⅲ基底200以及从第三区Ⅲ伪栅结构204和第二区Ⅱ伪栅结构204上形成第一保护层之后,在所述第一区Ⅰ伪栅结构204两侧的基底200内形成第一源漏掺杂区206。
所述第一源漏掺杂区的形成步骤包括:在所述第一区Ⅰ伪栅结构204两侧的鳍部202上形成图形化的掩膜层;以所述掩膜层为掩膜,采用刻蚀工艺在所述伪栅结构204两侧的鳍部202内形成开口;采用选择性外延沉积工艺在所述开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第一源漏掺杂区。
形成所述第二源漏掺杂区207之前,还包括:在所述第一区Ⅰ基底200、第三区Ⅲ基底200以及第三区伪栅结构204和第一区Ⅰ伪栅结构204上形成第二保护层。
所述第二保护层的形成步骤包括:在所述第一区Ⅰ、第二区Ⅱ和第三区Ⅲ的基底200以及伪栅结构204上形成第二保护膜;去除位于所述第二区基底200以及第二区Ⅱ伪栅结构204上的第二保护膜,形成第二保护层。
所述第二保护层的厚度为:6纳米~10纳米。选择所述第二保护层的厚度的意义在于:后续在形成第二源漏掺杂区207的过程中,所述第二保护层用于保护所述第一区Ⅰ基底200、第三区Ⅲ基底200以及从第三区延伸到第一区Ⅰ伪栅结构204,若所述第二保护层的厚度小于6纳米,所述第二保护层对所述第一区Ⅰ基底200、第三区Ⅲ基底200以及从第三区延伸到第一区Ⅰ伪栅结构204的保护力度不够,从而造成所述第一区Ⅰ基底200、第三区Ⅲ基底200以及从第三区延伸到第一区Ⅰ伪栅结构204的损伤,进而影响后续工艺;若所述第二保护层的厚度大于10纳米,增加后续去除第二区Ⅱ伪栅结构204上的第二保护层的难度。
所述第二保护层在后续形成的介质开口之前形成,即,在形成所述第二保护层的过程中,介质开口并未形成,因此,所述第二保护层不影响后续形成的介质开口沿伪栅结构204延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内能够形成层间介质层的前提下,由于所述介质开口的侧壁和底部并不无第二保护层的覆盖,因此,能够有效地避免介质开口过度做大。
所述第二源漏掺杂区207的形成步骤包括:在所述第二区Ⅱ伪栅结构204两侧的鳍部202上形成图形化的掩膜层;以所述掩膜层为掩膜,采用刻蚀工艺在所述伪栅结构204两侧的鳍部202内形成开口;采用选择性外延沉积工艺在所述开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第二源漏掺杂区207。
请参考图7和图8,图8是图7沿B-B’线的侧面剖视图。在所述隔离结构203、第一源漏掺杂区、第二源漏掺杂区207以及所述鳍部202的顶部表面形成第一层间介质层208,所述第一层间介质层208的顶部表面与所述伪栅极层的顶部表面齐平。
需要说明的是,图7与图5的剖面方向一致。
所述第一层间介质层208的形成步骤包括:在所述隔离结构203、第一源漏掺杂区、第二源漏掺杂区207、鳍部202以及所述伪栅结构204的顶部表面形成第一层间介质膜;平坦化所述第一层间介质膜直至暴露出伪栅极层的顶部表面,形成所述第一层间介质层208。
所述第一层间介质膜的形成工艺包括:化学气相沉积工艺。
平坦化所述第一层间介质膜直至暴露出伪栅极层顶部表面的工艺包括:化学机械研磨工艺。
请参考图9,形成所述第一源漏掺杂区和第二源漏掺杂区207之后,形成贯穿所述伪栅结构204的介质开口209,所述介质开口209暴露出所述第三区Ⅲ基底200。
所述介质开口209的形成步骤包括:去除所述第三区Ⅲ的伪栅结构204,形成介质开口209,所述介质开口209暴露出所述第三区Ⅲ隔离结构203的顶部表面。
去除所述第三区Ⅲ的伪栅结构204的工艺包括:干法刻蚀工艺或湿法刻蚀工艺。
在本实施例中,所述介质开口209沿伪栅结构204延伸方向上的尺寸为:20纳米~40纳米。
若所述介质开口209沿伪栅结构204延伸方向上的尺寸小于20纳米,使得后续在介质开口209内形成层间介质层难度较大。
若所述介质开口209沿伪栅结构204延伸方向上的尺寸大于40纳米,虽然有利于后续在所述介质开口209内形成层间介质层,但是对于静态随机存储器来说,当上拉晶体管、输出晶体管以及位于所述上拉晶体管的栅极结构和输出晶体管的栅极结构之间的层间介质层的总制造空间一定的情况下,用于形成层间介质层的介质开口209沿伪栅结构204延伸方向上的尺寸较大,使得用于形成上拉晶体管的栅极结构和输出晶体管的栅极结构的制造空间较小。后续去除伪栅结构204形成伪栅开口,所述伪栅开口用于形成上拉晶体管的栅极结构和输出晶体管的栅极结构。所述伪栅开口沿所述伪栅结构204延伸方向上的尺寸较小,不利于后续在所述伪栅开口内形成上拉晶体管的栅极结构和输出晶体管的栅极结构。
所述介质开口209用于后续在所述介质开口209内形成层间介质层。
形成所述层间介质层之后,还包括:去除第一区Ⅰ伪栅结构204形成第一伪栅开口;去除第二区Ⅱ伪栅结构204形成第二伪栅开口。
在本实施例中,去除第一区Ⅰ伪栅结构204的步骤包括:去除第一区Ⅰ伪栅极层;去除第一区Ⅰ伪栅极层之后,去除第一区Ⅰ伪栅介质层。
在本实施例中,去除第二区Ⅱ伪栅结构204的步骤包括:去除第二区Ⅱ伪栅极层;去除第二区Ⅱ伪栅极层之后,去除第二区Ⅱ伪栅介质层。
在本实施例中,在去除第一区Ⅰ伪栅结构204和第二区Ⅱ伪栅结构204之前,还包括:在所述介质开口209的侧壁形成第一侧墙和第二侧墙。
在其他实施例中,去除第一区伪栅结构的步骤包括:仅去除第一区伪栅极层。
在其他实施例中,去除第二区伪栅结构的步骤包括:仅去除第二伪栅极层。
以下以去除伪栅介质层为例,说明在所述介质开口209的侧壁形成第一侧墙和第二侧壁的方法。
图10至图11为所述第一侧墙和第二侧墙形成方法各步骤的结构示意图。
请参考图10,在所述介质开口209侧壁形成第二侧墙210。
所述第二侧墙210的形成工艺包括:等离子体氧化工艺。所述等离子体氧化工艺的参数包括:反应物包括:硅前驱体、氧化源,其中,硅前驱体包括:二氯硅烷,温度:200摄氏度~600摄氏度,压力为:1毫托~10毫托,氨气的流量为:1500标准毫升/分~4000标准毫升/分,循环次数:30次~100次。
采用等离子体氧化工艺形成的所述第二侧墙210与所述介质开口209的侧壁的结合力强,且所述第二侧墙210的厚度可控。
在本实施例中,所述介质开口209的侧壁为:伪栅极层,所述伪栅极层的材料为:多晶硅。所述第二侧墙210的形成原理包括:采用等离子体氧化工艺消耗部分所述介质开口209的侧壁形成第二侧墙210。所述第二侧墙210的材料为:氧化硅。
所述第二侧墙210用于后续进一步扩大所述伪栅开口沿所述伪栅结构204延伸方向上的尺寸。
所述第二侧墙210能够进一步扩大所述伪栅开口沿所述伪栅结构204延伸方向上的尺寸,原理在于:所述第二侧墙210通过等离子体氧化工艺消耗部分所述介质开口209的侧壁形成。形成所述第二侧墙210之后,去除伪栅结构204。去除所述伪栅结构204的步骤包括:去除伪栅极层;去除伪栅极层之后,去除伪介质层。在去除所述伪栅介质层的过程中,所述第二侧墙210也被去除,因此,所述第二侧墙210能够进一步扩大所述伪栅开口沿伪栅结构204延伸方向上的尺寸,从而能够降低后续在所述伪栅开口内填充栅极材料层形成上拉晶体管的栅极结构和输出晶体管的栅极结构的难度。
所述第二侧墙210的厚度为:10埃~50埃,选择所述第二侧墙210的厚度的意义在于:后续在去除所述伪栅介质层时,所述第二侧墙210也被去除。若所述第二侧墙210的厚度小于10埃,使得所述第二侧墙210对增大伪栅开口沿所述伪栅结构204延伸方向上尺寸的效果较弱;若所述第二侧墙210的厚度大于50埃,使得所述介质开口209沿伪栅结构204延伸方向上的尺寸减小,不利于后续在所述介质开口209内形成层间介质层。
在其他实施例中,介质开口侧壁不形成第二侧墙。
请参考图11,在第二侧墙210上形成第一侧墙211。
在本实施例中,在形成所述第一侧墙211之前,形成第二侧墙210。
在其他实施例中,在所述介质开口的侧壁形成第一侧墙。
所述第一侧墙211的材料包括:氮化硅。
所述第一侧墙211的材料与后续在介质开口209内形成的层间介质层的材料不同,后续去除所述伪栅结构204的过程中,所述第一侧墙211与层间介质层的刻蚀速率不同,所述第一侧墙211对所述层间介质层起到保护的作用。
所述第一侧墙211的厚度为:2纳米~3纳米。选择所述第一侧墙211厚度的意义在于:若所述第一侧墙211的厚度小于2纳米,后续在去除伪栅结构204时,所述第一侧墙211对后续形成的层间介质层的保护力度不够,使得所述层间介质层可能被刻穿,进而影响SRAM单元的性能;若所述第一侧墙211的厚度大于3纳米,使得介质开口209沿伪栅结构204延伸方向上的尺寸减小,不利于后续在所述介质开口209内形成层间介质层。
请参考图12,形成第一侧墙211之后,在所述介质开口209内形成层间介质层212,所述层间介质层212的顶部表面与伪栅结构204的顶部表面齐平。
所述层间介质层212的形成步骤包括:在所述介质开口209内以及伪栅结构204上形成层间介质膜,平坦化所述层间介质膜直至暴露出所述伪栅极层的顶部表面,形成层间介质层212。
所述介质开口209侧壁形成的第一侧墙211和第二侧墙210的厚度较薄,因此,所述第一侧墙211和第二侧墙210对所述介质开口209沿伪栅结构204沟道长度方向上的尺寸影响较小,使得在所述介质开口209内形成层间介质层较容易。
所述层间介质层212用于隔离后续形成的第一区Ⅰ上拉晶体管的栅极结构和第二区Ⅱ输出晶体管的栅极结构。
请参考图13,去除所述第一区Ⅰ伪栅结构204形成第一伪栅开口;在所述第一伪栅开口内形成第一栅极材料层;平坦化所述第一栅极材料层,直至暴露出层间介质层表面,形成上拉晶体管的栅极结构;去除所述第二区Ⅱ伪栅结构204形成第二伪栅开口;在所述第二伪栅开口内形成第二栅极材料层;平坦化所述第二栅极材料层,直至暴露出层间介质层表面,形成输出晶体管的栅极结构。
去除所述第一区Ⅰ伪栅结构204形成第一伪栅开口的步骤包括:去除第一区Ⅰ伪栅极层;去除第一区Ⅰ伪栅极层之后,去除第一区Ⅰ伪栅介质层。
去除第一区Ⅰ伪栅极层和去除第一区Ⅰ所述伪栅介质层的工艺包括:干法刻蚀工艺或湿法刻蚀工艺。
第一栅极材料层的形成步骤包括:在所述第一伪栅开口内形成界面层;在界面层上形成高K介质层;在高K介质层上形成功函数层;在功函数层上形成金属硅化物层;形成所述金属硅化物之后,在所述金属硅化物上形成金属材料层。
所述第一区Ⅰ到第三区Ⅲ距离最近的鳍部202定义为:第一鳍部。
所述第二侧墙210通过等离子体氧化工艺消耗部分所述介质开口209的侧壁形成。所述第二侧墙210的材料为氧化硅,所述第二侧墙210的材料与所述第一区Ⅰ伪栅介质层的材料相同,因此在去除所述第一区Ⅰ伪栅介质层的过程中,所述第二侧墙210也被去除。所述第二侧墙210被去除后,使得所述第一鳍部侧壁到第一伪栅开口侧壁的距离b1增大,使得后续在所述第一伪栅开口内填充第一栅极材料层时,较为容易,所形成的上拉晶体管的栅极结构性能较好,从而提高静态随机存储器的性能。
去除所述第二区Ⅱ伪栅结构204形成第二伪栅开口的步骤包括:去除第二区Ⅱ伪栅极层;去除第二区Ⅱ伪栅极层之后,去除第二区Ⅱ伪栅介质层。
去除第二区Ⅱ伪栅极层和去除第二区Ⅱ所述伪栅介质层的工艺包括:干法刻蚀工艺或湿法刻蚀工艺。
第二栅极材料层的形成步骤包括:在所述第二伪栅开口内形成界面层;在界面层上形成高K介质层;在高K介质层上形成功函数层;在功函数层上形成金属硅化物层;形成所述金属硅化物之后,在所述金属硅化物上形成金属材料层。
所述第二区Ⅱ到第三区Ⅲ距离最近的鳍部202定义为:第二鳍部。
所述第二侧墙210通过等离子体氧化工艺消耗部分所述介质开口209的侧壁形成。所述第二侧墙210的材料为氧化硅,所述第二侧墙210的材料与所述第二区Ⅱ伪栅介质层的材料相同,因此在去除所述第二区Ⅱ伪栅介质层的过程中,所述第二侧墙210也被去除。所述第二侧墙210被去除后,使得所述第二鳍部侧壁到第二伪栅开口侧壁的距离b2增大,使得后续在所述第二伪栅开口内填充栅极材料层时,较为容易,且形成的输出晶体管的栅极结构性能较好,从而提高静态随机存储器的性能。
综上,在本实施例中,形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口。即,在形成所述第一源漏掺杂区和第二源漏掺杂区的过程中,所述介质开口并未形成,因此,在形成第一源漏掺杂区和第二源漏掺杂区时,不影响后续形成的介质开口沿伪栅结构延伸方向上的尺寸,使得后续在所述介质开口内形成层间介质层较容易。并且,在所述介质开口内易于形成质量良好的层间介质层的前提下,由于所述介质开口沿伪栅结构延伸方向上的尺寸并未受到第一源漏掺杂区和第二源漏掺杂区的制造工艺的影响,使介质开口无需过度做大。当所述介质开口和伪栅结构的总制造空间一定的情况下,所述介质开口沿伪栅结构延伸方向的尺寸较小时,使得用于形成伪栅结构的制造空间较大。而在后栅工艺中,通常去除所述伪栅结构形成伪栅开口,后续在伪栅开口内形成栅极结构。由于伪栅结构的空间尺寸较大,使得去除伪栅结构形成的伪栅开口的空间尺寸较大,因此,在所述伪栅开口内形成栅极结构较容易,且形成的栅极结构性能良好。
相应的,本发明实施例还提供一种采用上述方法所形成的半导体结构,请参考图9,包括:
基底200,所述基底200包括第一区Ⅰ、第二区Ⅱ和第三区Ⅲ,所述第三区Ⅲ位于所述第一区Ⅰ和第二区Ⅱ之间;
从第一区Ⅰ延伸至第二区Ⅱ的伪栅结构204,所述伪栅结构204贯穿所述第三区Ⅲ,位于所述第一区Ⅰ伪栅结构204两侧基底200内的第一源漏掺杂区206(见图7),位于所述第二区Ⅱ伪栅结构204两侧基底200内的第二源漏掺杂区207(见图7);
贯穿所述伪栅结构204的介质开口209,所述介质开口209暴露出所述第三区Ⅲ基底。
所述介质开口209沿所述伪栅结构204延伸方向上的尺寸为:20纳米~40纳米。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (20)
1.一种半导体结构的形成方法,其特征在于,包括:
提供基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;
形成从第一区延伸至第二区的伪栅结构,所述伪栅结构贯穿所述第三区;
分别在所述第一区伪栅结构两侧的基底内形成第一源漏掺杂区;
分别在所述第二区伪栅结构两侧的基底内形成第二源漏掺杂区;
形成所述第一源漏掺杂区和第二源漏掺杂区之后,形成贯穿所述伪栅结构的介质开口,所述介质开口暴露出第三区的基底;
在所述介质开口内形成层间介质层,所述层间介质层的顶部表面与伪栅结构的顶部表面齐平。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第一源漏掺杂区之前,还包括:在所述第二区基底、第三区基底、第三区伪栅结构和第二区伪栅结构上形成第一保护层;所述第一保护层的厚度为:6纳米~10纳米。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,所述第一保护层的形成步骤包括:在所述第一区、第二区和第三区的基底以及伪栅结构上形成第一保护膜;去除位于所述第一区基底以及第一区伪栅结构上的第一保护膜,形成第一保护层。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第一区伪栅结构两侧的基底内形成第一开口;采用选择性外延沉积工艺在所述第一开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第一源漏掺杂区。
5.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第二源漏掺杂区之前,还包括:在所述第一区基底、第三区基底、第一区伪栅结构和第三区伪栅结构上形成第二保护层;所述第二保护层的厚度为:6纳米~10纳米。
6.如权利要求5所述的半导体结构的形成方法,其特征在于,所述第二保护层的形成步骤包括:在所述第一区、第二区和第三区的基底以及伪栅结构上形成第二保护膜;去除位于所述第二区基底以及第二区伪栅结构上的第二保护膜,形成第二保护层。
7.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第二源漏掺杂区的形成步骤包括:采用刻蚀工艺在所述第二区伪栅结构两侧的基底内形成第二开口;采用选择性外延沉积工艺在所述第二开口内形成外延层;在所述外延层内掺杂P型离子或N型离子,形成所述第二源漏掺杂区。
8.如权利要求1所述的半导体结构的形成方法,其特征在于,所述介质开口在沿伪栅结构延伸方向上的尺寸为:20纳米~40纳米。
9.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述层间介质层之后,还包括:去除伪栅结构形成伪栅开口。
10.如权利要求9所述的半导体结构的形成方法,其特征在于,所述伪栅结构包括:伪栅极层;去除所述伪栅结构的步骤包括:去除伪栅极层。
11.如权利要求10所述的半导体结构的形成方法,其特征在于,所述伪栅结构还包括:伪栅介质层;所述伪栅极层位于所述伪栅介质层上;去除所述伪栅结构的步骤还包括:去除伪栅极层之后,去除伪栅介质层。
12.如权利要求1所述的半导体结构的形成方法,其特征在于,在形成层间介质层之前,还包括:在所述介质开口的侧壁形成第一侧墙。
13.如权利要求12所述的半导体结构的形成方法,其特征在于,所述第一侧墙的材料包括:氮化硅;所述第一侧墙的厚度为:2纳米~3纳米。
14.如权利要求12所述的半导体结构的形成方法,其特征在于,形成所述第一侧墙之前,还包括:在所述介质开口侧壁上形成第二侧墙。
15.如权利要求14所述的半导体结构的形成方法,其特征在于,所述第二侧墙的材料包括:氧化硅;所述第二侧墙的厚度包括:10埃~50埃。
16.如权利要求15所述的半导体结构的形成方法,其特征在于,所述伪栅结构包括:伪栅介质层以及位于伪栅介质层上的伪栅极层;形成所述层间介质层之后,还包括:去除伪栅极层和伪栅介质层形成伪栅开口,且在去除伪栅介质层时去除所述第二侧墙。
17.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一区用于形成上拉晶体管,所述第二区用于形成输出晶体管,所述第三区用于形成位于所述上拉晶体管的栅极结构与所述输出晶体管的栅极结构之间的层间介质层。
18.如权利要求17所述的半导体结构的形成方法,其特征在于,所述上拉晶体管的栅极结构的形成步骤包括:去除第一区伪栅结构形成第一伪栅开口;在所述第一伪栅开口内形成第一栅极材料层;平坦化所述第一栅极材料层,直至暴露出层间介质层表面;所述输出晶体管的栅极结构的形成步骤包括:去除第二区伪栅结构形成第二伪栅开口;在所述第二伪栅开口内形成第二栅极材料层;平坦化所述第二栅极材料层,直至暴露出层间介质层表面。
19.如权利要求1所述的半导体结构的形成方法,其特征在于,所述基底包括:衬底以及位于所述衬底上的鳍部,所述鳍部之间的衬底上具有隔离结构,所述隔离结构的顶部表面低于所述鳍部的顶部表面,且覆盖所述鳍部的部分侧壁,横跨所述鳍部的伪栅结构,所述伪栅结构覆盖所述鳍部的部分侧壁和顶部表面;所述介质开口暴露出第三区隔离结构的顶部表面。
20.一种采用如权利要求1至19任一项方法所形成的半导体结构,其特征在于,包括:
基底,所述基底包括第一区、第二区和第三区,所述第三区位于所述第一区和第二区之间;
从第一区延伸至第二区的伪栅结构,所述伪栅结构贯穿所述第三区,位于所述第一区伪栅结构两侧基底内的第一源漏掺杂区,位于所述第二区伪栅结构两侧基底内的第二源漏掺杂区;
贯穿所述伪栅结构的介质层开口,所述介质层开口暴露出所述第三区基底;
位于所述介质层开口内的层间介质层,所述层间介质层的顶部表面与伪栅结构的顶部表面齐平。
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