CN103855093B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103855093B
CN103855093B CN201210505754.3A CN201210505754A CN103855093B CN 103855093 B CN103855093 B CN 103855093B CN 201210505754 A CN201210505754 A CN 201210505754A CN 103855093 B CN103855093 B CN 103855093B
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layer
metal gate
adulterant
semiconductor
semiconductor fin
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CN103855093A (zh
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朱慧珑
徐秋霞
张严波
杨红
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210505754.3A priority Critical patent/CN103855093B/zh
Priority to PCT/CN2012/086128 priority patent/WO2014082336A1/zh
Publication of CN103855093A publication Critical patent/CN103855093A/zh
Priority to US14/722,684 priority patent/US20150255557A1/en
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Abstract

公开了一种半导体器件及其制造方法。半导体器件的制造方法包括：在半导体衬底上形成半导体鳍片；在半导体鳍片的顶部表面和侧壁上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；通过共形掺杂在第一金属栅层中注入掺杂剂；以及进行退火以使掺杂剂扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体技术领域，具体地涉及包括金属栅和高K栅介质的半导体器件及其制造方法。
背景技术
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小导致栅电流泄漏的严重问题。高K栅介质的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度，因而可以降低栅隧穿漏电流。然而，传统的多晶硅栅与高K栅介质不兼容。金属栅与高K栅介质一起使用不仅可以避免多晶硅栅的耗尽效应，减小栅电阻，还可以避免硼穿透，提高器件的可靠性。因此，金属栅和高K栅介质的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质的集成仍然面临许多挑战，如热稳定性问题、界面态问题。特别是由于费米钉扎效应，采用金属栅和高K栅介质的MOSFET难以获得适当低的阈值电压。
在集成N型和P型FinFET的CMOS应用中，为了获得合适的阈值电压，N型FinFET的有效功函数应当在Si的导带底附近(4.1eV左右)，P型FinFET的有效功函数应当在Si的价带顶附近(5.2eV左右)。可以针对N型FinFET和P型FinFET分别选择不同的金属栅和高K栅介质的组合以实现所需的阈值电压。结果，需要在一个芯片上形成双金属栅和双高K栅介质。在半导体器件的制造期间，分别针对N型和P型FinFET的金属栅和高K栅介质执行各自的光刻和蚀刻步骤。因此，用于制造包括双金属栅和双栅介质的半导体器件的方法工艺复杂，不适合批量生产，这进一步导致成本高昂。
发明内容
本发明的目的是提供一种改进的半导体器件及其方法，其中可以在制造过程调节半导体器件的有效功函数。
根据本发明的一方面，提供一种半导体器件的制造方法，所述方法包括：在半导体衬底上形成半导体鳍片；在半导体鳍片的顶部表面和侧壁上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；通过共形掺杂在第一金属栅层中注入掺杂剂；以及进行退火以使掺杂剂扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。在优选的实施例中，所述半导体器件包括在一个半导体衬底上形成的N型FinFET和P型FinFET，并且在N型FinFET的第一金属栅层注入用于减小有效功函数的掺杂剂，在P型FinFET的第一金属栅层中注入于增加有效功函数的掺杂剂。
根据本发明的另一方面，提供一种半导体器件，包括：位于半导体衬底上的半导体鳍片；位于半导体鳍片的顶部表面和侧壁上的界面氧化物层；位于界面氧化物层上的高K栅介质；以及位于高K栅介质上的第一金属栅层，其中掺杂剂分布在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
根据本发明，一方面，在高K栅介质的上界面处聚积的掺杂剂改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质的下界面处聚积的掺杂剂通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。该方法获得的半导体器件的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。针对两种类型的MOSFET选择不同的掺杂剂，可以减小或增加有效功函数。在CMOS器件中，仅仅通过改变掺杂剂，就可以分别调节两种类型的MOSFET的阈值电压，而不需要分别使用金属栅和栅介质的不同组合。因此，该方法可以省去相应的沉积步骤和掩模及刻蚀步骤，从而实现了简化工艺且易于大量生产。共形掺杂改善了掺杂剂在半导体鳍片的顶部和侧壁附近的分布均匀性，从而可以抑制阈值电压的随机波动。
在优选的实施例中，该半导体器件还包括在半导体衬底和半导体鳍片之间的掺杂穿通阻止层，或者位于半导体衬底中的阱。该掺杂穿通阻止层和/或阱与源/漏区的掺杂类型相反，以减小源/漏区之间的漏电流。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1至13示意性地示出根据本发明的方法的一个实施例在制造半导体器件的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中，无论是否显示在不同实施例中，类似的部件采用相同或类似的附图标记表示。在各个附图中，为了清楚起见，附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
在本申请中，术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者，并且采用相同的一个附图标记标示。术语“负掺杂剂”是指用于N型FinFET的可以减小有效功函数的掺杂剂。术语“正掺杂剂”是指用于P型FinFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例，参照图1至13说明制造半导体器件的方法，其中，在图7a-9a中示出了半导体结构的俯视图及截面图的截取位置，在图1-6、7b-9b和13a中示出在半导体鳍片的宽度方向上沿线A-A截取的半导体结构的截面图，在图10-11、12B和13b中示出在P型FinFET的半导体鳍片的长度方向上沿线B-B截取的半导体结构的截面图，图12A中示出在N型FinFET的半导体鳍片的长度方向上沿线C-C截取的半导体结构的截面图。该半导体器件是包括在一个半导体衬底上形成的N型FinFET和P型FinFET的CMOS器件。
在图1中所示的半导体结构已经完成了一部分CMOS工艺。在半导体衬底101(例如，Si衬底)中的一定深度位置形成用于N型FinFET的P阱102a和用于P型FinFET的N阱102b。在图1所示的示例中，将P阱102a和N阱102b示出为矩形并且直接邻接，但实际上P阱102a和N阱102b可能没有清晰的边界，并且可能由半导体衬底101的一部分隔开。半导体层103(例如，Si)位于P阱102a和N阱102b上方，并且将用于形成半导体鳍片。半导体层103的厚度大致等于将要形成的半导体鳍片的高度。在一个示例中，半导体层103由半导体衬底101位于P阱102a和N阱102b上方的一部分形成。在替代的示例中，半导体层103由在P阱102a和N阱102b上方外延生长的层形成。
然后，例如通过旋涂在半导体层103上形成光致抗蚀剂层PR1，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层PR1形成用于限定半导体鳍片的形状(例如，条带)的图案。
采用光致抗蚀剂层PR1作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻，去除半导体层103的暴露部分，在P阱102a和N阱102b中形成开口，如图2所示。在开口之间将半导体层103限定为用于N型FinFET的半导体鳍片103a和用于P型FinFET的半导体鳍片103b。通过控制蚀刻的时间，可以控制改变开口的深度。在图2所示的示例中，将开口示出为其底部位于P阱102a和N阱102b中。在替代的示例中，通过延长蚀刻的时间，使得开口的底部位于P阱102a和N阱102b下方的半导体衬底101中。
优选地，在形成半导体鳍片103a和103b之前，可以通过离子注入在半导体层103的下部形成与源/漏区的掺杂类型相反的掺杂穿通阻止层。半导体鳍片103a和103b由半导体层103的上部形成。该掺杂穿通阻止层可以减小源/漏区之间经由半导体衬底的漏电流。
然后，通过在溶剂中溶解或灰化去除光致抗蚀剂层PR1。例如通过旋涂在半导体结构的表面上形成光致抗蚀剂层PR2。将光致抗蚀剂层PR2形成用于限定N型FinFET和P型FinFET之间的浅沟槽的图案。光致抗蚀剂层PR2至少遮挡先前形成的半导体鳍片103a和103b。
采用光致抗蚀剂层PR2作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻，去除半导体层103的暴露部分，在P阱102a和N阱102b之间中形成浅沟槽，如图3所示。通过控制蚀刻的时间，可以改变浅沟槽的深度。该浅沟槽隔开N型FinFET和P型FinFET的有源区。在图3所示的示例中，将浅沟槽示出为其底部位于P阱102a和N阱102b中。在替代的示例中，通过延长蚀刻的时间，使得开口的底部可以位于P阱102a和N阱102b下方的半导体衬底101中。
然后，通过在溶剂中溶解或灰化去除光致抗蚀剂层PR2。通过已知的沉积工艺，如电子束蒸发(EBM)、化学气相沉积(CVD)、原子层沉积(ALD)、溅射等，在半导体结构的表面上形成第一绝缘层104(例如，氧化硅)。第一绝缘层104覆盖半导体鳍片，并且填充用于限定半导体鳍片的开口以及用于隔开N型FinFET和P型FinFET的浅沟槽，如图4所示。如果需要，可以对第一绝缘层104进行化学机械抛光(CMP)，以获得平整的表面。
在一个示例中，可以通过高密度等离子体沉积(HDP)工艺形成第一绝缘层104。通过控制工艺淀积参数，使得第一绝缘层104在半导体鳍片103a和103b的顶部上的部分厚度远远小于位于半导体鳍片103a和103b之间的开口内的部分厚度，优选为半导体鳍片103a和103b的顶部上的部分厚度小于位于半导体鳍片103a和103b之间的开口内的部分厚度的三分之一，优选小于四分之一，且优选为第一绝缘层104在半导体鳍片103a和103b的顶部上的部分的厚度小于半导体鳍片103a和103b之间间距(即开口宽度)的一半。在一个示例中，第一绝缘层104在开口内的部分的厚度大于80nm，第一绝缘层104位于半导体鳍片103a和103b顶部的部分的厚度小于20nm。
然后，通过选择性的蚀刻工艺(例如，反应离子蚀刻)，回蚀刻第一绝缘层104，如图5所示。该蚀刻不仅去除第一绝缘层104位于半导体鳍片103a和103b的顶部上的部分，而且减小第一绝缘层104位于开口内的部分的厚度。控制蚀刻的时间，使得第一绝缘层104的位于开口内的部分的顶部与半导体鳍片103a和103b的底部齐平或更低，从而可完全暴露半导体鳍片103a和103b的顶部和侧壁。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成假栅极电介质105(例如，氧化硅或氮化硅)。在一个示例中，假栅极电介质105为约0.8-1.5nm厚的氧化硅层。假栅极电介质105覆盖半导体鳍片103a和103b的顶部表面和侧面。进一步地，通过上述已知的沉积工艺，在半导体结构的表面上形成假栅导体106(例如，多晶硅或非晶硅层(α-Si))，如图6所示。如果需要，可以对假栅导体106进行化学机械抛光(CMP)，以获得平整的表面。
然后，采用光致抗蚀剂掩模(未示出)或硬掩模(未示出)进行图案化以形成假栅叠层。在图案化中，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅导体106的暴露部分，分别形成N型FinFET和P型FinFET的假栅导体106a和106b，如图7a和7b所示。在图7a所示的示例中，N型FinFET和P型FinFET的假栅导体106a和106b是两个隔开并且分别横跨半导体鳍片103a和103b的条带图案，但假栅导体106a和106b也可以是其他形状。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成氮化物层。在一个示例中，该氮化物层为厚度约5-30nm的氮化硅层。通过各向异性的蚀刻工艺(例如，反应离子蚀刻)，去除氮化物层的横向延伸的部分，使得氮化物层位于假栅导体106a和106b的侧面上的垂直部分保留，从而形成栅极侧墙107a和107b，如图8a和8b所示。假栅导体106a和106b的高度例如是半导体鳍片103a和103b的高度的两倍或更大。由于形状因子，半导体鳍片103a和103b侧面上的氮化物层厚度比假栅导体106a和106b的侧面上的氮化物层厚度小，从而在该蚀刻步骤中可以完全去除半导体鳍片103a和103b侧壁上的氮化物层。否则，半导体鳍片103a和103b侧面上的氮化物层厚度太大可能妨碍形成栅极侧墙。可以采用附加的掩模进一步去除半导体鳍片103a和103b侧面上的氮化物层。结果，栅极侧墙107a和107b围绕假栅导体106a和106b，而没有形成在半导体鳍片103a和103b的侧壁上。
在形成栅极侧墙107a和107b之后，可以采用假栅导体及其侧墙作为硬掩模进行源/漏离子注入，并进行激活退火，从而在半导体鳍片103a和103b中形成N型FinFET的源/漏区(未示出)以及P型FinFET的源/漏区(未示出)。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二绝缘层108(例如，氧化硅)。第二绝缘层108覆盖假栅导体106a和106b以及半导体鳍片103a和103b。对第二绝缘层108进行化学机械抛光(CMP)，以获得平整的表面。该CMP可以去除第二绝缘层108位于假栅导体106a和106b的顶部的部分，并且可以进一步去除假栅导体106a和106b的一部分，如图9a和9b所示。
然后，以第二绝缘层108以及栅极侧墙107a和107b作为硬掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅导体106a和106b，并且进一步去除假栅极电介质105位于假栅导体106a和106b下方的部分，如图10所示。在一个示例中，假栅导体106a和106b由多晶硅组成，并且在该蚀刻中，通过其中使用合适的蚀刻剂(例如甲基氢氧化铵，缩写为TMAH)溶液的湿法蚀刻去除。该蚀刻形成暴露半导体鳍片103a和103b的顶部表面和侧壁的栅极开口。
然后，通过化学氧化或附加的热氧化，在半导体鳍片103a和103b的暴露表面和侧壁上形成界面氧化物层109a和109b(例如，氧化硅)。在一个示例中，通过在约600-900℃的温度下进行20—120s的快速热氧化形成界面氧化物层109a和109b。在另一个示例中，通过含臭氧(O3)的水溶液中进行化学氧化形成界面氧化物层109a和109b。
优选地，在形成界面氧化物层109a和109b之前，对半导体鳍片103a和103b的表面进行清洗。该清洗包括首先进行常规的清洗，然后浸入包括氢氟酸、异丙醇和水的混合溶液中，然后采用去离子水冲洗，最后甩干。在一个示例中，该混合溶液的成分为氢氟酸：异丙醇：水的体积比约为0.2-1.5％：0.01-0.10％：1，并且浸入时间约为1-10分钟。该清洗可以获得半导体鳍片103a和103b的洁净的表面，抑制硅表面自然氧化物的生成和颗粒污染，从而有利于形成高质量的界面氧化物层109a和109b。
然后，通过已知的沉积工艺，如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、溅射等，在半导体结构的表面上依次形成共形的高K栅介质110和第一金属栅层111，如图11所示。
高K栅介质110由介电常数大于SiO2的合适材料构成，例如可以是选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种。第一金属栅层111由可以用于形成金属栅的合适材料构成，例如可以是选自TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个示例中，界面氧化物层109a和109b例如是厚度约为0.2-0.8nm的氧化硅层。高K栅介质110例如是厚度约2-5nm的HfO2层，第一金属栅层111例如是厚度约1-10nm的TiN层。
优选地，在形成高K栅介质110和形成第一金属栅层111之间还可以包括高K栅介质沉积后退火(postdepositionannealing)，以改善高K栅介质的质量，这有利于随后形成的第一金属栅层111获得均匀的厚度。在一个示例中，通过在500-1000℃的温度进行5-100s的快速热退火作为沉积后退火。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模(未示出)，以遮挡P型FinFET的有源区并暴露N型FinFET的有源区。采用该光致抗蚀剂掩模，采用共形掺杂(conformaldoping)在N型FinFET的有源区的第一金属栅层111中注入负掺杂剂，如图12a所示。用于金属栅的负掺杂剂可以是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。控制离子注入的能量和剂量，使得注入的掺杂剂仅仅分布在第一金属栅层111中，而没有进入高K栅介质110a，并且控制离子注入的能量和剂量，使得第一金属栅层111具有合适的掺杂深度和浓度以获得期望的阈值电压。在一个示例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模(未示出)，以遮挡N型FinFET的有源区并暴露P型FinFET的有源区。采用该光致抗蚀剂掩模，采用共形掺杂(conformaldoping)在P型FinFET的有源区的第一金属栅层111中注入正掺杂剂，如图12b所示。用于金属栅的正掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量，使得注入的掺杂剂仅仅分布在第一金属栅层111中，而没有进入高K栅介质110b。并且使得第一金属栅层111具有合适的掺杂深度和浓度，以获得期望的阈值电压。在一个示例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二金属栅层112a和112b。以第二绝缘层108作为停止层进行化学机械抛光(CMP)，以去除第二金属栅层位于栅极开口外的部分，而仅仅保留位于栅极开口内的部分，如图13a和13b所示。第二金属栅层可以由与第一金属栅层相同或不同的材料组成，例如可以是选自W、TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个示例中，第二金属栅层例如是厚度约2-30nm的W层。在图中示出N型FinFET的栅叠层包括第二金属栅层112a、第一金属栅层111a、高K栅介质110a和界面氧化物层109a，P型FinFET的栅叠层包括第二金属栅层112b、第一金属栅层111b、高K栅介质110b和界面氧化物层109b。尽管N型FinFET和P型FinFET的栅叠层由相同的层形成，但两者的金属栅中包含相反类型的掺杂剂对有效功函数起到相反的调节作用。
在针对金属栅的掺杂的步骤之后，例如在形成第二金属栅层113之前或之后，上述半导体结构在惰性气氛(例如N2)或弱还原性气氛(例如N2和H2的混合气氛)中进行退火。在一个示例中，在炉中进行退火，退火温度约为350℃-700℃，退火时间约为5-30分钟。退火驱使注入的掺杂剂扩散并聚积在高K栅介质110a和110b的上界面和下界面处，并且进一步在高K栅介质110a和110b的下界面处通过界面反应形成电偶极子。这里，高K栅介质110a和110b的上界面是指其与上方的第一金属栅层111a和111b之间的界面，高K栅介质110a和110b的下界面是指其与下方的界面氧化物层109a和109b之间的界面。
该退火改变了掺杂剂的分布。一方面，在高K栅介质110a和110b的上界面处聚积的掺杂剂改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质110a和110b的下界面处聚积的掺杂剂通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。结果，N型FinFET的栅叠层的有效功函数可以在4.1eV至4.5eV的范围内改变，P型FInFET的栅叠层的有效功函数可以在4.8eV至5.2eV的范围内改变。
在上文中并未描述制造半导体器件的所有细节，例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的半导体器件中，因此对此不再详述。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (17)

1.一种半导体器件的制造方法，所述方法包括：
在半导体衬底上形成半导体鳍片；
形成横跨半导体鳍片的假栅叠层，假栅叠层包括假栅导体和位于假栅导体和半导体鳍片之间的假栅极电介质；
形成围绕假栅导体的栅极侧墙；
在半导体鳍片中形成源/漏区；
去除假栅叠层以形成暴露半导体鳍片的顶部表面和侧壁的栅极开口；
在半导体鳍片的顶部表面和侧壁上形成界面氧化物层；
在界面氧化物层上形成高K栅介质；
在高K栅介质上形成第一金属栅层；
通过共形掺杂在第一金属栅层中注入掺杂剂；
在第一金属栅层上形成第二金属栅层以填充栅极开口；
去除高K栅介质、第一金属栅层和第二金属栅层位于栅极开口外的部分；以及
进行退火以改变栅叠层的有效功函数，其中栅叠层包括第一金属栅层、高K栅介质和界面氧化物层。
2.根据权利要求1所述的方法，在形成半导体鳍片的步骤之前，还包括在半导体衬底和半导体鳍片之间形成掺杂穿通阻止层，使得随后形成的半导体鳍片位于掺杂穿通阻止层上。
3.根据权利要求1所述的方法，其中在第一金属栅层中注入掺杂剂的步骤中，控制离子注入的能量和剂量使得掺杂剂仅仅分布在第一金属栅层中。
4.根据权利要求3所述的方法，其中离子注入的能量为0.2KeV-30KeV。
5.根据权利要求3所述的方法，其中离子注入的剂量为1E13-1E15cm-2。
6.根据权利要求1所述的方法，其中所述半导体器件包括在一个半导体衬底上形成的N型FinFET和P型FinFET，并且在第一金属栅层中注入掺杂剂的步骤包括：
在遮挡P型FinFET的情形下，采用第一掺杂剂注入对N型FinFET的第一金属栅层进行离子注入；以及
在遮挡N型FinFET的情形下，采用第二掺杂剂注入对P型FinFET的第一金属栅层进行离子注入。
7.根据权利要求6所述的方法，其中第一掺杂剂是可以减小有效功函数的掺杂剂。
8.根据权利要求7所述的方法，其中第一掺杂剂是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。
9.根据权利要求6所述的方法，其中第二掺杂剂是可以增加有效功函数的掺杂剂。
10.根据权利要求9所述的方法，其中第二掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
11.根据权利要求1所述的方法，其中在惰性气氛或弱还原性气氛中执行退火，退火温度为350℃-450℃，退火时间为20-90分钟。
12.一种半导体器件，包括：
位于半导体衬底上的半导体鳍片；
位于半导体鳍片的顶部表面和侧壁上的界面氧化物层；
位于界面氧化物层上的高K栅介质；
位于高K栅介质上的第一金属栅层；
位于第一金属栅层上的第二金属栅层；
栅极侧墙，使得界面氧化物层、高K栅介质、第一金属栅层和第二金属栅层由栅极侧墙围绕；以及
位于半导体鳍片中的源/漏区，
其中掺杂剂分布在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
13.根据权利要求12所述的半导体器件，还包括：位于半导体衬底和半导体鳍片之间的掺杂穿通阻止层。
14.根据权利要求12所述的半导体器件，还包括：
位于半导体衬底中的阱，其中阱的掺杂类型与半导体器件的源/漏区的掺杂类型相反，并且半导体鳍片位于阱上方。
15.根据权利要求12所述的半导体器件，包括在一个半导体衬底上形成的N型FinFET和P型FinFET，其中N型FinFET中的第一掺杂剂可以减小有效功函数，P型FinFET中的第二掺杂剂可以增加有效功函数。
16.根据权利要求15所述的半导体器件，其中第一掺杂剂是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。
17.根据权利要求15所述的半导体器件，其中第二掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
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