CN103854983A - P型mosfet的制造方法 - Google Patents

P型mosfet的制造方法 Download PDF

Info

Publication number
CN103854983A
CN103854983A CN201210506496.0A CN201210506496A CN103854983A CN 103854983 A CN103854983 A CN 103854983A CN 201210506496 A CN201210506496 A CN 201210506496A CN 103854983 A CN103854983 A CN 103854983A
Authority
CN
China
Prior art keywords
gate
layer
metal gate
gate dielectric
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210506496.0A
Other languages
English (en)
Other versions
CN103854983B (zh
Inventor
徐秋霞
朱慧珑
周华杰
许高博
梁擎擎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210506496.0A priority Critical patent/CN103854983B/zh
Priority to US14/004,802 priority patent/US9196706B2/en
Priority to PCT/CN2012/086172 priority patent/WO2014082341A1/zh
Publication of CN103854983A publication Critical patent/CN103854983A/zh
Application granted granted Critical
Publication of CN103854983B publication Critical patent/CN103854983B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了一种P型MOSFET的制造方法，该方法包括：在半导体衬底上形成MOSFET的一部分，包括位于半导体衬底中的源/漏区、在半导体衬底上方位于源/漏区之间的假栅叠层、以及围绕假栅叠层的栅极侧墙；去除MOSFET的假栅叠层以形成栅极开口，以暴露半导体衬底的表面；在半导体的暴露表面上形成界面氧化物层；在栅极开口内的界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；在第一金属栅层中注入掺杂离子；以及进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。

Description

P型MOSFET的制造方法
技术领域
本发明涉及半导体技术领域，具体地涉及包括金属栅和高K栅介质的P型MOSFET的制造方法。
背景技术
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小可能导致电流泄漏的问题。高K栅介质的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度，因而可以降低栅隧穿漏电流。然而，传统的多晶硅栅与高K栅介质不兼容。金属栅与高K栅介质一起使用不仅可以避免多晶硅栅的耗尽效应，减小栅电阻，还可以避免硼穿透，提高器件的可靠性。因此，金属栅和高K栅介质的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质的集成仍然面临许多挑战，如热稳定性问题、界面态问题。特别是由于费米钉扎效应，采用金属栅和高K栅介质的MOSFET难以获得适当低的阈值电压。
为了获得合适的阈值电压，P型MOSFET的有效功函数应当在Si的价带顶附近(5.2eV左右)。对于P型MOSFET，期望选择合适的金属栅和高K栅介质的组合以实现所需的阈值电压。然而，仅仅通过材料的选择获得如此高的有效功函数是困难的。
发明内容
本发明的目的是提供一种改进的制造P型MOSFET的方法，其中可以在制造过程调节半导体器件的有效功函数。
根据本发明，提供一种P型MOSFET的制造方法，所述方法包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的所述部分包括位于半导体衬底中的源/漏区、在半导体衬底上方位于源/漏区之间的假栅叠层、以及围绕假栅叠层的栅极侧墙；去除所述MOSFET的假栅叠层以形成栅极开口，该栅极开口暴露半导体衬底的表面；在半导体的暴露表面上形成界面氧化物层；在栅极开口内的界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层(first metal gate layer)；在第一金属栅层中注入掺杂离子；在第一金属栅层上形成第二金属栅层(second metal gate layer)以填充栅极开口；以及进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
在该方法中，一方面，在高K栅介质的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。该方法获得的半导体器件的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1至6示意性地示出根据本发明的方法的一个实施例在制造P型MOSFET的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中，无论是否显示在不同实施例中，类似的部件采用相同或类似的附图标记表示。在各个附图中，为了清楚起见，附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
在本申请中，术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者，并且采用相同的一个附图标记标示。术语“P型掺杂剂”是指用于P型MOSFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例，参照图1至6说明按照后栅工艺制造P型MOSFET的方法。
在图1中所示的半导体结构已经完成了后栅工艺器件的一部分。在半导体衬底101(例如，硅衬底)上包括由浅沟槽隔离(未示出)限定的P型MOSFET的有源区。在P型MOSFET的有源区，在半导体衬底101上形成包括假栅介质102(例如，氧化硅)和假栅导体103(例如，多晶硅，或α-Si)的假栅叠层。该假栅叠层由栅极侧墙104(例如，氮化硅)围绕。在半导体衬底101中形成了P型MOSFET的源/漏区105。源/漏区105位于假栅叠层的两侧，并且可以包括至少部分地延伸至假栅介质102下方的延伸区。在源/漏区105的表面还形成了硅化区106(例如，硅化镍，硅化镍铂)，以减小源/漏区105的串联电阻和接触电阻。
该半导体结构还包括覆盖有源区的层间介质层107(例如，氮化硅，或氧化硅)。通过化学机械抛光(CMP)，平整层间介质层107的表面并暴露假栅导体103的顶部表面。该层间介质层107不仅在随后的步骤中保护有源区，而且如下所述将用作硬掩模。
然后，以层间介质层107作为硬掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅导体103，并且进一步选择性地去除假栅介质102，如图2所示。该蚀刻步骤在P型MOSFET的有源区中形成栅极开口，并暴露半导体衬底101的表面。
然后，通过化学氧化或附加的热氧化，在半导体衬底101的暴露表面上形成界面氧化物层108(例如，氧化硅)。通过已知的沉积工艺，如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、溅射等，在半导体结构的表面上依次形成高K介质层109和第一金属栅层110，如图3所示。高K介质层109和第一金属栅层110位于栅极开口内的底部和侧壁上，但未填满栅极开口。
高K介质层109由介电常数大于SiO2的合适材料构成，例如可以由选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种构成。第一金属栅层110由可以用于形成金属栅的合适材料构成，例如可以由选自TiN、TaN、MoN、WN、TaC、TaCN及其任意组合的一种构成。在一个实例中，高K介质层109例如是厚度约1.5-5nm的HfO2层，第一金属栅层110例如是厚度约2-10nm的TiN层。
优选地，在形成高K介质层109和形成第一金属栅层110之间还可以包括高K介质层109沉积后退火(post deposition annealing)，以改善高K介质层质量，这有利于随后形成的第一金属栅层110获得均匀的厚度。
然后，在P型MOSFET的有源区进行离子注入，在第一金属栅层110中注入P型掺杂剂，如图4所示。用于金属栅的P型掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量，使得注入的掺杂离子仅仅分布在第一金属栅层110中，而没有进入高K介质层109，并使得第一金属栅层110具有合适的掺杂深度和浓度，以获得期望的阈值电压。在一个实施例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。
然后，通过上述已知的沉积方法，在第一金属栅层110上形成覆盖的第二金属栅层111，如图5所示。第二金属栅层111的厚度足够厚从而在CMP后至少可以填满栅极开口。第二金属栅层111由可以用于形成金属栅的低电阻率的合适材料构成。优选地，第二金属栅层111可以由选自W、Ti、TiAl、Al、Mo、Ta、TiN、TaN、WN及其任意组合的一种构成。
然后，以层间介质层107作为停止层，例如通过化学机械抛光平整半导体结构的表面。该平整步骤从上至下依次去除第二金属栅层111、第一金属栅层110和高K介质层109和界面氧化层108位于栅极开口外部的部分，使得第二金属栅层111、第一金属栅层110、高K介质层109和界面氧化层108位于栅极开口内部的剩余部分作为P型MOSFET的栅叠层，如图6所示。
在完成公知的接触和互联后，上述半导体结构在惰性气氛(例如N2)或弱还原性气氛(例如N2和H2的混合气氛)中进行退火。在一个实例中，在炉中进行退火，退火温度约为350℃-450℃，退火时间约为20-90分钟。退火驱使注入的掺杂离子扩散并聚积在高K栅介质层109的上界面和下界面处，并且进一步在高K栅介质层109的下界面处通过界面反应形成电偶极子。这里，高K栅介质层109的上界面是指其与上方的第一金属栅层110之间的界面，高K栅介质层109的下界面是指其与下方的界面氧化物层108之间的界面。
该退火改变了掺杂离子的分布。一方面，在高K栅介质层109的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质层109的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。
在上文中并未描述MOSFET的所有细节，例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的MOSFET中，因此对此不再详述。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (14)

1.一种P型MOSFET的制造方法，所述方法包括：
在半导体衬底上形成MOSFET的一部分，所述MOSFET的所述部分包括位于半导体衬底中的源/漏区、在半导体衬底上方位于源/漏区之间的假栅叠层、以及围绕假栅叠层的栅极侧墙；
去除所述MOSFET的假栅叠层以形成栅极开口，该栅极开口暴露半导体衬底的表面；
在半导体的暴露表面上形成界面氧化物层；
在栅极开口内的界面氧化物层上形成高K栅介质；
在高K栅介质上形成第一金属栅层；
在第一金属栅层中注入掺杂离子；
在第一金属栅层上形成第二金属栅层以填充栅极开口；以及
进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
2.根据权利要求1所述的方法，其中高K栅介质由选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种构成。
3.根据权利要求1所述的方法，其中高K栅介质的厚度约为1.5-5nm。
4.根据权利要求1所述的方法，其中采用原子层沉积、物理汽相沉积或金属有机化学汽相沉积形成高K栅介质。
5.根据权利要求4所述的方法，其中在形成高K栅介质之后，还包括附加的退火以改善高K栅介质的质量。
6.根据权利要求1所述的方法，其中第一金属栅层由选自TiN、TaN、MoN、WN、TaC、TaCN及其任意组合的一种构成。
7.根据权利要求1所述的方法，其中第一金属栅层的厚度约为2-10nm。
8.根据权利要求1所述的方法，其中第二金属栅层由选自W、Ti、TiAl、Al、Mo、Ta、TiN、TaN、WN及其任意组合的一种构成。
9.根据权利要求1所述的方法，其中在第一金属栅层中注入掺杂离子的步骤中，根据期望的阈值电压控制离子注入的能量和剂量，并且使得掺杂离子仅仅分布在第一金属栅层中。
10.根据权利要求9所述的方法，其中离子注入的能量约为0.2KeV-30KeV。
11.根据权利要求9所述的方法，其中离子注入的剂量约为1E13-1E15cm-2。
12.根据权利要求1所述的方法，其中在第一金属栅层中注入掺杂离子的步骤采用可以增加有效功函数的掺杂剂。
13.根据权利要求12所述的方法，其中掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
14.根据权利要求1所述的方法，其中在惰性气氛或弱还原性气氛中执行退火，退火温度约为350℃-450℃，退火时间约为20-90分钟。
CN201210506496.0A 2012-11-30 2012-11-30 P型mosfet的制造方法 Active CN103854983B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201210506496.0A CN103854983B (zh) 2012-11-30 2012-11-30 P型mosfet的制造方法
US14/004,802 US9196706B2 (en) 2012-11-30 2012-12-07 Method for manufacturing P-type MOSFET
PCT/CN2012/086172 WO2014082341A1 (zh) 2012-11-30 2012-12-07 P型mosfet的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210506496.0A CN103854983B (zh) 2012-11-30 2012-11-30 P型mosfet的制造方法

Publications (2)

Publication Number Publication Date
CN103854983A true CN103854983A (zh) 2014-06-11
CN103854983B CN103854983B (zh) 2018-05-22

Family

ID=50827110

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210506496.0A Active CN103854983B (zh) 2012-11-30 2012-11-30 P型mosfet的制造方法

Country Status (3)

Country Link
US (1) US9196706B2 (zh)
CN (1) CN103854983B (zh)
WO (1) WO2014082341A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158966A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 具有不齐平的栅极结构的半导体结构及其形成方法
CN107749398A (zh) * 2017-11-09 2018-03-02 中国科学院微电子研究所 P型mosfet的制作方法
CN108039368A (zh) * 2017-11-09 2018-05-15 中国科学院微电子研究所 N型mosfet的制作方法
CN113644112A (zh) * 2020-05-11 2021-11-12 北京华碳元芯电子科技有限责任公司 晶体管及制作方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103855006A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件的制造方法
US9812366B2 (en) * 2014-08-15 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of tuning work function for a semiconductor device
US9583400B1 (en) * 2016-01-15 2017-02-28 International Business Machines Corporation Gate stack with tunable work function
CN113644109B (zh) * 2020-05-11 2023-06-09 北京华碳元芯电子科技有限责任公司 晶体管及其制备方法
DE102020130401A1 (de) 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dipolig-gefertigtes high-k-gate-dielektrikum und verfahren zu dessen bildung desselben
US11784052B2 (en) * 2020-05-28 2023-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Dipole-engineered high-k gate dielectric and method forming same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110079828A1 (en) * 2009-10-05 2011-04-07 International Business Machines Corporation Metal gate fet having reduced threshold voltage roll-off
CN102110689A (zh) * 2009-12-29 2011-06-29 中国科学院微电子研究所 一种半导体器件及其制造方法
CN102110650A (zh) * 2009-12-29 2011-06-29 中国科学院微电子研究所 一种半导体器件及其制造方法
CN102280376A (zh) * 2010-06-08 2011-12-14 中国科学院微电子研究所 一种用于cmos器件的双金属栅双高介质的集成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7704844B2 (en) * 2007-10-04 2010-04-27 International Business Machines Corporation High performance MOSFET
JP5235784B2 (ja) * 2009-05-25 2013-07-10 パナソニック株式会社 半導体装置
US20130032886A1 (en) * 2011-08-01 2013-02-07 International Business Machines Corporation Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET
US8492852B2 (en) * 2010-06-02 2013-07-23 International Business Machines Corporation Interface structure for channel mobility improvement in high-k metal gate stack
US8865551B2 (en) * 2012-06-28 2014-10-21 International Business Machines Corporation Reducing the inversion oxide thickness of a high-k stack fabricated on high mobility semiconductor material

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110079828A1 (en) * 2009-10-05 2011-04-07 International Business Machines Corporation Metal gate fet having reduced threshold voltage roll-off
CN102110689A (zh) * 2009-12-29 2011-06-29 中国科学院微电子研究所 一种半导体器件及其制造方法
CN102110650A (zh) * 2009-12-29 2011-06-29 中国科学院微电子研究所 一种半导体器件及其制造方法
CN102280376A (zh) * 2010-06-08 2011-12-14 中国科学院微电子研究所 一种用于cmos器件的双金属栅双高介质的集成方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
施敏: "《半导体制造工艺基础》", 30 April 2007 *
潘桂忠: "《MOS集成电路工艺与制造技术》", 30 June 2012 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158966A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 具有不齐平的栅极结构的半导体结构及其形成方法
CN106158966B (zh) * 2015-05-15 2019-07-05 台湾积体电路制造股份有限公司 具有不齐平的栅极结构的半导体结构及其形成方法
CN107749398A (zh) * 2017-11-09 2018-03-02 中国科学院微电子研究所 P型mosfet的制作方法
CN108039368A (zh) * 2017-11-09 2018-05-15 中国科学院微电子研究所 N型mosfet的制作方法
CN113644112A (zh) * 2020-05-11 2021-11-12 北京华碳元芯电子科技有限责任公司 晶体管及制作方法

Also Published As

Publication number Publication date
US20150295067A1 (en) 2015-10-15
WO2014082341A1 (zh) 2014-06-05
CN103854983B (zh) 2018-05-22
US9196706B2 (en) 2015-11-24

Similar Documents

Publication Publication Date Title
CN103855006A (zh) 半导体器件的制造方法
CN103854983B (zh) P型mosfet的制造方法
CN103854982B (zh) 半导体器件的制造方法
US6921691B1 (en) Transistor with dopant-bearing metal in source and drain
CN103855093B (zh) 半导体器件及其制造方法
CN107958872A (zh) 半导体器件及其形成方法
CN103855012A (zh) N型mosfet的制造方法
TWI469262B (zh) 半導體裝置之製造方法及半導體裝置
US9252059B2 (en) Method for manufacturing semiconductor device
CN102437118B (zh) 具有金属栅极的晶体管的制作方法
CN103855014B (zh) P型mosfet及其制造方法
US9934975B2 (en) N-type MOSFET and method for manufacturing the same
CN103094214B (zh) 制作半导体器件的方法
CN103855094A (zh) 半导体器件及其制造方法
US9029225B2 (en) Method for manufacturing N-type MOSFET
CN103855007A (zh) P型mosfet的制造方法
CN103855013A (zh) N型mosfet的制造方法
CN107910298A (zh) 半导体cmos器件的制作方法
CN104979289B (zh) 一种半导体器件及其制作方法
CN110690109B (zh) 半导体器件及其形成方法
CN107591367A (zh) 半导体结构的制造方法
TWI509702B (zh) 具有金屬閘極之電晶體及其製作方法
CN107749398A (zh) P型mosfet的制作方法
CN108807268A (zh) 半导体结构及其形成方法
CN106024631A (zh) 一种降低mos晶体管栅诱导漏极泄漏电流的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant