CN103854982B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN103854982B
CN103854982B CN201210505744.XA CN201210505744A CN103854982B CN 103854982 B CN103854982 B CN 103854982B CN 201210505744 A CN201210505744 A CN 201210505744A CN 103854982 B CN103854982 B CN 103854982B
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layer
gate
gate layer
metal gate
metal
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CN103854982A (zh
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徐秋霞
朱慧珑
许高博
周华杰
陈大鹏
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210505744.XA priority Critical patent/CN103854982B/zh
Priority to US14/355,919 priority patent/US9136181B2/en
Priority to PCT/CN2012/086126 priority patent/WO2014082334A1/zh
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    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract

公开了一种半导体器件的制造方法，该方法包括：在半导体衬底上限定有源区；在半导体衬底的表面上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；在第一金属栅层上形成假栅层；将假栅层、第一金属栅层、高K栅介质和界面氧化物层图案化为栅叠层；形成围绕栅叠层的栅极侧墙；形成源/漏区，去除假栅层以形成栅极开口；在第一金属栅层中注入掺杂离子；在第一金属栅层上形成第二金属栅层以填充栅极开口；以及进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体技术领域，具体地涉及包括金属栅和高K栅介质的半导体器件的制造方法。
背景技术
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小导致栅电流泄漏的严重问题。高K栅介质的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度，因而可以降低栅隧穿漏电流。然而，传统的多晶硅栅与高K栅介质不兼容。金属栅与高K栅介质一起使用不仅可以避免多晶硅栅的耗尽效应，减小栅电阻，还可以避免硼穿透，提高器件的可靠性。因此，金属栅和高K栅介质的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质的集成仍然面临许多挑战，如热稳定性问题、界面态问题。特别是由于费米钉扎效应，采用金属栅和高K栅介质的MOSFET难以获得适当低的阈值电压。
在集成N型和P型MOSFET的CMOS应用中，为了获得合适的阈值电压，N型MOSFET的有效功函数应当在Si的导带底附近(4.1eV左右)，P型MOSFET的有效功函数应当在Si的价带顶附近(5.2eV左右)。可以针对N型MOSFET和P型MOSFET分别选择不同的金属栅和高K栅介质的组合以实现所需的阈值电压。结果，需要在一个芯片上形成双金属栅和双高K栅介质。在半导体器件的制造期间，分别针对N型和P型MOSFET的金属栅和高K栅介质执行各自的光刻和蚀刻步骤。因此，用于制造包括双金属栅和双栅介质的半导体器件的方法工艺复杂，不适合批量生产，这进一步导致成本高昂。
发明内容
本发明的目的是提供一种改进的制造半导体器件的方法，其中可以在制造过程调节半导体器件的有效功函数。
根据本发明，提供一种半导体器件的制造方法，所述方法包括：在半导体衬底上限定有源区；在半导体衬底的表面上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；在第一金属栅层上形成假栅层；将假栅层、第一金属栅层、高K栅介质和界面氧化物层图案化为栅叠层；形成围绕栅叠层的栅极侧墙；形成源/漏区，去除假栅层以形成栅极开口；在第一金属栅层中注入掺杂离子；在第一金属栅层上形成第二金属栅层以填充栅极开口；以及进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。在优选的实施例中，所述半导体器件包括在一个半导体衬底上形成的N型MOSFET和P型MOSFET，并且在N型MOSFET的第一金属栅层注入用于减小有效功函数的掺杂剂，在P型MOSFET的第一金属栅层中注入于增加有效功函数的掺杂剂。
在该方法中，一方面，在高K栅介质与第一金属栅层之间的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质的与界面氧化物之间的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。该方法获得的半导体器件的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。针对两种类型的MOSFET选择不同的掺杂剂，可以减小或增加有效功函数。在CMOS器件中，仅仅通过改变掺杂剂，就可以分别调节两种类型的MOSFET的阈值电压，而不需要分别使用金属栅和栅介质的不同组合。因此，该方法可以省去相应的沉积步骤和掩模及刻蚀步骤，从而实现了简化工艺且易于大量生产。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1至11示意性地示出根据本发明的方法的一个实施例在制造半导体器件的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中，无论是否显示在不同实施例中，类似的部件采用相同或类似的附图标记表示。在各个附图中，为了清楚起见，附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
在本申请中，术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者，并且采用相同的一个附图标记标示。术语“N型掺杂剂”是指用于N型MOSFET的可以减小有效功函数的掺杂剂。术语“P型掺杂剂”是指用于P型MOSFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例，参照图1至11说明制造半导体器件的方法。该半导体器件是包括在一个半导体衬底上形成的NMOSFET和PMOSFET的CMOS器件。
在图1中所示的半导体结构已经完成了一部分CMOS工艺。在半导体衬底101(例如，硅衬底)上包括由浅沟槽隔离102分隔开的分别用于N型MOSFET和P型MOSFET的有源区。
通过化学氧化或附加的热氧化，在半导体衬底101的暴露表面上形成界面氧化物层103(例如，氧化硅)。在一个实例中，通过在约600-900℃的温度下进行20-120s的快速热氧化形成界面氧化物层103。在另一个实例中，通过含臭氧(O3)的水溶液中进行化学氧化形成界面氧化物层103。
优选地，在形成界面氧化物层103之前，对半导体衬底101的表面进行清洗。该清洗包括首先进行常规的清洗，然后浸入包括氢氟酸、异丙醇和水的混合溶液中，然后采用去离子水冲洗，最后甩干。在一个实例中，该混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5％∶0.01-0.10％∶1，并且浸入时间约为1-10分钟。该清洗可以获得半导体衬底101的洁净的表面，抑制硅表面自然氧化物的生成和颗粒污染，从而有利于形成高质量的界面氧化物层103。
然后，通过已知的沉积工艺，如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、溅射等，在半导体结构的表面上依次形成高K栅介质104、第一金属栅层105、阻挡层106和假栅层107，如图2所示。
高K栅介质104由介电常数大于SiO2的合适材料构成，例如可以是选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种。第一金属栅层105由可以用于形成金属栅的合适材料构成，例如可以是选自TiN、TaN、MoN、WN、TaC和TaCN的一种。阻挡层106由可以阻挡假栅层107和第一金属栅层105之间的反应和互扩散的材料组成，例如可以是选自TaN、A1N和TiN的一种。假栅层107可以由多晶硅层或非晶硅层(α-Si)组成。应当注意，阻挡层106是可选的，如果不会发生假栅层107和第一金属栅层105之间的反应和互扩散，则不需要包括该层。在一个实例中，高K栅介质104例如是厚度约1.5-5nm的HfO2层，第一金属栅层105例如是厚度约2-30nm的TiN层，阻挡层106例如是厚度约为3-8nm的TaN层，假栅层107例如是厚度约为30-120nm的多晶硅层。
优选地，在形成高K栅介质104和形成第一金属栅层105之间还可以包括高K栅介质沉积后退火(post deposition annealing)，以改善高K栅介质的质量，这有利于随后形成的第一金属栅层105获得均匀的厚度。在一个实例中，通过在500-1000℃的温度进行5-100s的快速热退火作为沉积后退火。
然后，采用光致抗蚀剂掩模(未示出)或硬掩模(未示出)进行图案化以形成栅叠层。在图案化中，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅层107、阻挡层106、第一金属栅层105、高K栅介质104和界面氧化物层103的暴露部分，分别形成N型MOSFET和P型MOSFET的栅叠层，如图3所示。在图中示出N型MOSFET的栅叠层包括假栅层107a、阻挡层106a、第一金属栅层105a、高K栅介质104a和界面氧化物层103a，P型MOSFET的栅叠层包括假栅层107b、阻挡层106b、第一金属栅层105b、高K栅介质104b和界面氧化物层103b。
在用于形成栅叠层的图案化步骤中，可以针对不同的层采用不同的蚀刻剂。在一个实例中，在干法蚀刻假栅层107时采用基于F的蚀刻气体、基于Cl的蚀刻气体或者基于HBr/Cl2的蚀刻气体，在干法蚀刻第一金属栅层105/高K栅介质104时采用基于BCL3/Cl2的蚀刻气体。优选地，在前述蚀刻气体中还可以添加Ar和/或O2以改善蚀刻效果。要求栅叠层的刻蚀具有陡直和连续的剖面，高的各向异性，对硅衬底有高的刻蚀选择比，不损伤硅衬底。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成例如10-50nm的氮化硅层，然后对氮化硅层进行各向异性蚀刻，从而在N型MOSFET的有源区中形成围绕栅叠层的侧墙108a，在P型MOSFET的有源区中形成围绕栅叠层的侧墙108b，如图4所示。
然后，采用栅叠层及其侧墙作为硬掩模进行源/漏离子注入，并进行激活退火，从而在半导体衬底101中形成N型MOSFET的源/漏区109a以及P型MOSFET的源/漏区109b，如图5所示。N型MOSFET的源/漏区109a位于栅叠层的两侧，并且可以包括至少部分地延伸至高K栅介质104a下方的延伸区。P型MOSFET的源/漏区109b位于栅叠层的两侧，并且可以包括至少部分地延伸至高K栅介质104b下方的延伸区。由于假栅层107a和107b的保护，源/漏离子注入的掺杂剂没有进入第一金属栅层105a和105b中，这有利于在随后的金属栅注入中调节有效功函数。
可以采用快速热退火(RTA)、瞬态退火(spike anneal)、激光退火(laser anneal)、微波退火(microwave anneal)进行源/漏激活退火。退火的温度约为950-1100℃，时间约为2ms-30s。
然后，在源/漏区109a的表面形成硅化区110a(例如，硅化镍，硅化镍铂)，在源/漏区109b的表面形成硅化区110b(例如，硅化镍，硅化镍铂)，如图6所示。硅化区可以减小源/漏区的串联电阻和接触电阻。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成覆盖有源区的层间介质层111(例如，氮化硅、氧化硅)。通过化学机械抛光(CMP)，平整层间介质层111的表面并暴露假栅层107a和107b的顶部，如图7所示。
然后，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，相对于层间介质层111选择性地去除假栅层107a和107b，以形成栅极开口，如图8所示。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模PR1，以遮挡P型MOSFET的有源区并暴露N型MOSFET的有源区。采用该光致抗蚀剂掩模PR1穿过栅极开口进行离子注入，在N型MOSFET的有源区的第一金属栅层105a中注入N型掺杂剂，如图8所示。用于金属栅的N型掺杂剂可以是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。控制离子注入的能量和剂量，使得注入的掺杂离子仅仅分布在第一金属栅层105a中，而没有进入高K栅介质104a，并且控制离子注入的能量和剂量，使得第一金属栅层105a具有合适的掺杂深度和浓度以获得期望的阈值电压。在一个实施例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模PR1。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模PR2，以遮挡N型MOSFET的有源区并暴露P型MOSFET的有源区。采用该光致抗蚀剂掩模PR2穿过栅极开口进行离子注入，在P型MOSFET的有源区的第一金属栅层105b中注入P型掺杂剂，如图10所示。用于金属栅的P型掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量，使得注入的掺杂离子仅仅分布在第一金属栅层105b中，而没有进入高K栅介质104b。并且使得第一金属栅层105b具有合适的掺杂深度和浓度，以获得期望的阈值电压。在一个实施例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模PR2。
然后通过上述已知的沉积工艺，在半导体结构的表面上形成第二金属栅层。以层间介质层111作为停止层进行化学机械抛光(CMP)，以去除第二金属栅层位于栅极开口外的部分，而仅仅保留位于栅极开口内的部分，如图11所示。第二金属栅层可以由与第一金属栅层相同或不同的材料组成，例如可以是选自W、Ti、TiAl、Al、Mo、Ta、TiN、TaN、WN及其任意组合的一种构成。在一个实例中，第二金属栅层例如是厚度约30-80nm的W层。在图中示出N型MOSFET的栅叠层包括第二金属栅层112a、阻挡层106a、第一金属栅层105a、高K栅介质104a和界面氧化物层103a，P型MOSFET的栅叠层包括第二金属栅层112b、阻挡层106b、第一金属栅层105b、高K栅介质104b和界面氧化物层103b。尽管N型MOSFET和P型MOSFET的栅叠层由相同的层形成，但两者的金属栅中包含相反类型的掺杂离子对有效功函数起到相反的调节作用。
在完成公知的接触和互联后，上述半导体结构在惰性气氛(例如N2)或弱还原性气氛(例如N2和H2的混合气氛)中进行退火。在一个实例中，在炉中进行退火，退火温度约为350℃-450℃，退火时间约为20-90分钟。退火驱使注入的掺杂离子扩散并聚积在高K栅介质104a和104b的上界面和下界面处，并且进一步在高K栅介质104a和104b的下界面处通过界面反应形成电偶极子。这里，高K栅介质104a和104b的上界面是指其与上方的第一金属栅层105a和105b之间的界面，高K栅介质104a和104b的下界面是指其与下方的界面氧化物层103a和103b之间的界面。
该退火改变了掺杂离子的分布。一方面，在高K栅介质104a和104b的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质104a和104b的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。
在上文中并未描述MOSFET的所有细节，例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的MOSFET中，因此对此不再详述。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (20)

1.一种半导体器件的制造方法，所述方法包括：
在半导体衬底上限定有源区；
在半导体衬底的表面上形成界面氧化物层；
在界面氧化物层上形成高K栅介质；
在高K栅介质上形成第一金属栅层；
在第一金属栅层上形成假栅层；
将假栅层、第一金属栅层、高K栅介质和界面氧化物层图案化为栅叠层；
形成围绕栅叠层的栅极侧墙；
形成源/漏区，
去除假栅层以形成栅极开口；
在第一金属栅层中注入掺杂离子；
在第一金属栅层上形成第二金属栅层以填充栅极开口；以及
进行退火以使掺杂离子扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
2.根据权利要求1所述的方法，其中高K栅介质由选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种构成。
3.根据权利要求1所述的方法，其中高K栅介质的厚度为1.5-5nm。
4.根据权利要求1所述的方法，其中采用原子层沉积、物理汽相沉积或金属有机化学汽相沉积形成高K栅介质。
5.根据权利要求4所述的方法，其中在形成高K栅介质之后，还包括附加的退火以改善高K栅介质的质量。
6.根据权利要求1所述的方法，其中第一金属栅层由选自TiN、TaN、MoN、WN、TaC、TaCN及其任意组合的一种构成。
7.根据权利要求1所述的方法，其中第一金属栅层的厚度为2-30nm。
8.根据权利要求1所述的方法，其中第二金属栅层由选自W、Ti、TiAl、Al、Mo、Ta、TiN、TaN、WN及其任意组合的一种构成。
9.根据权利要求1所述的方法，其中在第一金属栅层中注入掺杂离子的步骤中，根据期望的阈值电压控制离子注入的能量和剂量，并且使得掺杂离子仅仅分布在第一金属栅层中。
10.根据权利要求9所述的方法，其中离子注入的能量为0.2KeV-30KeV。
11.根据权利要求9所述的方法，其中离子注入的剂量为1E13-1E15cm-2。
12.根据权利要求1所述的方法，其中所述半导体器件包括在一个半导体衬底上形成的N型MOSFET和P型MOSFET，并且在第一金属栅层中注入掺杂离子的步骤包括：
在遮挡P型MOSFET的情形下，采用第一掺杂剂注入对N型MOSFET的第一金属栅层进行离子注入；以及
在遮挡N型MOSFET的情形下，采用第二掺杂剂注入对P型MOSFET的第一金属栅层进行离子注入。
13.根据权利要求12所述的方法，其中第一掺杂剂是可以减小有效功函数的掺杂剂。
14.根据权利要求13所述的方法，其中第一掺杂剂是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。
15.根据权利要求12所述的方法，其中第二掺杂剂是可以增加有效功函数的掺杂剂。
16.根据权利要求15所述的方法，其中第二掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
17.根据权利要求1所述的方法，其中在惰性气氛或弱还原性气氛中执行退火，退火温度为350℃-450℃，退火时间为20-90分钟。
18.根据权利要求1所述的方法，其中假栅层由多晶硅或非晶硅组成。
19.根据权利要求1所述的方法，其中在第一金属栅层注入掺杂剂的步骤和形成假栅层的步骤之间还包括形成阻挡层，使得栅叠层还包括该阻挡层。
20.根据权利要求19所述的方法，其中阻挡层由选自TaN、AlN、TiN及其任意组合的一种构成。
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