CN103681274B - 半导体器件制造方法 - Google Patents
半导体器件制造方法 Download PDFInfo
- Publication number
- CN103681274B CN103681274B CN201210336478.2A CN201210336478A CN103681274B CN 103681274 B CN103681274 B CN 103681274B CN 201210336478 A CN201210336478 A CN 201210336478A CN 103681274 B CN103681274 B CN 103681274B
- Authority
- CN
- China
- Prior art keywords
- layer
- grid
- false
- etching
- gate material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 125000001475 halogen functional group Chemical group 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
本发明提供了一种假栅结构的制造方法。本发明在假栅材料层之上形成了ONO结构和顶层非晶硅层,首先以图案化的顶层非晶硅层为掩膜对ONO结构进行刻蚀,能够精确地控制其尺寸和剖面形貌,使ONO结构成为所期望的假栅材料层的掩膜,并且能够控制ONO各层刻蚀速率和厚度;接着,以ONO结构为掩膜刻蚀假栅材料层,同样实现图形的精确转移,使得假栅关键尺寸和剖面形貌得到精确控制,使得后续形成的金属栅极具有良好的粗糙度,保证了器件的性能及其稳定性。
Description
技术领域
本发明涉及半导体器件制造方法领域,特别地,涉及一种后栅工艺中的假栅制造方法。
背景技术
随着晶体管尺寸的不断缩小,HKMG(高K绝缘层和金属栅极)技术已经成为45nm以下半导体制程的必备技术。HKMG技术中,后栅工艺(Gate Last)方案被众多业内知名半导体企业广泛看好,其中,已有企业(例如美国Intel公司)生产出基于后栅工艺的HKMG产品。所谓后栅工艺,指的是在晶体管制造工艺中,首先形成假栅(dummy gate),然后,进行例如间隙壁(spacer)的沉积和刻蚀,源漏注入等工艺以形成源漏区域,在完成晶体管栅极之外的部件的制造以后,去除假栅,在假栅所在位置形成晶体管栅极。假栅通常为形成于二氧化硅层上的非晶硅或多晶硅假栅,而HKMG技术中最终形成的晶体管栅极为金属栅极。
目前看来,后栅工艺具有一些独特的优势,例如,克服了高温工艺负面影响,尤其是在金属栅材料选择上避开高温限制,另外,后栅工艺有助于大幅提高晶体管沟道应力,对提高PFETs性能尤其有效。但是,现有的后栅工艺面对如下问题还存在困难,例如超细线条(45nm以下)的形成,栅极的关键尺寸(Critical Dimension)和剖面形貌(Profile)的精确控制,硬掩膜结构的剖面形貌和剩余厚度控制,等等。因此,需要一种新的后栅工艺,尤其是假栅形成工艺,来解决上面所述的难题,从而更好地解决晶体管制造过程中的问题,确保晶体管性能。
发明内容
本发明提供一种晶体管后栅工艺中的假栅制造方法,其避免了现有后栅工艺的缺陷。
根据本发明的一个方面,本发明提供一种半导体器件制造方法,其包括如下步骤:
提供半导体衬底,在该半导体衬底上依次形成假栅栅极氧化层和假栅材料层;
在所述假栅材料层之上形成ONO结构,其从下至上包括第一氧化物层,氮化物层,第二氧化物层;
在所述ONO结构之上形成顶层非晶硅层;
在所述顶层非晶硅层之上形成图案化光刻胶层;
以所述图案化光刻胶层为掩膜,对所述顶层非晶硅层进行刻蚀,刻蚀停止在所述ONO结构的最上层;
以所述图案化光刻胶层以及剩余的所述顶层非晶硅层为掩膜,对所述ONO结构进行刻蚀,刻蚀停止在所述假栅材料层的上表面上;
去除所述图案化光刻胶层;
对所述假栅材料层进行刻蚀,刻蚀停止在所述假栅栅极氧化层的上表面上,形成所需要的假栅结构。
根据本发明的一个方面,所述假栅材料层的材料为非晶硅,厚度为900-1200埃;所述假栅栅极氧化层的材料为二氧化硅,厚度为20-40埃。
根据本发明的一个方面,所述第一氧化物层为SiO2,其厚度为100埃,所述氮化物层为Si3N4,其厚度为200埃,所述第二氧化物层为SiO2,其厚度为500-800埃。
根据本发明的一个方面,对所述ONO结构进行刻蚀,分为三个不同阶段,分别刻蚀所述第二氧化物层、所述氮化物层和所述第一氧化物层。
根据本发明的一个方面,所述顶层非晶硅层的厚度为400-600埃。
根据本发明的一个方面,对所述假栅材料层进行刻蚀具体包括:以剩余的所述顶层非晶硅层和所述ONO结构为掩膜,对所述假栅材料层进行刻蚀,刻蚀停止在所述假栅栅极氧化层的上表面上,同时,剩余的所述顶层非晶硅层也在该步骤中被完全除去。
根据本发明的一个方面,在形成所述假栅结构之后,依次进行如下步骤:
栅极间隙壁的沉积和刻蚀;
自对准地形成LDD区域、Halo结构和源漏区域;
形成源漏区域接触;
形成中间介质层,进行CMP工艺。
根据本发明的一个方面,在形成中间介质层,进行CMP工艺之后,去除所述假栅以及所述假栅下方的所述假栅栅极氧化层,以在所述中间介质层中形成栅极凹槽;然后,在所述栅极凹槽中依次沉积高K栅绝缘材料和金属栅极材料,并进行CMP工艺,从而形成了高K栅绝缘层和金属栅极,完成HKMG工艺的制造过程。
本发明的优点在于:本发明在假栅材料层之上形成了ONO结构和顶层非晶硅层,首先,以图案化的顶层非晶硅层为掩膜对ONO结构进行刻蚀,能够精确地控制其尺寸和剖面形貌,使ONO结构成为所期望的假栅材料层的掩膜,并且能够控制ONO各层最终厚度;接着,以ONO结构为掩膜刻蚀假栅材料层,同样实现图形的精确转移,使得假栅关键尺寸和剖面形貌得到精确控制,使得后续形成的金属栅极具有良好的粗糙度,有利于之后间隙壁沉积和刻蚀,以及硅化物形成、CMP等工艺的顺利进行,保证了器件的性能及其稳定性。另外,本发明的技术方案适用于亚45nm的技术带,不仅适合于工厂的大规模生产,也适合于实验室的先导工艺开发,通过部分优化,具备向更先进制造技术升级转移的能力。
附图说明
图1-8本发明提供的半导体器件制造方法流程示意图。
具体实施方式
以下,通过附图中示出的具体实施例来描述本发明。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
本发明提供一种半导体器件制造方法,特别地涉及后栅工艺中的假栅制造方法,其克服了现有后栅工艺中的一些难题。下面,参见附图1-8,将详细描述本发明提供的半导体器件制造方法。
首先,参见附图1,在半导体衬底10上依次形成假栅栅极氧化层11和假栅材料层12。其中,本实施例中采用了单晶硅衬底,可选地,也可采用锗衬底或者其他合适的半导体衬底。假栅栅极氧化层11可以通过热氧化方式形成,材料可以是SiO2,其厚度优选为20-40埃。假栅材料层12优选为非晶硅层,可选地为多晶硅层,采用LPCVD工艺形成,其厚度优选为900-1200埃。
接着,参见附图2,在假栅材料层12之上依次形成第一氧化物层13,氮化物层14,第二氧化物层15,其中,第一氧化物层13,氮化物层14和第二氧化物层15形成了ONO结构。第一氧化物层13可以是SiO2,采用PECVD工艺形成,其厚度为100埃。氮化物层14可以是Si3N4,采用LPCVD工艺形成,其厚度为200埃。第二氧化物层15可以是SiO2,采用PECVD工艺形成,其厚度为500-800埃。
接着,参见附图3,在ONO结构之上,形成顶层非晶硅层16。其中,顶层非晶硅层16采用LPCVD工艺形成,顶层非晶硅层16的厚度为400-600埃。
之后,参见附图4,在顶层非晶硅层16之上形成图案化光刻胶层17。该步骤具体包括:首先全面性涂敷一层光刻胶,然后,采用浸润式光刻或者电子束(eBeam)直写光刻对光刻胶层进行曝光,形成图案化光刻胶层17,图案化光刻胶层17具有小于45nm的线条尺寸。
接着,参见附图5,以图案化光刻胶层17为掩膜,对顶层非晶硅层16进行刻蚀。该步刻蚀工艺可以采用等离子干法刻蚀,刻蚀停止在ONO结构的最上层,也即第二氧化物层15的上表面上。
接着,参见附图6,以图案化光刻胶层17以及剩余的顶层非晶硅层16为掩膜,对ONO结构进行刻蚀。该步刻蚀工艺可以分为三个不同阶段,分别刻蚀第二氧化物层15、氮化物层14和第一氧化物层13,刻蚀最终停止在假栅材料层12的上表面上。
接着,参见附图7,去除图案化光刻胶层17。采用湿法清洗的方式,例如SPM/APM(SPM,H2SO4,H2O2和H2O的混合物;APM,NH4OH,H2O2和H2O的混合物),将剩余的图案化光刻胶层17清洗除去。
接着,参见附图8,对假栅材料层12进行刻蚀,停止在假栅栅极氧化层11的上表面上。该步刻蚀以剩余的顶层非晶硅层16和ONO结构为掩膜,对假栅材料层12进行刻蚀,由于顶层非晶硅层16的材料与假栅材料层12的材料相同,例如均为非晶硅,在该步刻蚀中顶层非晶硅层16也会被完全除去,因此,不需要采用额外的后续步骤去除顶层非晶硅层16。通过此步骤刻蚀,即可实现假栅的制造,其中,假栅堆栈包括了假栅材料层12和其上的ONO结构。
在假栅形成之后,可以进行晶体管其余部件的制造,例如,栅极间隙壁(spacer)的沉积和刻蚀,自对准地形成LDD区域、Halo结构、源漏区域,形成源漏接触,形成中间介质层,进行CMP工艺等等。在完成上述部件制造之后,去除假栅以及假栅下方的假栅栅极氧化层,这样,在中间介质层中形成了栅极凹槽,然后,在栅极凹槽中依次沉积高K栅绝缘材料和金属栅极材料,并进行CMP工艺,从而形成了高K栅绝缘层和金属栅极,完成HKMG工艺的制造过程。
至此,已经完全描述了本发明提供的制造方法。本发明在假栅材料层之上形成了ONO结构和顶层非晶硅层,首先以图案化的顶层非晶硅层为掩膜对ONO结构进行刻蚀,能够精确地控制其尺寸和剖面形貌,使ONO结构成为所期望的假栅材料层的掩膜,并且能够控制ONO各层刻蚀速率和厚度;接着,以ONO结构为掩膜刻蚀假栅材料层,同样实现图形的精确转移,使得假栅关键尺寸和剖面形貌得到精确控制,使得后续形成的金属栅极具有良好的粗糙度(Line Edge Roughens,LER),保证了器件的性能及其稳定性,同时,还为后续栅极间隙壁、CMP工艺以及假栅去除等工艺的顺利进行提供了保障。另外,本发明的技术方案适用于亚45nm的技术带,不仅适合于工厂的大规模生产,也适合于实验室的先导工艺开发,通过部分优化,具备向更先进制造技术(如22nm以下技术带)升级转移的能力。
以上参照本发明的实施例对本发明予以了说明。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围,本领域技术人员可以做出多种替换和修改,这些替换和修改都应落在本发明的范围之内。
Claims (7)
1.一种半导体器件制造方法,其特征在于,包括如下步骤:
提供半导体衬底,在该半导体衬底上依次形成假栅栅极氧化层和假栅材料层;
在所述假栅材料层之上形成ONO结构,其从下至上包括第一氧化物层,氮化物层,第二氧化物层;
在所述ONO结构之上形成顶层非晶硅层;
在所述顶层非晶硅层之上形成图案化光刻胶层;
以所述图案化光刻胶层为掩膜,对所述顶层非晶硅层进行刻蚀,刻蚀停止在所述ONO结构的最上层;
以所述图案化光刻胶层以及剩余的所述顶层非晶硅层为掩膜,对所述ONO结构进行刻蚀,刻蚀停止在所述假栅材料层的上表面上;
去除所述图案化光刻胶层;
对所述假栅材料层进行刻蚀,刻蚀停止在所述假栅栅极氧化层的上表面上,形成所需要的假栅结构;
其中,对所述假栅材料层进行刻蚀具体包括:
以剩余的所述顶层非晶硅层和所述ONO结构为掩膜,对所述假栅材料层进行刻蚀,刻蚀停止在所述假栅栅极氧化层的上表面上,同时,剩余的所述顶层非晶硅层也在该步骤中被完全除去。
2.根据权利要求1所述的方法,其特征在于,所述假栅材料层的材料为非晶硅,其厚度为900-1200埃;所述假栅栅极氧化层的材料为二氧化硅,厚度为20-40埃。
3.根据权利要求1所述的方法,其特征在于,所述第一氧化物层为SiO2,其厚度为100埃,所述氮化物层为Si3N4,其厚度为200埃,所述第二氧化物层为SiO2,其厚度为500-800埃。
4.根据权利要求1所述的方法,其特征在于,对所述ONO结构进行刻蚀,分为三个不同阶段,分别刻蚀所述第二氧化物层、所述氮化物层和所述第一氧化物层。
5.根据权利要求1所述的方法,其特征在于,所述顶层非晶硅层的厚度为400-600埃。
6.根据权利要求1所述的方法,其特征在于,在形成所述假栅结构之后,依次进行如下步骤:
栅极间隙壁的沉积和刻蚀;
自对准地形成LDD区域、Halo结构和源漏区域;
形成源漏区域接触;
形成中间介质层,进行CMP工艺。
7.根据权利要求6所述的方法,其特征在于,在形成中间介质层,进行CMP工艺之后,去除所述假栅以及所述假栅下方的所述假栅栅极氧化层,以在所述中间介质层中形成栅极凹槽;然后,在所述栅极凹槽中依次沉积高K栅绝缘材料和金属栅极材料,并进行CMP工艺,从而形成了高K栅绝缘层和金属栅极,完成HKMG工艺的制造过程。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210336478.2A CN103681274B (zh) | 2012-09-12 | 2012-09-12 | 半导体器件制造方法 |
US14/426,690 US9331172B2 (en) | 2012-09-12 | 2012-11-13 | Method for making HKMG dummy gate structure with amorphous/ONO masking structure and procedure |
PCT/CN2012/001537 WO2014040213A1 (zh) | 2012-09-12 | 2012-11-13 | 半导体器件制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210336478.2A CN103681274B (zh) | 2012-09-12 | 2012-09-12 | 半导体器件制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103681274A CN103681274A (zh) | 2014-03-26 |
CN103681274B true CN103681274B (zh) | 2016-12-28 |
Family
ID=50277467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210336478.2A Active CN103681274B (zh) | 2012-09-12 | 2012-09-12 | 半导体器件制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9331172B2 (zh) |
CN (1) | CN103681274B (zh) |
WO (1) | WO2014040213A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103681274B (zh) * | 2012-09-12 | 2016-12-28 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN103854985B (zh) * | 2012-12-03 | 2016-06-29 | 中国科学院微电子研究所 | 一种后栅工艺假栅的制造方法和后栅工艺假栅 |
CN105762071B (zh) * | 2014-12-17 | 2019-06-21 | 中国科学院微电子研究所 | 鳍式场效应晶体管及其鳍的制造方法 |
US20220319940A1 (en) * | 2019-12-13 | 2022-10-06 | Xidian University | Package Structure for Semiconductor Device and Preparation Method Thereof |
CN112382564B (zh) * | 2020-11-02 | 2024-01-19 | 上海华力集成电路制造有限公司 | 栅极的制造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102386085A (zh) * | 2010-09-06 | 2012-03-21 | 中国科学院微电子研究所 | 一种用于后栅工艺的平坦化方法及其器件结构 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5342801A (en) * | 1993-03-08 | 1994-08-30 | National Semiconductor Corporation | Controllable isotropic plasma etching technique for the suppression of stringers in memory cells |
US6037265A (en) * | 1998-02-12 | 2000-03-14 | Applied Materials, Inc. | Etchant gas and a method for etching transistor gates |
US6297092B1 (en) * | 1998-12-02 | 2001-10-02 | Micron Technology, Inc. | Method and structure for an oxide layer overlaying an oxidation-resistant layer |
TW473840B (en) * | 2000-10-06 | 2002-01-21 | Winbond Electronics Corp | Manufacturing method of EEPROM with split-gate structure |
US6897514B2 (en) * | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
US6803315B2 (en) * | 2002-08-05 | 2004-10-12 | International Business Machines Corporation | Method for blocking implants from the gate of an electronic device via planarizing films |
US6781186B1 (en) * | 2003-01-30 | 2004-08-24 | Silicon-Based Technology Corp. | Stack-gate flash cell structure having a high coupling ratio and its contactless flash memory arrays |
US20050118531A1 (en) * | 2003-12-02 | 2005-06-02 | Hsiu-Chun Lee | Method for controlling critical dimension by utilizing resist sidewall protection |
US7344965B2 (en) * | 2003-12-10 | 2008-03-18 | International Business Machines Corporation | Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions |
JP2006332130A (ja) * | 2005-05-23 | 2006-12-07 | Toshiba Corp | 半導体装置の製造方法 |
JP4575320B2 (ja) * | 2006-03-15 | 2010-11-04 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7410854B2 (en) * | 2006-10-05 | 2008-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making FUSI gate and resulting structure |
KR100831571B1 (ko) * | 2006-12-28 | 2008-05-21 | 동부일렉트로닉스 주식회사 | 플래시 소자 및 이의 제조 방법 |
US20090130836A1 (en) * | 2007-11-16 | 2009-05-21 | Jong-Won Sun | Method of fabricating flash cell |
US8008145B2 (en) * | 2008-09-10 | 2011-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-K metal gate structure fabrication method including hard mask |
US7776757B2 (en) * | 2009-01-15 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating high-k metal gate devices |
CN101930979B (zh) * | 2009-06-26 | 2014-07-02 | 中国科学院微电子研究所 | 控制器件阈值电压的CMOSFETs结构及其制造方法 |
US8329515B2 (en) * | 2009-12-28 | 2012-12-11 | Globalfoundries Inc. | eFUSE enablement with thin polysilicon or amorphous-silicon gate-stack for HKMG CMOS |
US8592296B2 (en) * | 2010-06-16 | 2013-11-26 | International Business Machines Corporation | Gate-last fabrication of quarter-gap MGHK FET |
US8334198B2 (en) * | 2011-04-12 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a plurality of gate structures |
CN103531475A (zh) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
CN103681274B (zh) * | 2012-09-12 | 2016-12-28 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN103854982B (zh) * | 2012-11-30 | 2016-09-28 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
CN103855016A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
CN103854985B (zh) * | 2012-12-03 | 2016-06-29 | 中国科学院微电子研究所 | 一种后栅工艺假栅的制造方法和后栅工艺假栅 |
CN103854984B (zh) * | 2012-12-03 | 2017-03-01 | 中国科学院微电子研究所 | 一种后栅工艺假栅的制造方法和后栅工艺假栅 |
US9111863B2 (en) * | 2012-12-03 | 2015-08-18 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process |
US9054220B2 (en) * | 2013-02-08 | 2015-06-09 | Freescale Semiconductor, Inc. | Embedded NVM in a HKMG process |
JP6026914B2 (ja) * | 2013-02-12 | 2016-11-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2012
- 2012-09-12 CN CN201210336478.2A patent/CN103681274B/zh active Active
- 2012-11-13 WO PCT/CN2012/001537 patent/WO2014040213A1/zh active Application Filing
- 2012-11-13 US US14/426,690 patent/US9331172B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102386085A (zh) * | 2010-09-06 | 2012-03-21 | 中国科学院微电子研究所 | 一种用于后栅工艺的平坦化方法及其器件结构 |
Also Published As
Publication number | Publication date |
---|---|
CN103681274A (zh) | 2014-03-26 |
WO2014040213A1 (zh) | 2014-03-20 |
US20150214332A1 (en) | 2015-07-30 |
US9331172B2 (en) | 2016-05-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103177950B (zh) | 制造鳍器件的结构和方法 | |
US9853124B2 (en) | Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers | |
CN103515321B (zh) | 半导体器件的侧墙形成方法 | |
CN103681274B (zh) | 半导体器件制造方法 | |
TWI528462B (zh) | 調整低溫多晶矽電晶體閥值電壓的方法 | |
US20140117447A1 (en) | Dual gate finfet devices | |
CN104821296A (zh) | 半导体器件及其形成方法 | |
CN106952874B (zh) | 多阈值电压鳍式晶体管的形成方法 | |
CN106158725B (zh) | 半导体结构的形成方法 | |
JP2014042008A (ja) | 電界効果半導体デバイスを製造する方法 | |
CN102983098A (zh) | 后栅工艺中电极和连线的制造方法 | |
CN103377928B (zh) | 半导体结构的形成方法、晶体管的形成方法 | |
CN105226022A (zh) | 半导体结构的形成方法 | |
CN107039335A (zh) | 半导体结构的形成方法 | |
CN107045981B (zh) | 半导体结构的形成方法 | |
CN102856207B (zh) | 一种半导体结构及其制造方法 | |
CN106328706B (zh) | 鳍式场效应晶体管的形成方法 | |
CN103187293B (zh) | 半导体器件的制作方法 | |
CN103531476A (zh) | 半导体器件制造方法 | |
CN101800172A (zh) | 一种自对准多晶硅浮栅的制作方法 | |
CN106206306A (zh) | 鳍式场效应晶体管及其形成方法 | |
CN107978526B (zh) | 半导体结构的制造方法 | |
CN107039333B (zh) | 半导体结构的形成方法 | |
CN102856198B (zh) | 一种半导体结构及其制造方法 | |
CN104716042A (zh) | 一种半导体器件的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |