CN103855016A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN103855016A
CN103855016A CN201210507230.8A CN201210507230A CN103855016A CN 103855016 A CN103855016 A CN 103855016A CN 201210507230 A CN201210507230 A CN 201210507230A CN 103855016 A CN103855016 A CN 103855016A
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China
Prior art keywords
layer
metal gate
dielectric layer
gate dielectric
gate
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CN201210507230.8A
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Inventor
徐秋霞
许高博
周华杰
朱慧珑
陈大鹏
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210507230.8A priority Critical patent/CN103855016A/zh
Priority to US14/233,280 priority patent/US9252059B2/en
Priority to PCT/CN2012/086132 priority patent/WO2014082338A1/zh
Publication of CN103855016A publication Critical patent/CN103855016A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种半导体器件的制造方法，该半导体器件包括在一个半导体衬底上形成的两种相反类型的MOSFET，所述方法包括：在半导体衬底上限定各个MOSFET的有源区；在半导体衬底的表面上形成界面氧化物层；在界面氧化物层上形成高K栅介质层；在高K栅介质层上形成金属栅层；在金属栅层中注入掺杂离子；在金属栅层上形成多晶硅层；将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层；形成围绕栅叠层的栅极侧墙；以及形成源/漏区。利用源/漏退火时使得金属栅中的掺杂离子在界面处堆积和生成合适极性的电偶极子，分别实现对不同类型的MOSFET的金属栅有效功函数的调节。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体技术领域，具体地涉及包括金属栅和高K栅介质层的半导体器件的制造方法。
背景技术
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小导致栅电流泄漏的严重问题。高K栅介质层的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度，因而可以降低栅隧穿漏电流。然而，传统的多晶硅栅与高K栅介质层不兼容。金属栅与高K栅介质层一起使用不仅可以避免多晶硅栅的耗尽效应，减小栅电阻，还可以避免硼穿透，提高器件的可靠性。因此，金属栅和高K栅介质层的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质层的集成仍然面临许多挑战，如热稳定性问题、界面态问题。特别是由于费米钉扎效应，采用金属栅和高K栅介质层的MOSFET难以获得适当低的阈值电压。
在集成N型和P型MOSFET的CMOS应用中，为了获得合适的阈值电压，N型MOSFET的有效功函数应当在Si的导带底附近(4.1eV左右)，P型MOSFET的有效功函数应当在Si的价带顶附近(5.2eV左右)。可以针对N型MOSFET和P型MOSFET分别选择不同的金属栅和高K栅介质层的组合以实现所需的阈值电压。结果，需要在一个芯片上形成双金属栅和双高K栅介质层。在半导体器件的制造期间，分别针对N型和P型MOSFET的金属栅和高K栅介质层执行各自的光刻和蚀刻步骤。因此，用于制造包括双金属栅和双栅介质的半导体器件的方法工艺复杂，不适合批量生产，这进一步导致成本高昂。
发明内容
本发明的目的是提供一种改进的制造半导体器件的方法，其中可以在制造过程调节半导体器件的有效功函数。
根据本发明，提供一种半导体器件的制造方法，该半导体器件包括在一个半导体衬底上形成的两种相反类型的MOSFET，所述方法包括：在半导体衬底上限定各个MOSFET的有源区；在半导体衬底的表面上形成界面氧化物层；在界面氧化物层上形成高K栅介质层；在高K栅介质层上形成金属栅层；在金属栅层中注入掺杂离子；在金属栅层上形成多晶硅层；将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层；形成围绕栅叠层的栅极侧墙；以及形成源/漏区，其中，在形成源/漏区的激活退火期间，使得金属栅层中的掺杂离子扩散并聚积在高K栅介质层与金属栅层之间的上界面和高K栅介质层与界面氧化物之间的下界面处，并且在高K栅介质层与界面氧化物之间的下界面处通过界面反应产生电偶极子。
在该方法中，一方面，在高K栅介质层的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质层的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数。该方法获得的半导体器件的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。针对两种类型的MOSFET选择不同的掺杂剂，可以减小或增加有效功函数。在CMOS器件中，仅仅通过改变掺杂剂，就可以分别调节两种类型的MOSFET的阈值电压，而不需要分别使用金属栅和栅介质的不同组合。因此，该方法可以省去相应的沉积步骤和掩模及刻蚀步骤，从而实现了简化工艺且易于大量生产。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1至8示意性地示出根据本发明的方法的一个实施例在制造半导体器件的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中，无论是否显示在不同实施例中，类似的部件采用相同或类似的附图标记表示。在各个附图中，为了清楚起见，附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
在本申请中，术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者，并且采用相同的一个附图标记标示。术语“N型掺杂剂”是指用于N型MOSFET的可以减小有效功函数的掺杂剂。术语“P型掺杂剂”是指用于P型MOSFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例，参照图1至8说明按照先栅工艺制造半导体器件的方法。该半导体器件是包括在一个半导体衬底上形成的NMOSFET和PMOSFET的CMOS器件。
在图1中所示的半导体结构已经完成了先栅工艺的一部分。在半导体衬底101(例如，硅衬底)上包括由浅沟槽隔离102分隔开的分别用于N型MOSFET和P型MOSFET的有源区。
通过化学氧化或附加的热氧化，在半导体衬底101的暴露表面上形成界面氧化物层103(例如，氧化硅)。在一个实例中，通过在约600-900℃的温度下进行20-120s的快速热氧化形成界面氧化物层103。在另一个实例中，通过含臭氧(O3)的水溶液中进行化学氧化形成界面氧化物层103。
优选地，在形成界面氧化物层103之前，对半导体衬底101的表面进行清洗。该清洗包括首先进行常规的清洗，然后浸入包括氢氟酸、异丙醇和水的混合溶液中，然后采用去离子水冲洗，最后甩干。在一个实例中，该混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5％∶0.01-0.10％∶1，并且浸入时间约为1-10分钟。该清洗可以获得半导体衬底101的洁净的表面，抑制硅表面自然氧化物的生成和颗粒污染，从而有利于形成高质量的界面氧化物层103。
然后，通过已知的沉积工艺，如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、、溅射等，在半导体结构的表面上依次形成高K栅介质层104和金属栅层105，如图2所示。
高K栅介质层104由介电常数大于SiO2的合适材料构成，例如可以是选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种。金属栅层105由可以用于形成金属栅的合适材料构成，例如可以是选自TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个实例中，高K栅介质层104例如是厚度约1.5-5nm的HfO2层，金属栅层105例如是厚度约2-30nm的TiN层。
优选地，在形成高K栅介质层104和形成金属栅层105之间还可以包括高K栅介质层沉积后退火(post deposition annealing)，以改善高K栅介质层的质量，这有利于随后形成的金属栅层105获得均匀的厚度。在一个实例中，通过在500-1000℃的温度进行5-100s的快速热退火作为沉积后退火。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模106，以遮挡P型MOSFET的有源区并暴露N型MOSFET的有源区。采用该光致抗蚀剂掩模106进行离子注入，在N型MOSFET的有源区的金属栅层105中注入N型掺杂剂，如图3所示。用于金属栅的N型掺杂剂可以是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。控制离子注入的能量和剂量，使得注入的掺杂离子仅仅分布在金属栅层105中，而没有进入高K栅介质层104，并且控制离子注入的能量和剂量，使得金属栅层105具有合适的掺杂深度和浓度以获得期望的阈值电压。在一个实施例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模106。
然后，通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂掩模107，以遮挡N型MOSFET的有源区并暴露P型MOSFET的有源区。采用该光致抗蚀剂掩模107进行离子注入，在P型MOSFET的有源区的金属栅层105中注入P型掺杂剂，如图4所示。用于金属栅的P型掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量，使得注入的掺杂离子仅仅分布在金属栅层105中，而没有进入高K栅介质层104。并且使得金属栅层105具有合适的掺杂深度和浓度，以获得期望的阈值电压。在一个实施例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。在该注入之后，通过灰化或溶解去除光抗蚀剂掩模107。
然后，通过上述已知的沉积工艺，在半导体结构的表面上依次形成金属阻挡层108和多晶硅层109，如图5所示。金属阻挡层108由可以阻挡多晶硅层109和金属栅层107之间的反应和互扩散的材料组成，例如可以是选自TaN、AlN和TiN的一种。应当注意，金属阻挡层108是可选的，如果不会发生多晶硅层109和金属栅层107之间的反应和互扩散，则不需要包括该层。多晶硅层109掺杂为导电性的。在一个实例中，金属阻挡层108例如是厚度约为3-8nm的TaN层，多晶硅层的厚度约为30-120nm。
然后，采用光致抗蚀剂掩模(未示出)或硬掩模(未示出)进行图案化以形成栅叠层。在图案化中，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除多晶硅层109、阻挡层108、金属栅层105、高K栅介质层104和界面氧化物层103的暴露部分，分别形成N型MOSFET和P型MOSFET的栅叠层，如图6所示。在图中示出N型MOSFET的栅叠层包括多晶硅栅109a、阻挡层108a、金属栅105a、高K栅介质层104a和界面氧化物层103a，P型MOSFET的栅叠层包括多晶硅栅109b、阻挡层108b、金属栅105b、高K栅介质层104b和界面氧化物层103b。尽管N型MOSFET和P型MOSFET的栅叠层由相同的层形成，但两者的金属栅中包含相反类型的掺杂离子对有效功函数起到相反的调节作用。该蚀刻还暴露半导体衬底101的表面。
在用于形成栅叠层的图案化步骤中，可以针对不同的层采用不同的蚀刻剂。在一个实例中，在干法蚀刻多晶硅层109时采用基于F的蚀刻气体、基于Cl的蚀刻气体或者基于HBr/Cl2的蚀刻气体，在干法蚀刻金属栅层105/高K栅介质层104时采用基于BCL3/Cl2的蚀刻气体。优选地，在前述蚀刻气体中还可以添加Ar和/或O2以改善蚀刻效果。要求栅叠层的刻蚀具有陡直和连续的剖面，高的各向异性，对硅衬底有高的刻蚀选择比，不损伤硅衬底。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成例如10-50nm的氮化硅层，然后对氮化硅层进行各向异性蚀刻，从而在N型MOSFET的有源区中形成围绕栅叠层的侧墙110a，在P型MOSFET的有源区中形成围绕栅叠层的侧墙110b。采用栅叠层及其侧墙作为硬掩模进行源/漏离子注入，并进行激活退火，从而在半导体衬底101中形成N型MOSFET的源/漏区111a以及P型MOSFET的源/漏区111b，如图7所示。N型MOSFET的源/漏区111a位于栅叠层的两侧，并且可以包括至少部分地延伸至高K栅介质层104a下方的延伸区。P型MOSFET的源/漏区111b位于栅叠层的两侧，并且可以包括至少部分地延伸至高K栅介质层104b下方的延伸区。
可以采用快速热退火(RTA)、瞬态退火(spike anneal)、激光退火(laser anneal)、微波退火(microwave anneal)进行源/漏激活退火。退火的温度约为950-1100℃，时间约为2ms-30s。在形成源/漏区的激活退火期间，使得金属栅层中注入的掺杂离子扩散并聚积在高K栅介质层与金属栅之间的上界面和高K栅介质层与界面氧化物之间的下界面处，形成堆积。一方面，在高K栅介质层104a和104b的上界面处聚积的掺杂离子改变了金属栅的性质，从而可以有利地调节相应的MOSFET的有效功函数。另一方面，在高K栅介质层104a和104b的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节相应的MOSFET的有效功函数，分别实现对NMOS器件和PMOS器件金属栅有效功函数的调节。
在源/漏区111a和栅区109a的表面还形成了硅化区112a(例如，硅化镍，硅化镍铂)，以减小源/漏区111a和栅区109a的串联电阻和接触电阻。在源/漏区111b和栅区109b的表面还形成了硅化区112b(例如，硅化镍，硅化镍铂)，以减小源/漏区111b和栅区109b的串联电阻和接触电阻。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成覆盖有源区的层间介质层113(例发，氮化硅，氧化硅)。通过化学机械抛光(CMP)，平整层间介质层113的表面并暴露多晶硅栅109a和109b的顶部表面的硅化物，如图8所示。然后进行公知技术的接触和金属化。
在上文中并未描述MOSFET的所有细节，例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的MOSFET中，因此对此不再详述。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (23)

1.一种半导体器件的制造方法，该半导体器件包括在一个半导体衬底上形成的两种相反类型的MOSFET，所述方法包括：
在半导体衬底上限定各个MOSFET的有源区；
在半导体衬底的表面上形成界面氧化物层；
在界面氧化物层上形成高K栅介质层；
在高K栅介质层上形成金属栅层；
在金属栅层中注入掺杂离子；
在金属栅层上形成多晶硅层；
将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层；
形成围绕栅叠层的栅极侧墙；以及
形成源/漏区，
其中，在形成源/漏区的激活退火期间，使得金属栅中的掺杂离子扩散并聚积在高K栅介质层与金属栅层之间的上界面和高K栅介质层与界面氧化物之间的下界面处，并且在高K栅介质层与界面氧化物之间的下界面处通过界面反应产生电偶极子。
2.根据权利要求1所述的方法，其中在限定有源区的步骤和形成界面氧化物的步骤之间，还包括对半导体衬底的表面进行清洗。
3.根据权利要求2所述的方法，其中清洗包括：
在去离子水中进行超声清洗；
浸入包括氢氟酸、异丙醇和水的混合溶液中；
采用去离子水冲洗；以及
甩干。
4.根据权利要求3所述的方法，其中混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5％∶0.01-0.10％∶1。
5.根据权利要求3所述的方法，其中浸入时间约为2-10分钟。
6.根据权利要求1所述的方法，其中在形成高K栅介质层的步骤和形成金属栅层的步骤之间，还包括高K栅介质层沉积后退火以改善高K栅介质层的质量。
7.根据权利要求1所述的方法，其中高K栅介质层由选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种构成。
8.根据权利要求1所述的方法，其中采用原子层沉积、物理汽相沉积或金属有机化学汽相沉积形成高K栅介质层。
9.根据权利要求1所述的方法，其中高K栅介质层的厚度约为1.5-5nm。
10.根据权利要求1所述的方法，其中金属栅层由选自TiN、TaN、MoN、WN、TaC和TaCN的一种构成。
11.根据权利要求1所述的方法，其中金属栅层的厚度约为2-30nm。
12.根据权利要求1所述的方法，其中在金属栅层中注入掺杂离子的步骤中，控制离子注入的能量和剂量使得掺杂离子仅仅分布在金属栅层中，并根据期望的阈值电压控制离子注入的能量和剂量。
13.根据权利要求12所述的方法，其中离子注入的能量约为0.2KeV-30KeV。
14.根据权利要求13所述的方法，其中离子注入的剂量约为1E13-1E15cm-2。
15.根据权利要求1所述的方法，其中两种相反类型的MOSFET包括N型MOSFET和P型MOSFET，并且在金属栅层中注入掺杂离子的步骤包括：
在遮挡P型MOSFET的有源区的情形下，采用第一掺杂剂注入对N型MOSFET的有源区的金属栅层进行离子注入；以及
在遮挡N型MOSFET的有源区的情形下，采用第二掺杂剂注入对P型MOSFET的有源区的金属栅层进行离子注入。
16.根据权利要求15所述的方法，其中第一掺杂剂是可以减小有效功函数的掺杂剂。
17.根据权利要求16所述的方法，其中第一掺杂剂是选自P、As、Sb、La、Er、Dy、Gd、Sc、Yb、Er和Tb的一种。
18.根据权利要求15所述的方法，其中第二掺杂剂是可以增加有效功函数的掺杂剂。
19.根据权利要求18所述的方法，其中第二掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
20.根据权利要求1所述的方法，其中在注入步骤和形成多晶硅层的步骤之间，还包括在金属栅层上形成金属阻挡层，其中金属阻挡层位于金属栅层和随后形成的多晶硅层之间。
21.根据权利要求20所述的方法，其中金属阻挡层是选自TaN、AlN和TiN的一种。
22.根据权利要求1所述的方法，其中高温退火的温度约为950-1100℃，时间约为2ms-30s。
23.根据权利要求1所述的方法，其中采用选自快速热退火、瞬态退火、激光退火和微波退火中的一种进行退火。
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