CN101930979B - 控制器件阈值电压的CMOSFETs结构及其制造方法 - Google Patents
控制器件阈值电压的CMOSFETs结构及其制造方法 Download PDFInfo
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Abstract
本发明公开了一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构及其制造方法。结构包括:硅衬底;在硅衬底上生长的SiO2界面层;在SiO2界面层上沉积的高k栅介质层;在高k栅介质层上沉积的极薄金属层;在极薄金属层结构上沉积的高k栅介质层;在高k栅介质叠层结构上沉积的金属栅层。制造方法是在NMOS和PMOS器件区域的高k栅介质层内部分别沉积极薄金属层,利用该极薄金属层在高k栅介质层内部形成的正或负电荷来调整器件的平带电压,进而控制器件的阈值电压。利用本发明,不仅可以增强CMOS器件中高k栅介质和SiO2界面层间的界面偶极子,而且还可以很好的控制高k栅介质层内部的固定电荷类型和数量,有效地控制器件的阈值电压。
Description
技术领域
本发明涉及纳米工艺CMOS技术中的高k栅介质和金属栅结构技术领域,尤其涉及一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构及其制造方法。
背景技术
22纳米及以下工艺集成电路关键核心技术的应用是集成电路发展的必然趋势,也是国际上主要半导体公司和研究组织竞相研发的课题之一。以“高k栅介质/金属栅”技术为核心的CMOS器件栅工程研究是22纳米及以下技术中最有代表性的关键核心工艺,与之相关的材料、工艺及结构研究已在广泛的进行中。
对于具有高k栅介质/金属栅结构的CMOS器件,其漏电流可以比具有多晶硅栅/SiO2结构的传统CMOS器件至少低一个数量级,即静态功耗可以大大减少。但随之而来的是CMOS器件的阈值电压控制问题。由于CMOS工艺需要同时具备NMOS与PMOS器件,所以为最大限度的优化器件性能,要求NMOS和PMOS器件的阈值电压在保持绝对值大致相等的前提下,要尽可能的降低阈值电压的数值。
目前优化CMOS器件阈值电压特性的方法包括,采用具有不同带边功函数的金属栅材料,在栅叠层中引入高k介质帽层,以产生界面偶极子等。另一方面,由于费米能级钉扎效应,Vfb roll-off效应等问题的存在,利用以上方法对NMOS器件及PMOS器件的阈值电压的调节也只能被限制在一定的范围内。
因此,新的栅叠层结构及加工工艺仍需进一步探索。
发明内容
(一)要解决的技术问题
有鉴于此,本发明的主要目的是提供一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构及其制造方法,该工艺是在NMOS和PMOS器件区域的高k栅介质层内部分别沉积极薄金属层,利用该极薄金属层在高k栅介质层内部形成的正或负电荷,以及由于金属原子热扩散引起的界面偶极子改变来调整器件的平带电压,进而控制器件的阈值电压。
(二)技术方案
为达到上述目的的一个方面,本发明提供了一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构,该结构包括:
硅衬底;
在硅衬底上生长的SiO2界面层;
在SiO2界面层上沉积的高k栅介质层;
在高k栅介质层上沉积的极薄金属层;
在极薄金属层结构上沉积的高k栅介质层;
在高k栅介质叠层结构上沉积的金属栅层。
上述方案中,所述SiO2界面层的厚度为0.3~1nm。
上述方案中,所述极薄金属层是被沉积于两层或多层同类或不同类的高k栅介质中间,所使用的沉积方法包括,物理沉积、化学气相沉积或原子层沉积。
上述方案中,对NMOS器件和PMOS器件,极薄金属层的材料不同,对于NMOS器件,极薄金属层的材料包括稀土金属Y、La、Dy、和Gd中的任一种;对PMOS器件,极薄金属层的材料包括金属Al、Mg和Hf中的任一种。
上述方案中,所述高k栅介质层包含一层高k栅介质结构或多层高k栅介质结构。
上述方案中,所述金属栅层包含一层栅电极结构或多层栅电极结构,是TiN、TaN、MoN、HfN、TaAlN、TiAlN、MoAlN、HfAlN、TaYbN、TaErN、TaTbN、TaC、HfC、TaSiC、HfSiC、Pt、Ru、Ir、W、Mo、Re、RuOx、RuTax、HfRux、多晶硅和金属硅化物中的至少一种或多种的组合。
上述方案中,所述高k栅介质层是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx中的至少一种,或者是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx中至少一种的氮化物、氮氧化物、其他稀土元素氧化物、其他稀土元素氮化物、SiNx和SiON中的至少一种或多种的组合。
为达到上述目的的另一个方面,本发明提供了一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,该方法包括:
在硅衬底上生长SiO2界面层;
在SiO2界面层上沉积高k栅介质层;
在高k栅介质层上沉积极薄金属层,形成高k栅介质层/极薄金属层结构;
在高k栅介质层/极薄金属层结构上沉积高k栅介质层,形成高k栅介质层/极薄金属层/高k栅介质叠层结构;
在高k栅介质层/极薄金属层/高k栅介质叠层结构上沉积金属栅层;
涂胶和刻蚀,形成利用栅叠层结构控制器件阈值电压的CMOSFETs结构。
上述方案中,所述在硅衬底上生长SiO2界面层的步骤中,生长的SiO2界面层的厚度为0.3~1nm。
上述方案中,所述在高k栅介质层上沉积极薄金属层的步骤中,极薄金属层是被沉积于两层或多层同类或不同类的高k栅介质中间,所使用的沉积方法包括,物理沉积、化学气相沉积和原子层沉积。
上述方案中,对NMOS器件和PMOS器件,所述极薄金属层的材料不同,对于NMOS器件来说,极薄金属层的材料包括稀土金属Y、La、Dy和Gd中的任一种;对PMOS器件来说,极薄金属层的材料包括金属Al、Mg和Hf中的任一种。
上述方案中,所述高k栅介质层包含一层高k栅介质结构或多层高k栅介质结构。
上述方案中,所述在高k栅介质层/极薄金属层/高k栅介质叠层结构上沉积金属栅层的步骤中,金属栅层包含一层栅电极结构或多层栅电极结构,是TiN、TaN、MoN、HfN、TaAlN、TiAlN、MoAlN、HfAlN、TaYbN、TaErN、TaTbN、TaC、HtC、TaSiC、HfSiC、Pt、Ru、Ir、W、Mo、Re、RuOx、RuTax、HfRux、多晶硅和金属硅化物中的至少一种或多种的组合。
上述方案中,所述高k栅介质层是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx中的至少一种,或者是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx中至少一种的氮化物、氮氧化物、其他稀土元素氧化物、其他稀土元素氮化物、SiNx和SiON中的至少一种或多种的组合。
(三)有益效果
本发明提供的这种利用栅叠层结构控制器件阈值电压的CMOSFETs结构及其制造方法,是在NMOS和PMOS器件区域的高k栅介质层内部分别沉积极薄金属层,利用该极薄金属层在高k栅介质层内部形成的正或负电荷来调整器件的平带电压,进而控制器件的阈值电压。利用本发明,不仅可以增强CMOS器件中高k栅介质和SiO2界面层间的界面偶极子,而且还可以很好的控制高k栅介质层内部的固定电荷类型和数量,可以有效地控制器件的阈值电压。
附图说明
图1是本发明提供的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的示意图;
图2是本发明提供的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法流程图;
图3至图8是依照本发明实施例利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
本发明提供的这种利用栅叠层结构控制器件阈值电压的CMOSFETs结构及其制造方法,是在NMOS和PMOS器件区域的高k栅介质层内部分别沉积极薄金属层,利用该极薄金属层在高k栅介质层内部形成的正或负电荷来调整器件的平带电压,进而控制器件的阈值电压。通过采取该工艺,不仅可以增强CMOS器件中高k栅介质和SiO2界面层间的界面偶极子,而且还可以很好的控制高k栅介质层内部的固定电荷类型和数量,可以有效地控制器件的阈值电压。
如图1所示,图1是本发明提供的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的示意图,该结构包括:
硅衬底;
在硅衬底上生长的SiO2界面层;
在SiO2界面层上沉积的高k栅介质层;
在高k栅介质层上沉积的极薄金属层;
在极薄金属层结构上沉积的高k栅介质层;
在高k栅介质叠层结构上沉积的金属栅层。
其中,SiO2界面层的厚度为0.3~1nm。极薄金属层是被沉积于两层或多层同类或不同类的高k栅介质中间,所使用的沉积方法包括,物理沉积、化学气相沉积或原子层沉积。对NMOS器件和PMOS器件,极薄金属层的材料不同,对于NMOS器件,极薄金属层的材料包括稀土金属Y、La、Dy、和Gd中的任一种;对PMOS器件,极薄金属层的材料包括金属Al、Mg和Hf中的任一种。高k栅介质层包含一层高k栅介质结构或多层高k栅介质结构。
金属栅层包含一层栅电极结构或多层栅电极结构,是TiN、TaN、MoN、HfN、TaAlN、TiAlN、MoAlN、HfAlN、TaYbN、TaErN、TaTbN、TaC、HfC、TaSiC、HfSiC、Pt、Ru、Ir、W、Mo、Re、RuOx、RuTax、HfRux、多晶硅和金属硅化物等中的至少一种或多种的组合。
高k栅介质层是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx等中的至少一种,或者是HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaAlOx和LaSiOx等中至少一种的氮化物、氮氧化物、其他稀土元素氧化物、其他稀土元素氮化物、SiNx和SiON中的至少一种或多种的组合。
基于图1所示的利用栅叠层结构控制器件阈值电压的CMOSFETs结构,图2示出了本发明提供的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法流程图,该方法包括:
步骤201:在硅衬底上生长SiO2界面层;
步骤202:在SiO2界面层上沉积高k栅介质层;
步骤203:在高k栅介质层上沉积极薄金属层,形成高k栅介质层/极薄金属层结构;
步骤204:在高k栅介质层/极薄金属层结构上沉积高k栅介质层,形成高k栅介质层/极薄金属层/高k栅介质叠层结构;
步骤205:在高k栅介质层/极薄金属层/高k栅介质叠层结构上沉积金属栅层;
步骤206:涂胶和刻蚀,形成利用栅叠层结构控制器件阈值电压的CMOSFETs结构。
图3至图8是依照本发明实施例利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法工艺流程图。
步骤1:如图3所示,在已做好前期工艺处理的硅衬底上生长0.5nm厚的SiO2界面层和3nm厚的第一层高k栅介质层HfO2。
步骤2:如图4所示,在第一区域的HfO2/SiO2结构上沉积一层极薄的金属层1。
步骤3:如图5所示,在第二区域的HfO2/SiO2结构上沉积一层极薄的金属层2。
步骤4:如图6所示,在第一区域和第二区域的极薄金属层上沉积第二层高k栅介质层(第一层高k栅介质层和第二层高k栅介质层可以是同种材料,也可以是不同种材料。)。
步骤5:如图7所示,在第二层高k栅介质层上分别沉积金属栅电极层1和金属栅电极2(金属栅电极1和金属栅电极2可以是同种材料,也可以是不同种材料。)。
步骤6:如图8所示,分别对第一区域和第二区域进行图形、涂胶和刻蚀等工艺,制备CMOSFETs器件。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (12)
1.一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其特征在于,该结构包括:
硅衬底;
在硅衬底上生长的SiO2界面层;
在SiO2界面层上沉积的高k栅介质层;
在高k栅介质层上沉积的极薄金属层;
在极薄金属层结构上沉积的高k栅介质层;
在高k栅介质叠层结构上沉积的金属栅层;
对于NMOS器件,极薄金属层的材料包括稀土金属Y、La、Dy和Gd中的任一种;对PMOS器件,极薄金属层的材料包括金属Al、Mg的任一种。
3.根据权利要求1所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其特征在于,所述极薄金属层是被沉积于两层或多层同类或不同类的高k栅介质中间,所使用的沉积方法包括,物理沉积、化学气相沉积或原子层沉积。
4.根据权利要求1所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其特征在于,所述高k栅介质层包含一层高k栅介质结构或多层高k栅介质结构。
5.根据权利要求1所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其特征在于,所述金属栅层包含一层栅电极结构或多层栅电极结构,是TiN、TaN、MoN、HfN、TaAIN、TiAIN、MoAIN、HfAIN、TaYbN、TaErN、TaTbN、TaC、HfC、TaSiC、HfSiC、Pt、Ru、Ir、W、Mo、Re、RuOx、RuTax、HfRux、多晶硅和金属硅化物中的至少一种或多种的组合。
6.根据权利要求1所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其特征在于,所述高k栅介质层是HfO2、HfSiOx、HfON、HfSiON、HfA1Ox、A12O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaA1Ox和LaSiOx中的至少一种,或者是HfO2、HfSiOx、HfON、HfSiON、HfA1Ox、A12O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaA1Ox和LaSiOx中至少一种的氮化物、氮氧化物、其他稀土元素氧化物、其他稀土元素氮化物、SiNx和SiON中的至少一种或多种的组合。
7.一种利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,其特征在于,该方法包括:
在硅衬底上生长SiO2界面层;
在SiO2界面层上沉积高k栅介质层;
在高k栅介质层上沉积极薄金属层,形成高k栅介质层/极薄金属层结构;
在高k栅介质层/极薄金属层结构上沉积高k栅介质层,形成高k栅介质层/极薄金属层/高k栅介质叠层结构;
在高k栅介质层/极薄金属层/高k栅介质叠层结构上沉积金属栅层;
涂胶和刻蚀,形成利用栅叠层结构控制器件阈值电压的CMOSFETs结构,其中,
对于NMOS器件来说,极薄金属层的材料包括稀土金属Y、La、Dy和Gd中的任一种;对PMOS器件来说,极薄金属层的材料包括金属Al、Mg中的任一种。
9.根据权利要求7所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,其特征在于,所述在高k栅介质层上沉积极薄金属层的步骤中,极薄金属层是被沉积于两层或多层同类或不同类的高k栅介质中间,所使用的沉积方法包括,物理沉积、化学气相沉积和原子层沉积。
10.根据权利要求7所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,其特征在于,所述高k栅介质层包含一层高k栅介质结构或多层高k栅介质结构。
11.根据权利要求7所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,其特征在于,所述在高k栅介质层/极薄金属层/高k栅介质叠层结构上沉积金属栅层的步骤中,金属栅层包含一层栅电极结构或多层栅电极结构,是TiN、TaN、MoN、HfN、TaAIN、TiAIN、MoAIN、HfAIN、TaYbN、TaErN、TaTbN、TaC、HfC、TaSiC、HfSiC、Pt、Ru、Ir、W、Mo、Re、RuOx、RuTax、HfRux、多晶硅和金属硅化物中的至少一种或多种的组合。
12.根据权利要求7所述的利用栅叠层结构控制器件阈值电压的CMOSFETs结构的制造方法,其特征在于,所述高k栅介质层是HfO2、HfSiOx、HfON、HfSiON、HfA1Ox、A12O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaA1Ox和LaSiOx中的至少一种,或者是HfO2、HfSiOx、HfON、HfSiON、HfA1Ox、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、HfLaOx、LaA1Ox和LaSiOx中至少一种的氮化物、氮氧化物、其他稀土元素氧化物、其他稀土元素氮化物、SiNx和SiON中的至少一种或多种的组合。
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