CN103855007A - P型mosfet的制造方法 - Google Patents
P型mosfet的制造方法 Download PDFInfo
- Publication number
- CN103855007A CN103855007A CN201210505742.0A CN201210505742A CN103855007A CN 103855007 A CN103855007 A CN 103855007A CN 201210505742 A CN201210505742 A CN 201210505742A CN 103855007 A CN103855007 A CN 103855007A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- dielectric layer
- metal gate
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 15
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 4
- 238000010406 interfacial reaction Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000007654 immersion Methods 0.000 claims description 3
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 2
- 229910003855 HfAlO Inorganic materials 0.000 claims description 2
- -1 HfAlON Inorganic materials 0.000 claims description 2
- 229910004143 HfON Inorganic materials 0.000 claims description 2
- 229910004129 HfSiO Inorganic materials 0.000 claims description 2
- 229910006252 ZrON Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 238000005224 laser annealing Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 claims description 2
- 125000002524 organometallic group Chemical group 0.000 claims 1
- 238000004506 ultrasonic cleaning Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 78
- 238000005530 etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
本发明公开了一种P型MOSFET的制造方法,所述方法包括:在半导体衬底上限定P型MOSFET的有源区;在半导体衬底的表面上形成界面氧化物层;在界面氧化物层上形成高K栅介质层;在高K栅介质层上形成金属栅层;在金属栅层中注入掺杂离子;在金属栅层上形成多晶硅层;将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层;形成围绕栅叠层的栅极侧墙;以及形成源/漏区。利用源/漏退火时使得金属栅中的掺杂离子在界面处堆积和生成合适极性的电偶极子,分别实现对P型MOSFET的金属栅有效功函数的调节。
Description
技术领域
本发明涉及半导体技术领域,具体地涉及包括金属栅和高K栅介质层的P型MOSFET的制造方法。
背景技术
随着半导体技术的发展,金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小导致栅电流泄漏的严重问题。高K栅介质层的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度,因而可以降低栅隧穿漏电流。然而,传统的多晶硅栅与高K栅介质层不兼容。金属栅与高K栅介质层一起使用不仅可以避免多晶硅栅的耗尽效应,减小栅电阻,还可以避免硼穿透,提高器件的可靠性。因此,金属栅和高K栅介质层的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质层的集成仍然面临许多挑战,如热稳定性问题、界面态问题。特别是由于费米钉扎效应,采用金属栅和高K栅介质层的MOSFET难以获得适当低的阈值电压。
为了获得合适的阈值电压,P型MOSFET的有效功函数应当在Si的价带顶附近(5.2eV左右)。对于P型MOSFET,期望选择合适的金属栅和高K栅介质层的组合以实现所需的阈值电压。然而,仅仅通过材料的选择获得如此高的有效功函数是困难的。
发明内容
本发明的目的是提供一种改进的制造P型MOSFET的方法,其中可以在制造过程调节半导体器件的有效功函数。
根据本发明,提供一种P型MOSFET的制造方法,所述方法包括:在半导体衬底上限定P型MOSFET的有源区;在半导体衬底的表面上形成界面氧化物层;在界面氧化物层上形成高K栅介质层;在高K栅介质层上形成金属栅层;在金属栅层中注入掺杂离子;在金属栅层上形成多晶硅层;将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层;形成围绕栅叠层的栅极侧墙;以及形成源/漏区,其中,在形成源/漏区的激活退火期间,使得金属栅中的掺杂离子扩散并聚积在高K栅介质层与金属栅层之间的上界面和高K栅介质层与界面氧化物之间的下界面处,并且在高K栅介质层与界面氧化物之间的下界面处通过界面反应产生电偶极子。
在该方法中,一方面,在高K栅介质层的上界面处聚积的掺杂离子改变了金属栅的性质,从而可以有利地调节相应的MOSFET的有效功函数。另一方面,在高K栅介质层的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子,从而可以进一步有利地调节相应的MOSFET的有效功函数。该方法获得的半导体器件的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。
附图说明
为了更好的理解本发明,将根据以下附图对本发明进行详细描述:
图1至7示意性地示出根据本发明的方法的一个实施例在制造P型MOSFET的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中,无论是否显示在不同实施例中,类似的部件采用相同或类似的附图标记表示。在各个附图中,为了清楚起见,附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。除非在下文中特别指出,半导体器件中的各个部分可以由本领域的技术人员公知的材料构成,或者可以采用将来开发的具有类似功能的材料。
在本申请中,术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者,并且采用相同的一个附图标记标示。术语“P型掺杂剂”是指用于P型MOSFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例,参照图1至7说明按照先栅工艺制造P型MOSFET的方法。
在图1中所示的半导体结构已经完成了先栅工艺的一部分。在半导体衬底101(例如,硅衬底)上包括由浅沟槽隔离102限定的P型MOSFET的有源区。
通过化学氧化或附加的热氧化,在半导体衬底101的暴露表面上形成界面氧化物层103(例如,氧化硅)。在一个实例中,通过在约600-900℃的温度下进行20-120s的快速热氧化形成界面氧化物层103。在另一个实例中,通过含臭氧(O3)的水溶液中进行化学氧化形成界面氧化物层103。
优选地,在形成界面氧化物层103之前,对半导体衬底101的表面进行清洗。该清洗包括首先进行常规的清洗,然后浸入包括氢氟酸、异丙醇和水的混合溶液中,然后采用去离子水冲洗,最后甩干。在一个实例中,该混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5%∶0.01-0.10%∶1,并且浸入时间约为1-10分钟。该清洗可以获得半导体衬底101的洁净的表面,抑制硅表面自然氧化物的生成和颗粒污染,从而有利于形成高质量的界面氧化物层103。
然后,通过已知的沉积工艺,如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、、溅射等,在半导体结构的表面上依次形成高K栅介质层104和金属栅层105,如图2所示。
高K栅介质层104由介电常数大于SiO2的合适材料构成,例如可以是选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种。金属栅层105由可以用于形成金属栅的合适材料构成,例如可以是选自TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个实例中,高K栅介质层104例如是厚度约1.5-5nm的HfO2层,金属栅层105例如是厚度约2-30nm的TiN层。
优选地,在形成高K栅介质层104和形成金属栅层105之间还可以包括高K栅介质层沉积后退火(post deposition annealing),以改善高K栅介质层的质量,这有利于随后形成的金属栅层105获得均匀的厚度。在一个实例中,通过在500-1000℃的温度进行5-100s的快速热退火作为沉积后退火。
然后,在在P型MOSFET的有源区的金属栅层105中注入P型掺杂剂,如图3所示。用于金属栅的P型掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量,使得注入的掺杂离子仅仅分布在金属栅层105中,而没有进入高K栅介质层104。并且控制离子注入的能量和剂量,使得金属栅层105具有合适的掺杂深度和浓度以获得期望的阈值电压。在一个实施例中,离子注入的能量约为0.2KeV-30KeV,剂量约为1E13-1E15cm-2。
然后,通过上述已知的沉积工艺,在半导体结构的表面上依次形成金属阻挡层108和多晶硅层109,如图4所示。金属阻挡层108由可以阻挡多晶硅层109和金属栅层107之间的反应和互扩散的材料组成,例如可以是选自TaN、AlN和TiN的一种。应当注意,金属阻挡层108是可选的,如果不会发生多晶硅层109和金属栅层107之间的反应和互扩散,则不需要包括该层。多晶硅层109掺杂为导电性的。在一个实例中,金属阻挡层108例如是厚度约为3-8nm的TaN层,多晶硅层的厚度约为30-120nm。
然后,采用光致抗蚀剂掩模(未示出)或硬掩模(未示出)进行图案化以形成栅叠层。在图案化中,通过干法蚀刻,如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀,或者通过其中使用蚀刻剂溶液的湿法蚀刻,选择性地去除多晶硅层109、阻挡层108、金属栅层105、高K栅介质层104和界面氧化物层103的暴露部分,形成P型MOSFET的栅叠层,如图5所示。
在用于形成栅叠层的图案化步骤中,可以针对不同的层采用不同的蚀刻剂。在一个实例中,在干法蚀刻多晶硅层109时采用基于F的蚀刻气体、基于Cl的蚀刻气体或者基于HBr/Cl2的蚀刻气体,在干法蚀刻金属栅层105/高K栅介质层104时采用基于BCL3/Cl2的蚀刻气体。优选地,在前述蚀刻气体中还可以添加Ar和/或O2以改善蚀刻效果。要求栅叠层的刻蚀具有陡直和连续的剖面,高的各向异性,对硅衬底有高的刻蚀选择比,不损伤硅衬底。
然后,通过上述已知的沉积工艺,在半导体结构的表面上形成例如10-50nm的氮化硅层,然后对氮化硅层进行各向异性蚀刻,从而在P型MOSFET的有源区中形成围绕栅叠层的侧墙110。采用栅叠层及其侧墙作为硬掩模进行源/漏离子注入,并进行激活退火,从而在半导体衬底101中形成P型MOSFET的源/漏区111,如图6所示。P型MOSFET的源/漏区111位于栅叠层的两侧,并且可以包括至少部分地延伸至高K栅介质层104下方的延伸区。
可以采用快速热退火(RTA)、瞬态退火(spike anneal)、激光退火(laser anneal)、微波退火(microwave anneal)进行激活退火。退火的温度约为950-1100℃,时间约为2ms-30s。在形成源/漏区的激活退火期间,使得金属栅层中注入的掺杂离子扩散并聚积在高K栅介质层与金属栅之间的上界面和高K栅介质层与界面氧化物之间的下界面处,形成堆积。一方面,在高K栅介质层104的上界面处聚积的掺杂离子改变了金属栅的性质,从而可以有利地调节相应的MOSFET的有效功函数。另一方面,在高K栅介质层104的下界面处聚积的掺杂离子通过界面反应还形成合适极性的电偶极子,从而可以进一步有利地调节P型MOSFET的有效功函数,实现对PMOS器件金属栅有效功函数的调节。
在源/漏区111和多晶硅栅109的表面还形成了硅化区112(例如,硅化镍,硅化镍铂),以减小源/漏区111和多晶硅栅109的串联电阻和接触电阻。
然后,通过上述已知的沉积工艺,在半导体结构的表面上形成覆盖有源区的层间介质层113(例如,氮化硅,氧化硅)。通过化学机械抛光(CMP),平整层间介质层113的表面并暴露多晶硅栅109的顶部的硅化物表面,如图7所示。然后进行公知技术的接触和金属化。
在上文中并未描述MOSFET的所有细节,例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的MOSFET中,因此对此不再详述。
以上描述只是为了示例说明和描述本发明,而非意图穷举和限制本发明。因此,本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改,均在本发明的保护范围之内。
Claims (20)
1.一种P型MOSFET的制造方法,所述方法包括:
在半导体衬底上限定P型MOSFET的有源区;
在半导体衬底的表面上形成界面氧化物层;
在界面氧化物层上形成高K栅介质层;
在高K栅介质层上形成金属栅层;
在金属栅层中注入掺杂离子;
在金属栅层上形成多晶硅层;
将多晶硅层、金属栅层、高K栅介质层和界面氧化物层图案化为栅叠层;
形成围绕栅叠层的栅极侧墙;以及
形成源/漏区,
其中,在形成源/漏区的激活退火期间,使得金属栅中的掺杂离子扩散并聚积在高K栅介质层与金属栅层之间的上界面和高K栅介质层与界面氧化物之间的下界面处,并且在高K栅介质层与界面氧化物之间的下界面处通过界面反应产生电偶极子。
2.根据权利要求1所述的方法,其中在限定有源区的步骤和形成界面氧化物的步骤之间,还包括对半导体衬底的表面进行清洗。
3.根据权利要求2所述的方法,其中清洗包括:
在去离子水中进行超声清洗;
浸入包括氢氟酸、异丙醇和水的混合溶液中;
采用去离子水冲洗;以及
甩干。
4.根据权利要求3所述的方法,其中混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5%∶0.01-0.10%∶1。
5.根据权利要求3所述的方法,其中浸入时间约为2-10分钟。
6.根据权利要求1所述的方法,其中在形成高K栅介质层的步骤和形成金属栅层的步骤之间,还包括高K栅介质层沉积后退火以改善高K栅介质层的质量。
7.根据权利要求1所述的方法,其中高K栅介质层由选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种构成。
8.根据权利要求1所述的方法,其中采用原子层沉积、物理汽相沉积或金属有机化学汽相沉积形成高K栅介质层。
9.根据权利要求1所述的方法,其中高K栅介质层的厚度约为1.5-5nm。
10.根据权利要求1所述的方法,其中金属栅层由选自TiN、TaN、MoN、WN、TaC和TaCN的一种构成。
11.根据权利要求1所述的方法,其中金属栅层的厚度约为2-30nm。
12.根据权利要求1所述的方法,其中在金属栅层中注入掺杂离子的步骤中,控制离子注入的能量和剂量,使得掺杂离子仅仅分布在金属栅层中,并根据期望的阈值电压控制离子注入的能量和剂量。
13.根据权利要求12所述的方法,其中离子注入的能量约为0.2KeV-30KeV。
14.根据权利要求12所述的方法,其中离子注入的剂量约为1E13-1E15cm-2。
15.根据权利要求1所述的方法,其中在金属栅层中注入掺杂离子的步骤中采用可以增加有效功函数的掺杂剂。
16.根据权利要求15所述的方法,其中掺杂剂是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。
17.根据权利要求1所述的方法,其中在注入步骤和形成多晶硅层的步骤之间,还包括在金属栅层上形成金属阻挡层,其中金属阻挡层位于金属栅层和随后形成的多晶硅层之间。
18.根据权利要求17所述的方法,其中金属阻挡层是选自TaN、AlN和TiN的一种。
19.根据权利要求1所述的方法,其中高温退火的温度约为950-1100℃,时间约为2ms-30s。
20.根据权利要求1所述的方法,其中采用选自快速热退火、瞬态退火、激光退火和微波退火中的一种进行退火。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210505742.0A CN103855007A (zh) | 2012-11-30 | 2012-11-30 | P型mosfet的制造方法 |
US14/373,628 US20150011069A1 (en) | 2012-11-30 | 2012-12-07 | Method for manufacturing p-type mosfet |
PCT/CN2012/086112 WO2014082331A1 (zh) | 2012-11-30 | 2012-12-07 | P型mosfet的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210505742.0A CN103855007A (zh) | 2012-11-30 | 2012-11-30 | P型mosfet的制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103855007A true CN103855007A (zh) | 2014-06-11 |
Family
ID=50827100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210505742.0A Pending CN103855007A (zh) | 2012-11-30 | 2012-11-30 | P型mosfet的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20150011069A1 (zh) |
CN (1) | CN103855007A (zh) |
WO (1) | WO2014082331A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106653591A (zh) * | 2016-12-12 | 2017-05-10 | 东莞市广信知识产权服务有限公司 | 一种在GaN表面生长高K介质的方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103855013A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | N型mosfet的制造方法 |
US10615041B2 (en) * | 2017-12-11 | 2020-04-07 | Applied Materials, Inc. | Methods and materials for modifying the threshold voltage of metal oxide stacks |
CN115132585A (zh) * | 2021-03-29 | 2022-09-30 | 联华电子股份有限公司 | 高电子迁移率晶体管及其制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020130378A1 (en) * | 2001-03-15 | 2002-09-19 | Leonard Forbes | Technique to mitigate short channel effects with vertical gate transistor with different gate materials |
CN1943027A (zh) * | 2004-02-25 | 2007-04-04 | 国际商业机器公司 | Cmos硅化物金属栅集成 |
CN101924034A (zh) * | 2009-06-17 | 2010-12-22 | 中国科学院微电子研究所 | 调节高k栅介质和金属栅结构pMOSFET器件阈值电压的方法 |
US20110256704A1 (en) * | 2010-04-09 | 2011-10-20 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing a metal gate electrode/high k dielectric gate stack |
CN102254805A (zh) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | 一种适用于nmos器件的金属栅功函数的调节方法 |
CN102280376A (zh) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6720630B2 (en) * | 2001-05-30 | 2004-04-13 | International Business Machines Corporation | Structure and method for MOSFET with metallic gate electrode |
US7087480B1 (en) * | 2002-04-18 | 2006-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process to make high-k transistor dielectrics |
US6902980B2 (en) * | 2003-06-05 | 2005-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
US6780741B2 (en) * | 2003-01-08 | 2004-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers |
US20050224897A1 (en) * | 2004-03-26 | 2005-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-K gate dielectric stack with buffer layer to improve threshold voltage characteristics |
US7416933B2 (en) * | 2004-08-06 | 2008-08-26 | Micron Technology, Inc. | Methods of enabling polysilicon gate electrodes for high-k gate dielectrics |
US20060163671A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Silicide cap structure and process for reduced stress and improved gate sheet resistance |
US8188551B2 (en) * | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20080237743A1 (en) * | 2007-03-30 | 2008-10-02 | Texas Instruments Incorporated | Integration Scheme for Dual Work Function Metal Gates |
US7858459B2 (en) * | 2007-04-20 | 2010-12-28 | Texas Instruments Incorporated | Work function adjustment with the implant of lanthanides |
US7511348B2 (en) * | 2007-03-13 | 2009-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS transistors with selectively strained channels |
US7629212B2 (en) * | 2007-03-19 | 2009-12-08 | Texas Instruments Incorporated | Doped WGe to form dual metal gates |
US7763945B2 (en) * | 2007-04-18 | 2010-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained spacer design for protecting high-K gate dielectric |
US7727838B2 (en) * | 2007-07-27 | 2010-06-01 | Texas Instruments Incorporated | Method to improve transistor Tox using high-angle implants with no additional masks |
US7790616B2 (en) * | 2007-08-29 | 2010-09-07 | Northrop Grumman Systems Corporation | Encapsulated silicidation for improved SiC processing and device yield |
US7892930B2 (en) * | 2007-10-08 | 2011-02-22 | Texas Instruments Incorporated | Method to improve transistor tox using SI recessing with no additional masking steps |
US7648868B2 (en) * | 2007-10-31 | 2010-01-19 | International Business Machines Corporation | Metal-gated MOSFET devices having scaled gate stack thickness |
US8058122B2 (en) * | 2007-12-28 | 2011-11-15 | Texas Instruments Incorporated | Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal |
JP5592083B2 (ja) * | 2009-06-12 | 2014-09-17 | アイメック | 基板処理方法およびそれを用いた半導体装置の製造方法 |
US8354671B1 (en) * | 2010-05-17 | 2013-01-15 | Xilinx, Inc. | Integrated circuit with adaptive VGG setting |
CN102339858B (zh) * | 2010-07-16 | 2013-09-04 | 中国科学院微电子研究所 | p型半导体器件及其制造方法 |
JP2012253241A (ja) * | 2011-06-03 | 2012-12-20 | Sony Corp | 半導体集積回路およびその製造方法 |
CN102915917B (zh) * | 2011-08-03 | 2015-02-11 | 中国科学院微电子研究所 | 一种互补型金属氧化物半导体场效应晶体管的制备方法 |
US8647951B2 (en) * | 2011-08-24 | 2014-02-11 | Globalfoundries Inc. | Implantation of hydrogen to improve gate insulation layer-substrate interface |
FR2983351B1 (fr) * | 2011-11-28 | 2014-01-24 | Commissariat Energie Atomique | Diode p/n a heterostructure controlee autopositionnee sur hgcdte pour imageurs infrarouges |
-
2012
- 2012-11-30 CN CN201210505742.0A patent/CN103855007A/zh active Pending
- 2012-12-07 WO PCT/CN2012/086112 patent/WO2014082331A1/zh active Application Filing
- 2012-12-07 US US14/373,628 patent/US20150011069A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020130378A1 (en) * | 2001-03-15 | 2002-09-19 | Leonard Forbes | Technique to mitigate short channel effects with vertical gate transistor with different gate materials |
US20040185630A1 (en) * | 2001-03-15 | 2004-09-23 | Leonard Forbes | Technique to mitigate short channel effects with vertical gate transistor with different gate materials |
CN1943027A (zh) * | 2004-02-25 | 2007-04-04 | 国际商业机器公司 | Cmos硅化物金属栅集成 |
CN101924034A (zh) * | 2009-06-17 | 2010-12-22 | 中国科学院微电子研究所 | 调节高k栅介质和金属栅结构pMOSFET器件阈值电压的方法 |
US20110256704A1 (en) * | 2010-04-09 | 2011-10-20 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing a metal gate electrode/high k dielectric gate stack |
CN102254805A (zh) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | 一种适用于nmos器件的金属栅功函数的调节方法 |
CN102280376A (zh) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106653591A (zh) * | 2016-12-12 | 2017-05-10 | 东莞市广信知识产权服务有限公司 | 一种在GaN表面生长高K介质的方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2014082331A1 (zh) | 2014-06-05 |
US20150011069A1 (en) | 2015-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103854982B (zh) | 半导体器件的制造方法 | |
CN103855093B (zh) | 半导体器件及其制造方法 | |
CN103855006A (zh) | 半导体器件的制造方法 | |
CN107958872A (zh) | 半导体器件及其形成方法 | |
CN103854983B (zh) | P型mosfet的制造方法 | |
US8980718B2 (en) | PMOS transistors and fabrication method | |
CN103855016A (zh) | 半导体器件的制造方法 | |
CN103855012A (zh) | N型mosfet的制造方法 | |
US9934975B2 (en) | N-type MOSFET and method for manufacturing the same | |
CN103855014B (zh) | P型mosfet及其制造方法 | |
CN103855094A (zh) | 半导体器件及其制造方法 | |
CN103094214B (zh) | 制作半导体器件的方法 | |
CN105226023A (zh) | 半导体器件的形成方法 | |
CN103855007A (zh) | P型mosfet的制造方法 | |
US9029225B2 (en) | Method for manufacturing N-type MOSFET | |
CN103855013A (zh) | N型mosfet的制造方法 | |
CN104299994B (zh) | 晶体管及晶体管的形成方法 | |
CN110690109B (zh) | 半导体器件及其形成方法 | |
CN106847695A (zh) | 鳍式场效应管的形成方法 | |
CN107749398A (zh) | P型mosfet的制作方法 | |
CN104064452A (zh) | 半导体器件的形成方法 | |
CN108039368A (zh) | N型mosfet的制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140611 |
|
RJ01 | Rejection of invention patent application after publication |