CN103855014B - P型mosfet及其制造方法 - Google Patents

P型mosfet及其制造方法 Download PDF

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CN103855014B
CN103855014B CN201210506506.0A CN201210506506A CN103855014B CN 103855014 B CN103855014 B CN 103855014B CN 201210506506 A CN201210506506 A CN 201210506506A CN 103855014 B CN103855014 B CN 103855014B
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metal gate
layer
gate layer
gate
semiconductor substrate
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CN103855014A (zh
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朱慧珑
徐秋霞
张严波
杨红
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Institute of Microelectronics of CAS
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Priority to PCT/CN2012/086173 priority patent/WO2014082342A1/zh
Priority to US14/385,101 priority patent/US10056261B2/en
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Abstract

公开了一种P型MOSFET及其制造方法。P型MOSFET的制造方法包括：在半导体衬底中形成源/漏区；在半导体衬底上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；通过共形掺杂在第一金属栅层中注入掺杂剂；以及进行退火以改变栅叠层的有效功函数，其中栅叠层包括第一金属栅层、高K栅介质和界面氧化物层。

Description

P型MOSFET及其制造方法
技术领域
本发明涉及半导体技术领域，具体地涉及包括金属栅和高K栅介质的P型MOSFET及其制造方法。
背景技术
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸不断减小。MOSFET的尺寸缩小导致栅电流泄漏的严重问题。高K栅介质的使用使得可以在保持等效氧化物厚度(EOT)不变的情形下增加栅介质的物理厚度，因而可以降低栅隧穿漏电流。然而，传统的多晶硅栅与高K栅介质不兼容。金属栅与高K栅介质一起使用不仅可以避免多晶硅栅的耗尽效应，减小栅电阻，还可以避免硼穿透，提高器件的可靠性。因此，金属栅和高K栅介质的组合在MOSFET中得到了广泛的应用。金属栅和高K栅介质的集成仍然面临许多挑战，如热稳定性问题、界面态问题。特别是由于费米钉扎效应，采用金属栅和高K栅介质的MOSFET难以获得适当低的阈值电压。
为了获得合适的阈值电压，P型MOSFET的有效功函数应当在Si的导带底附近(5.2eV左右)。对于P型MOSFET，期望选择合适的金属栅和高K栅介质的组合以实现所需的阈值电压。然而，仅仅通过材料的选择获得如此高的有效功函数是困难的。
发明内容
本发明的目的是提供一种改进的P型MOSFET及其方法，其中可以在制造过程调节P型MOSFET的有效功函数。
根据本发明的一方面，提供一种P型MOSFET的制造方法，所述方法包括：在半导体衬底中形成源/漏区；在半导体衬底上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；通过共形掺杂在第一金属栅层中注入掺杂剂；以及进行退火以改变栅叠层的有效功函数，其中栅叠层包括第一金属栅层、高K栅介质和界面氧化物层。在优选的实施例中，在P型MOSFET的金属栅层注入用于增加有效功函数的掺杂剂。
根据本发明的另一方面，提供一种P型MOSFET，包括：位于半导体衬底中的源/漏区；位于半导体衬底上的界面氧化物层；位于界面氧化物层上的高K栅介质；以及位于高K栅介质上的第一金属栅层，其中掺杂剂分布在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子，从而改变栅叠层的有效功函数，其中栅叠层包括第一金属栅层、高K栅介质和界面氧化物层。
根据本发明，一方面，在高K栅介质的上界面处聚积的掺杂剂改变了金属栅的性质，从而可以有利地调节P型MOSFET的有效功函数。另一方面，在高K栅介质的下界面处聚积的掺杂剂通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节P型MOSFET的有效功函数。该方法获得的P型MOSFET的性能表现出良好的稳定性和显著的调节金属栅的有效功函数的作用。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1至11示意性地示出根据本发明的方法的一个实施例在制造P型MOSFET的各个阶段的半导体结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在下文的描述中，无论是否显示在不同实施例中，类似的部件采用相同或类似的附图标记表示。在各个附图中，为了清楚起见，附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
在本申请中，术语“半导体结构”指在经历制造半导体器件的各个步骤后形成的半导体衬底和在半导体衬底上已经形成的所有层或区域。术语“源/漏区”指一个MOSFET的源区和漏区二者，并且采用相同的一个附图标记标示。术语“正掺杂剂”是指用于P型MOSFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例，参照图1至11说明制造P型MOSFET的方法，其中示出该方法的各阶段形成的半导体结构的截面图。
在图1中所示的半导体结构已经完成了一部分CMOS工艺。在半导体衬底101(例如，Si衬底)中的一定深度位置形成P型MOSFET的N阱102。在图1所示的示例中，将N阱102示出为矩形，但实际上N阱102可能没有清晰的边界，并且可能由半导体衬底101的一部分隔开。浅沟槽隔离103限定P型MOSFET的有源区。
然后，通过已知的沉积工艺，如电子束蒸发(EBM)、化学气相沉积(CVD)、原子层沉积(ALD)、溅射等，在半导体结构的表面上形成假栅极电介质104(例如，氧化硅或氮化硅)。在一个示例中，假栅极电介质104为约0.8-1.5nm厚的氧化硅层。进一步地，通过上述已知的沉积工艺，在假栅极电介质104的表面上形成假栅导体105(例如，多晶硅或非晶硅层(α-Si))，如图2所示。
然后，例如通过旋涂在假栅极电介质104上形成光致抗蚀剂层PR1，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层PR1形成用于限定栅叠层的形状(例如，条带)的图案。
采用光致抗蚀剂层PR1作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅导体105的暴露部分，形成P型MOSFET的假栅导体105，如图3所示。在图3所示的示例中，P型MOSFET的假栅导体105是条带图案，但假栅导体105也可以是其他形状。
然后，通过在溶剂中溶解或灰化去除光致抗蚀剂层PR1。采用假栅导体105作为硬掩模进行离子注入以形成P型MOSFET的延伸区。在优选的示例中，还可以进一步进行离子注入以形成P型MOSFET的晕圈区(halo)。
通过上述已知的沉积工艺，在半导体结构的表面上形成氮化物层。在一个示例中，该氮化物层为厚度约5-30nm的氮化硅层。通过各向异性的蚀刻工艺(例如，反应离子蚀刻)，去除氮化物层的横向延伸的部分，使得氮化物层位于假栅导体105的侧面上的垂直部分保留，从而形成栅极侧墙106。结果，栅极侧墙106围绕假栅导体105。
采用假栅导体105及其栅极侧墙106作为硬掩模，进行离子注入以形成源/漏，从而形成P型MOSFET的源/漏区107，如图4所示。在用于形成源/漏区的离子注入之后，可以在大约1000-1100℃的温度下进行快速退火(spike anneal)，和/或激光退火(laser anneal)以激活掺杂离子。
然后，采用假栅导体105及其栅极侧墙106作为硬掩模，选择性地去除假栅极电介质104的暴露部分，从而暴露P型MOSFET的N阱102的一部分表面，如图5所示。结果，剩余部分的假栅极电介质104位于假栅导体105下方。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成共形的第一绝缘层(例如，氮化硅)108，如图6所示。第一绝缘层108覆盖P型MOSFET的假栅导体105和N阱102。在一个示例中，第一绝缘层108是厚度约5-30nm的氮化硅层。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成覆盖的第二绝缘层(例如，氧化硅)109。第二绝缘层109覆盖第一绝缘层108并且填充假栅导体105之间的开口。进行化学机械抛光(CMP)以平整半导体结构的表面。CMP去除第一绝缘层108和第二绝缘层109位于假栅导体105上方的部分，并且可以进一步去除假栅导体105以及栅极侧墙106的一部分。结果，半导体结构不仅获得平整的表面并且暴露假栅导体105，如图7所示。第一绝缘层108和第二绝缘层109一起作为层间介质层。
然后，以第一绝缘层108、第二绝缘层109以及栅极侧墙106作为硬掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，选择性地去除假栅导体105，并且进一步去除假栅极电介质104的位于假栅导体105的部分，如图8所示。在一个示例中，假栅导体105由多晶硅组成，在该蚀刻中，通过其中使用合适的蚀刻剂(例如甲基氢氧化铵，缩写为TMAH)溶液的湿法蚀刻去除。该蚀刻形成暴露P型MOSFET的N阱102的顶部表面和侧壁的栅极开口。
然后，通过化学氧化或附加的热氧化，在P型MOSFET的N阱102的暴露表面上形成界面氧化物层110(例如，氧化硅)。在一个示例中，通过在约600-900℃的温度下进行20-120s的快速热氧化形成界面氧化物层110。在另一个示例中，通过含臭氧(O3)的水溶液中进行化学氧化形成界面氧化物层110。
优选地，在形成界面氧化物层110之前，对P型MOSFET的N阱102的表面进行清洗。该清洗包括首先进行常规的清洗，然后浸入包括氢氟酸、异丙醇和水的混合溶液中，然后采用去离子水冲洗，最后甩干。在一个示例中，该混合溶液的成分为氢氟酸∶异丙醇∶水的体积比约为0.2-1.5％∶0.01-0.10％∶1，并且浸入时间约为1-10分钟。该清洗可以获得P型MOSFET的N阱102的洁净的表面，抑制硅表面自然氧化物的生成和颗粒污染，从而有利于形成高质量的界面氧化物层110。
然后，通过已知的沉积工艺，如ALD(原子层沉积)、CVD(化学气相沉积)、MOCVD(金属有机化学气相沉积)、PVD(物理气相沉积)、溅射等，在半导体结构的表面上依次形成共形的高K栅介质111和第一金属栅层112，如图9所示。
高K栅介质111由介电常数大于SiO2的合适材料构成，例如可以是选自ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON及其任意组合的一种。第一金属栅层112由可以用于形成金属栅的合适材料构成，例如可以是选自TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个示例中，界面氧化物层110例如是厚度约为0.2-0.8nm的氧化硅层。高K栅介质111例如是厚度约2-5nm的HfO2层，第一金属栅层112例如是厚度约1-10nm的TiN层。
优选地，在形成高K栅介质111和形成第一金属栅层112之间还可以包括高K栅介质沉积后退火(post deposition annealing)，以改善高K栅介质的质量，这有利于随后形成的第一金属栅层112获得均匀的厚度。在一个示例中，通过在500-1000℃的温度进行5-100s的快速热退火作为沉积后退火。
然后，采用共形掺杂(conformal doping)在P型MOSFET的有源区的第一金属栅层112中注入正掺杂剂，如图10所示。用于金属栅的正掺杂剂可以是选自In、B、BF2、Ru、W、Mo、Al、Ga、Pt的一种。控制离子注入的能量和剂量，使得注入的掺杂剂仅仅分布在第一金属栅层112中，而没有进入高K栅介质111，并且控制离子注入的能量和剂量，使得第一金属栅层112具有合适的掺杂深度和浓度以获得期望的阈值电压。在一个示例中，离子注入的能量约为0.2KeV-30KeV，剂量约为1E13-1E15cm-2。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二金属栅层113。以第二绝缘层109作为停止层进行化学机械抛光(CMP)，以去除高K栅介质111、第一金属栅层112、第二金属栅层113位于栅极开口外的部分，而仅仅保留位于栅极开口内的部分，如图11所示。第二金属栅层可以由与第一金属栅层相同或不同的材料组成，例如可以是选自W、TiN、TaN、MoN、WN、TaC和TaCN的一种。在一个示例中，第二金属栅层例如是厚度约2-30nm的W层。在图中示出P型MOSFET的栅叠层包括第二金属栅层113、第一金属栅层112、高K栅介质111和界面氧化物层110。
在针对金属栅的掺杂的步骤之后，例如在形成第二金属栅层113之前或之后，在惰性气氛(例如N2)或弱还原性气氛(例如N2和H2的混合气氛)中进行退火。在一个示例中，在炉中进行退火，退火温度约为350℃-700℃，退火时间约为5-30分钟。退火驱使注入的掺杂剂扩散并聚积在高K栅介质111的上界面和下界面处，并且进一步在高K栅介质111的下界面处通过界面反应形成电偶极子。这里，高K栅介质111的上界面是指其与上方的第一金属栅层112之间的界面，高K栅介质111的下界面是指其与下方的界面氧化物层110之间的界面。
该退火改变了掺杂剂的分布。一方面，在高K栅介质111的上界面处聚积的掺杂剂改变了金属栅的性质，从而可以有利地调节P型MOSFET的有效功函数。另一方面，在高K栅介质111的下界面处聚积的掺杂剂通过界面反应还形成合适极性的电偶极子，从而可以进一步有利地调节P型MOSFET的有效功函数。结果，P型MOSFET的栅叠层的有效功函数可以在4.8eV至5.2eV的范围内改变。
在上文中并未描述制造半导体器件的所有细节，例如源/漏接触、附加的层间电介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准CMOS工艺以及如何应用于上述实施例的半导体器件中，因此对此不再详述。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (9)

1.一种P型MOSFET的制造方法，所述方法包括：
在半导体衬底中形成源/漏区，其中在形成源/漏区的步骤包括：
在半导体衬底上形成假栅叠层，假栅叠层包括假栅导体和位于假栅导体和半导体衬底之间的假栅极电介质，
形成围绕假栅导体的栅极侧墙，以及
以假栅导体和栅极侧墙作为硬掩模，在半导体衬底中形成源/漏区；
去除假栅叠层以形成暴露半导体衬底的表面的栅极开口；
在半导体衬底上形成界面氧化物层；
在界面氧化物层上形成高K栅介质；
在高K栅介质上形成第一金属栅层；
通过共形掺杂在第一金属栅层中注入掺杂剂；
在第一金属栅层上形成第二金属栅层以填充栅极开口；
去除高K栅介质、第一金属栅层和第二金属栅层位于栅极开口外的部分；以及
进行退火以改变栅叠层的有效功函数，其中栅叠层包括第一金属栅层、高K栅介质和界面氧化物层，
其中掺杂剂是选自In、B、BF2的一种，
其中在第一金属栅层中注入掺杂剂的步骤中，控制离子注入的能量和剂量使得掺杂剂仅仅分布在第一金属栅层中，其中离子注入的能量为0.2KeV-30KeV，第一金属栅层的厚度为1-10nm，以及
其中在惰性气氛或弱还原性气氛中执行退火，退火温度为350-700度。
2.根据权利要求1所述的方法，其中在形成高K栅介质的步骤和形成第一金属栅层的步骤之间还包括附加的退火以改善高K栅介质的质量。
3.根据权利要求1所述的方法，其中第一金属栅层由选自TiN、TaN、MoN、WN、TaC、TaCN及其任意组合的一种构成。
4.根据权利要求1所述的方法，其中第一金属栅层的厚度为2-10nm。
5.根据权利要求4所述的方法，其中第二金属栅层由选自W、Ti、TiAl、Al、Mo、Ta、TiN、TaN、WN及其任意组合的一种构成。
6.根据权利要求1所述的方法，其中离子注入的剂量为1E13-1E15cm-2。
7.根据权利要求1所述的方法，其中在形成源/漏区的步骤之前还包括：
在半导体衬底中形成阱，其中阱的掺杂类型为N型，并且随后形成的源/漏区位于阱中。
8.根据权利要求1所述的方法，其中在第一金属栅层中注入的掺杂剂是增加有效功函数的掺杂剂。
9.根据权利要求1所述的方法，其中退火时间为5-30分钟。
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