WO2014082336A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014082336A1
WO2014082336A1 PCT/CN2012/086128 CN2012086128W WO2014082336A1 WO 2014082336 A1 WO2014082336 A1 WO 2014082336A1 CN 2012086128 W CN2012086128 W CN 2012086128W WO 2014082336 A1 WO2014082336 A1 WO 2014082336A1
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Prior art keywords
layer
semiconductor
gate
dopant
metal gate
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PCT/CN2012/086128
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English (en)
French (fr)
Inventor
朱慧珑
徐秋霞
张严波
杨红
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中国科学院微电子研究所
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Publication of WO2014082336A1 publication Critical patent/WO2014082336A1/zh
Priority to US14/722,684 priority Critical patent/US20150255557A1/en

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Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device including a metal gate and a high-k gate dielectric and a method of fabricating the same. Background technique
  • MOSFETs metal oxide semiconductor field effect transistors
  • EOT equivalent oxide thickness
  • conventional polysilicon gates are not compatible with high-k gate dielectrics.
  • the use of a metal gate with a high-k gate dielectric not only avoids the depletion effect of the polysilicon gate, reduces the gate resistance, but also avoids boron penetration and improves device reliability. Therefore, the combination of metal gate and high-k gate dielectric is widely used in MOSFETs.
  • the effective work function of the N-type FinFET should be near the bottom of the conduction band of Si (around 4. leV), and the effective work function of the P-type FinFET should be Near the top of the valence band of Si (about 5. 2eV).
  • a combination of different metal gates and high K gate dielectrics can be selected for the N-type FinFET and the P-type FinFET, respectively, to achieve the desired threshold voltage. As a result, it is necessary to form a double metal gate and a double high K gate dielectric on one chip.
  • a method of fabricating a semiconductor device comprising: forming a semiconductor fin on a semiconductor substrate; forming an interface oxide layer on a top surface and a sidewall of the semiconductor fin; Forming a high-k gate dielectric on the oxide layer; forming a first metal gate layer on the high-k gate dielectric; implanting a dopant into the first metal gate layer by conformal doping; and annealing to diffuse the dopant Accumulating at an upper interface between the high- ⁇ gate dielectric and the first metal gate layer and a lower interface between the high- ⁇ gate dielectric and the interface oxide, and passing at a lower interface between the high- ⁇ gate dielectric and the interface oxide The interface reaction produces an electric dipole.
  • the semiconductor device includes an N-type FinFET and a P-type FinFET formed on a semiconductor substrate, and implants a doping for reducing an effective work function in a first metal gate layer of the N-type FinFET.
  • the dopant is implanted in the first metal gate layer of the P-type FinFET with a dopant that increases the effective work function.
  • a semiconductor device comprising: a semiconductor fin on a semiconductor substrate; an interface oxide layer on a top surface and a sidewall of the semiconductor fin; on the interface oxide layer a high-k gate dielectric; and a first metal gate layer on the high-k gate dielectric, wherein the dopant is distributed between the upper interface between the high- ⁇ gate dielectric and the first metal gate layer and the high- ⁇ gate dielectric and the interface oxide At the lower interface, and generating an electric dipole through the interfacial reaction at the lower interface between the high ⁇ gate dielectric and the interface oxide.
  • the dopants accumulated at the upper interface of the high ⁇ gate dielectric change the properties of the metal gate, so that the effective work function of the corresponding MOSFET can be advantageously adjusted.
  • the dopant accumulated at the lower interface of the high-k gate dielectric also forms an electric dipole of a suitable polarity through the interfacial reaction, so that the effective work function of the corresponding MOSFET can be further advantageously adjusted.
  • the performance of the semiconductor device obtained by this method exhibits good stability and a significant effect of adjusting the effective work function of the metal gate. By selecting different dopants for both types of MOSFETs, the effective work function can be reduced or increased.
  • the threshold voltages of the two types of MOSFETs can be separately adjusted by simply changing the dopants, without the need to use different combinations of metal gates and gate dielectrics, respectively. Therefore, the method can omit the corresponding deposition steps and masking and etching steps, thereby achieving a simplified process and being easy to mass-produce. Conformal doping improves the uniformity of distribution of dopants near the top and side walls of the semiconductor fins, thereby suppressing random fluctuations in threshold voltage.
  • the semiconductor device further includes a doped pass-through blocking layer between the semiconductor substrate and the semiconductor fin, or a well located in the semiconductor substrate.
  • the doping pass-through blocking layer and/or well is opposite to the doping type of the source/drain regions to reduce leakage current between the source/drain regions.
  • FIG. 1 through 13 schematically illustrate cross-sectional views of a semiconductor structure at various stages of fabricating a semiconductor device in accordance with one embodiment of the method of the present invention. detailed description
  • semiconductor structure refers to a semiconductor substrate formed after undergoing various steps of fabricating a semiconductor device and all layers or regions that have been formed on the semiconductor substrate.
  • source/drain region refers to both the source and drain regions of a MOSFET and is labeled with the same reference numeral.
  • negative dopant refers to a dopant for an N-type FinFET that reduces the effective work function.
  • positive dopant refers to a dopant for a P-type FinFET that can increase the effective work function.
  • FIGS. 7a-9a A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown, and semiconductor structures taken along line BB in the length direction of the semiconductor fin of the P-type FinFET are shown in FIGS. 10-11, 12B, and 13b.
  • FIG. 12A is a cross-sectional view showing the semiconductor structure taken along the line CC in the longitudinal direction of the semiconductor fin of the N-type FinFET.
  • the semiconductor device is a CMOS device including an N-type FinFET and a P-type FinFET formed on a semiconductor substrate.
  • a portion of the CMOS process has been completed in the semiconductor structure shown in FIG.
  • a P well 102a for an N-type FinFET and an N well 102b for a P-type FinFET are formed at a certain depth position in the semiconductor substrate 101 (for example, a Si substrate).
  • the semiconductor substrate 101 for example, a Si substrate.
  • P-well 102a and N-well 102b are shown as being rectangular and directly adjacent, but in reality P-well 102a and N-well 102b may not have sharp boundaries and may be lining by semiconductor
  • a portion of the bottom 101 is spaced apart.
  • a semiconductor layer 103 eg, Si
  • Si is over the P-well 102a and the N-well 102b and will be used to form the semiconductor fins.
  • the thickness of the semiconductor layer 103 is substantially equal to the height of the semiconductor fins to be formed.
  • the semiconductor layer 103 is formed of a portion of the semiconductor substrate 101 above the P well 102a and the N well 102b.
  • the semiconductor layer 103 is formed of a layer that is epitaxially grown over the P-well 102a and the N-well 102b.
  • a photoresist layer PR1 is formed on the semiconductor layer 103, for example, by spin coating, and the photoresist layer PR1 is formed to define a shape of the semiconductor fin by a photolithography process including exposure and development therein (for example) , strip) pattern.
  • the exposure of the semiconductor layer 103 is removed by dry etching using a photoresist layer PR1 as a mask, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution.
  • openings are formed in the P well 102a and the N well 102b as shown in FIG.
  • the semiconductor layer 103 is defined between the openings as a semiconductor fin 103a for an N-type FinFET and a semiconductor fin 103b for a P-type FinFET.
  • the etching time it is possible to control the depth of the opening.
  • the opening is shown with its bottom located in P well 102a and N well 102b.
  • the length of the etch is such that the bottom of the opening is in the semiconductor substrate 101 below the P-well 102a and the N-well 102b.
  • the doping-through blocking layer opposite to the doping type of the source/drain regions may be formed in the lower portion of the semiconductor layer 103 by ion implantation before the formation of the semiconductor fins 103a and 103b.
  • the semiconductor fins 103a and 103b are formed by the upper portion of the semiconductor layer 103.
  • the doped through-blocking layer can reduce leakage current between the source/drain regions via the semiconductor substrate.
  • the photoresist layer PR1 is removed by dissolving or ashing in a solvent.
  • a photoresist layer PR2 is formed on the surface of the semiconductor structure by spin coating, for example.
  • the photoresist layer PR2 is patterned to define shallow trenches between the N-type FinFET and the P-type FinFET.
  • the photoresist layer PR2 at least blocks the previously formed semiconductor fins 103a and 103b.
  • the exposure of the semiconductor layer 103 is removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, using the photoresist layer PR2 as a mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, using the photoresist layer PR2 as a mask.
  • a shallow trench is formed between the P well 102a and the N well 102b, as shown in FIG.
  • the depth of the shallow trench can be changed by controlling the etching time.
  • the shallow trench separates the active regions of the N-type FinFET and the P-type FinFET.
  • the shallow trench is shown with its bottom located in P well 102a and N well 102b.
  • the bottom of the opening can be located in the semiconductor substrate 101 below the P-well 102a and the N-well 102b. Then, the photoresist layer PR2 is removed by dissolving or ashing in a solvent.
  • the first insulating layer 104 (for example, silicon oxide) is formed on the surface of the semiconductor structure by a known deposition process such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or the like. ).
  • the first insulating layer 104 covers the semiconductor fins and fills openings for defining the semiconductor fins and shallow trenches for separating the N-type FinFETs and the P-type FinFETs, as shown in FIG. If necessary, the first insulating layer 104 may be subjected to chemical mechanical polishing (CMP) to obtain a flat surface.
  • CMP chemical mechanical polishing
  • the first insulating layer 104 can be formed by a high density plasma deposition (HDP) process.
  • HDP high density plasma deposition
  • a portion of the thickness of the first insulating layer 104 on top of the semiconductor fins 103a and 103b is much smaller than a portion of the thickness of the opening between the semiconductor fins 103a and 103b, preferably a semiconductor fin.
  • the thickness of the portion on the top of the 103a and 103b is less than one third, preferably less than one quarter, of the thickness of the portion located within the opening between the semiconductor fins 103a and 103b, and preferably the first insulating layer 104 is on the semiconductor fin
  • the thickness of the portion on the top of the 103a and 103b is less than half the pitch (i.e., the opening width) between the semiconductor fins 103a and 103b.
  • a portion of the first insulating layer 104 within the opening has a thickness greater than 80 nm, and a portion of the first insulating layer 104 at the top of the semiconductor fins 103a and 103b has a thickness of less than 20 nm.
  • the first insulating layer 104 is etched back by a selective etching process (for example, reactive ion etching) as shown in FIG.
  • a selective etching process for example, reactive ion etching
  • This etching not only removes the portion of the first insulating layer 104 on the top of the semiconductor fins 103a and 103b, but also reduces the thickness of the portion of the first insulating layer 104 located inside the opening.
  • the etching time is controlled such that the top of the portion of the first insulating layer 104 located inside the opening is flush with or lower than the bottoms of the semiconductor fins 103a and 103b, so that the top and side walls of the semiconductor fins 103a and 103b can be completely exposed.
  • a dummy gate dielectric 105 e.g., silicon oxide or silicon nitride
  • the dummy gate dielectric 105 is a silicon oxide layer of about 0.8-1. 5 nm thick.
  • the dummy gate dielectric 105 covers the top and sides of the semiconductor fins 103a and 103b.
  • a dummy gate conductor 106 e.g., polysilicon or amorphous silicon layer (a _Si)
  • the dummy gate conductor 106 can be chemical mechanically polished (CMP) to obtain a flat surface.
  • Patterning is then performed using a photoresist mask (not shown) or a hard mask (not shown) to form a dummy gate stack.
  • the exposed portions of the dummy gate conductors 106 are selectively removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution therein,
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution therein.
  • the dummy gate conductors 106a and 106b of the N-type FinFET and the P-type FinFET are formed, respectively.
  • Figures 7a and 7b are shown.
  • the dummy gate conductors 106a and 106b of the N-type FinFET and the P-type FinFET are two strip patterns spaced apart and spanning the semiconductor fins 103a and 103b, respectively, but the dummy gate conductors 106a and 106b It can also be other shapes.
  • a nitride layer is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the nitride layer is a silicon nitride layer having a thickness of about 5-30 nm.
  • the laterally extending portion of the nitride layer is removed by an anisotropic etching process (eg, reactive ion etching) such that the nitride layer remains on a vertical portion on the side of the dummy gate conductors 106a and 106b, thereby forming a gate spacer 107a and 107b, as shown in Figures 8a and 8b.
  • the heights of the dummy gate conductors 106a and 106b are, for example, twice or more the heights of the semiconductor fins 103a and 103b. Due to the shape factor, the thickness of the nitride layer on the sides of the semiconductor fins 103a and 103b is smaller than the thickness of the nitride layer on the side faces of the dummy gate conductors 106a and 106b, so that the sides of the semiconductor fins 103a and 103b can be completely removed in this etching step. A nitride layer on the wall. Otherwise, the thickness of the nitride layer on the side faces of the semiconductor fins 103a and 103b is too large to hinder the formation of the gate spacer.
  • the nitride layer on the sides of the semiconductor fins 103a and 103b may be further removed using an additional mask.
  • the gate spacers 107a and 107b surround the dummy gate conductors 106a and 106b without being formed on the sidewalls of the semiconductor fins 103a and 103b.
  • source/drain ion implantation may be performed using the dummy gate conductor and its side walls as a hard mask, and activation annealing is performed to form an N-type FinFET in the semiconductor fins 103a and 103b. Source/drain regions (not shown) and source/drain regions (not shown) of the P-type FinFET.
  • a second insulating layer 108 (e.g., silicon oxide) is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the second insulating layer 108 covers the dummy gate conductors 106a and 106b and the semiconductor fins 103a and 103b.
  • the second insulating layer 108 is subjected to chemical mechanical polishing (CMP) to obtain a flat surface.
  • CMP chemical mechanical polishing
  • the CMP can remove portions of the second insulating layer 108 at the top of the dummy gate conductors 106a and 106b, and a portion of the dummy gate conductors 106a and 106b can be further removed as shown in Figs. 9a and 9b.
  • the second insulating layer 108 and the gate spacers 107a and 107b as hard masks, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by using an etchant solution therein
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by using an etchant solution therein
  • the wet etch selectively removes the dummy gate conductors 106a and 106b and further removes portions of the dummy gate dielectric 105 under the dummy gate conductors 106a and 106b, as shown in FIG.
  • dummy gate conductors 106a and 106b are comprised of polysilicon and, in this etch, are removed by wet etching using a suitable etchant (e.g., methylammonium hydroxide, abbreviated as TMAH) solution. This etching forms a gate opening that exposes the top surface and sidewalls of the semiconductor fins 103a and 103b.
  • a suitable etchant e.g., methylammonium hydroxide, abbreviated as TMAH
  • interfacial oxide layer 109 (eg, silicon oxide) is formed on the sidewalls.
  • the interfacial oxide layer 109 is formed by rapid thermal oxidation of 20-120 s at a temperature of about 600-900 °C.
  • the interfacial oxide layer 109 is formed by chemical oxidation in an aqueous solution containing ozone (0 3 ).
  • the surfaces of the semiconductor fins 103a and 103b are cleaned prior to forming the interfacial oxide layer 109.
  • the cleaning consists of first performing a conventional cleaning, then immersing in a mixed solution comprising hydrofluoric acid, isopropanol and water, then rinsing with deionized water, and finally drying.
  • the composition of the mixed solution is hydrofluoric acid: isopropyl alcohol: water has a volume ratio of about 0. 2-1. 5%: 0. 01-0. 10%: 1, and the immersion time is about 1-10 minutes.
  • This cleaning can obtain a clean surface of the semiconductor fins 103a and 103b, suppress generation of natural oxides on the silicon surface, and particle contamination, thereby facilitating formation of a high quality interface oxide layer 109.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • M0CVD metal organic chemical vapor deposition
  • PVD physical vapor deposition
  • a conformal high-k gate dielectric 110 and a first metal gate layer 111 are sequentially formed as shown in FIG.
  • the high-k gate dielectric 110 is composed of a suitable material having a dielectric constant greater than SiO 2 , and may be, for example, selected from the group consisting of Zr0 2 , ZrON, ZrSiON, HfZrO, HfZrON, HfON, Hf0 2 , HfA10, HfA10N, HfSiO, HfSiON, HfLaO HfLaON and A combination of any combination.
  • the first metal gate layer 111 is composed of a suitable material that can be used to form a metal gate, and may be, for example, one selected from the group consisting of TiN, TaN, MoN, WN, TaC, and TaCN.
  • the interface oxide layer 109 is, for example, a silicon oxide layer having a thickness of about 0.2 to 0.8 nm.
  • the high-k gate dielectric 110 is, for example, an Hf0 2 layer having a thickness of about 2 to 5 nm, and the first metal gate layer 111 is, for example, a TiN layer having a thickness of about 1 to 1 nm.
  • a high K gate dielectric post deposition annealing may be included between the formation of the high K gate dielectric 110 and the formation of the first metal gate layer 111 to improve the quality of the high K gate dielectric, which facilitates subsequent formation.
  • the first metal gate layer 111 obtains a uniform thickness.
  • post-deposition annealing is performed by rapid thermal annealing of 5-100 s at a temperature of 500-1000 °C.
  • a patterned photoresist mask (not shown) is formed by a photolithography process including exposure and development to block the active region of the P-type FinFET and expose the active region of the N-type FinFET.
  • a negative dopant is implanted into the first metal gate layer 111 of the active region of the N-type FinFET by conformal doping, as shown in Figure 12a.
  • the negative dopant for the metal gate may be one selected from the group consisting of P, As, Sb, La, Er, Dy, Gd, Sc, Yb, Er and P Tb.
  • the energy and the dose of the ion implantation are controlled such that the implanted dopant is only distributed in the first metal gate layer 111 without entering the high-k gate dielectric 110a, and the energy and dose of the ion implantation are controlled such that the first metal gate layer 111 There is a suitable doping depth and concentration to achieve the desired threshold voltage.
  • the energy of the ion implantation is about 0. 2KeV-30KeV
  • the dose It is about lE13-lE15cm- 2 .
  • the photoresist mask is removed by ashing or dissolving.
  • a patterned photoresist mask (not shown) is formed by a photolithography process including exposure and development to block the active region of the N-type FinFET and expose the active region of the P-type FinFET.
  • a positive dopant is implanted into the first metal gate layer 111 of the active region of the P-type FinFET by conformal doping, as shown in Figure 12b.
  • the positive dopant for the metal gate may be one selected from the group consisting of In, B, BF 2 , Ru, W, Mo, Al, Ga, Pt.
  • the energy and dose of ion implantation are controlled such that the implanted dopant is only distributed in the first metal gate layer 111 without entering the high K gate dielectric 110b.
  • the first metal gate layer 111 is made to have a suitable doping depth and concentration to obtain a desired threshold voltage.
  • the energy of ion implantation is about 0.2KeV-30KeV, and the dose is about lE13_lE15cm- 2 .
  • the photoresist mask is removed by ashing or dissolving.
  • a second metal gate layer 112 is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • Chemical mechanical polishing (CMP) is performed with the second insulating layer 108 as a stop layer to remove a portion of the second metal gate layer outside the gate opening, leaving only a portion located inside the gate opening, as shown in FIGS. 13a and 13b.
  • the second metal gate layer may be composed of the same or different material as the first metal gate layer, and may be, for example, one selected from the group consisting of W, TiN, TaN, MoN, WN, TaC, and TaCN.
  • the second metal gate layer is, for example, a W layer having a thickness of about 2 to 30 nm.
  • the gate stack of the N-type FinFET is shown in the drawing to include a second metal gate layer 112a, a first metal gate layer 111a, a high-k gate dielectric 110a and an interfacial oxide layer 109a
  • the gate stack of the P-type FinFET includes a second metal The gate layer 112b, the first metal gate layer 111b, the high-k gate dielectric 110b, and the interface oxide layer 109b.
  • the above semiconductor structure is in an inert atmosphere (for example, N 2 ) or a weakly reducing atmosphere (for example, a mixed atmosphere of N 2 and a mixture) Annealing is performed.
  • the annealing is carried out in an oven at an annealing temperature of about 350 ° C to 700 ° C and an annealing time of about 5 to 30 minutes. Annealing drives the implanted dopants to diffuse and accumulate at the upper and lower interfaces of the high-k gate dielectrics 110a and 110b, and further forms an electric dipole by interfacial reaction at the lower interface of the high-k gate dielectrics 110a and 110b.
  • the upper interface of the high-k gate dielectrics 110a and 110b refers to the interface with the upper first metal gate layers 111a and 111b
  • the lower interface of the high-k gate dielectrics 110a and 110b refers to the interface oxide with the lower interface.
  • This annealing changes the distribution of the dopant.
  • the dopants accumulated at the upper interface of the high-k gate dielectrics 110a and 110b change the properties of the metal gate, so that the effective work function of the corresponding MOSFET can be advantageously adjusted.
  • Number the dopants accumulated at the lower interface of the high-k gate dielectrics 110a and 110b also form an electric dipole of a suitable polarity by interfacial reaction, so that the effective work function of the corresponding MOSFET can be further advantageously adjusted.
  • the result of the effective work function of the gate stack of the P-type FinFET may be 4. 8 eV to 5.
  • the effective work function of the gate stack of the P-type FinFET may be 4. 8 eV to 5. 2

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Abstract

公开了一种半导体器件及其制造方法。半导体器件的制造方法包括：在半导体衬底上形成半导体鳍片；在半导体鳍片的顶部表面和侧壁上形成界面氧化物层；在界面氧化物层上形成高K栅介质；在高K栅介质上形成第一金属栅层；通过共形掺杂在第一金属栅层中注入掺杂剂；以及进行退火以使掺杂剂扩散并聚积在高K栅介质与第一金属栅层之间的上界面和高K栅介质与界面氧化物之间的下界面处，并且在高K栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。

Description

半导体器件及其制造方法 本申请要求了 2012年 11月 30 日提交的、 申请号为 201210505754. 3、 发明名 称为"半导体器件及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结 合在本申请中。 技术领域
本发明涉及半导体技术领域， 具体地涉及包括金属栅和高 K栅介质的半导体器 件及其制造方法。 背景技术
随着半导体技术的发展， 金属氧化物半导体场效应晶体管 （M0SFET) 的特征尺 寸不断减小。 M0SFET的尺寸缩小导致栅电流泄漏的严重问题。 高 K栅介质的使用使 得可以在保持等效氧化物厚度（EOT)不变的情形下增加栅介质的物理厚度， 因而可 以降低栅隧穿漏电流。 然而， 传统的多晶硅栅与高 K栅介质不兼容。 金属栅与高 K 栅介质一起使用不仅可以避免多晶硅栅的耗尽效应， 减小栅电阻， 还可以避免硼穿 透， 提高器件的可靠性。 因此， 金属栅和高 K栅介质的组合在 M0SFET中得到了广泛 的应用。 金属栅和高 K栅介质的集成仍然面临许多挑战， 如热稳定性问题、 界面态 问题。特别是由于费米钉扎效应， 采用金属栅和高 K栅介质的 M0SFET难以获得适当 低的阈值电压。
在集成 N型和 P型 FinFET的 CMOS应用中，为了获得合适的阈值电压， N型 FinFET 的有效功函数应当在 Si的导带底附近 （4. leV左右）， P型 FinFET的有效功函数应 当在 Si的价带顶附近 （5. 2eV左右）。 可以针对 N型 FinFET和 P型 FinFET分别选 择不同的金属栅和高 K栅介质的组合以实现所需的阈值电压。 结果， 需要在一个芯 片上形成双金属栅和双高 K栅介质。 在半导体器件的制造期间， 分别针对 N型和 P 型 FinFET的金属栅和高 K栅介质执行各自的光刻和蚀刻步骤。 因此， 用于制造包括 双金属栅和双栅介质的半导体器件的方法工艺复杂， 不适合批量生产， 这进一步导 致成本高昂。 发明内容 本发明的目的是提供一种改进的半导体器件及其方法， 其中可以在制造过程调 节半导体器件的有效功函数。
根据本发明的一方面， 提供一种半导体器件的制造方法， 所述方法包括： 在半 导体衬底上形成半导体鰭片；在半导体鰭片的顶部表面和侧壁上形成界面氧化物层； 在界面氧化物层上形成高 K栅介质； 在高 K栅介质上形成第一金属栅层； 通过共形 掺杂在第一金属栅层中注入掺杂剂； 以及进行退火以使掺杂剂扩散并聚积在高 κ栅 介质与第一金属栅层之间的上界面和高 κ栅介质与界面氧化物之间的下界面处， 并 且在高 κ栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。 在优选 的实施例中， 所述半导体器件包括在一个半导体衬底上形成的 N型 FinFET和 P型 FinFET, 并且在 N型 FinFET的第一金属栅层注入用于减小有效功函数的掺杂剂， 在 P型 FinFET的第一金属栅层中注入于增加有效功函数的掺杂剂。
根据本发明的另一方面， 提供一种半导体器件， 包括： 位于半导体衬底上的半 导体鰭片； 位于半导体鰭片的顶部表面和侧壁上的界面氧化物层； 位于界面氧化物 层上的高 K栅介质； 以及位于高 K栅介质上的第一金属栅层， 其中掺杂剂分布在高 κ栅介质与第一金属栅层之间的上界面和高 κ栅介质与界面氧化物之间的下界面处， 并且在高 κ栅介质与界面氧化物之间的下界面处通过界面反应产生电偶极子。
根据本发明， 一方面， 在高 κ栅介质的上界面处聚积的掺杂剂改变了金属栅的 性质， 从而可以有利地调节相应的 MOSFET的有效功函数。 另一方面， 在高 K栅介质 的下界面处聚积的掺杂剂通过界面反应还形成合适极性的电偶极子， 从而可以进一 步有利地调节相应的 MOSFET的有效功函数。该方法获得的半导体器件的性能表现出 良好的稳定性和显著的调节金属栅的有效功函数的作用。针对两种类型的 MOSFET选 择不同的掺杂剂， 可以减小或增加有效功函数。 在 CMOS器件中， 仅仅通过改变掺杂 剂， 就可以分别调节两种类型的 MOSFET的阈值电压， 而不需要分别使用金属栅和栅 介质的不同组合。 因此， 该方法可以省去相应的沉积步骤和掩模及刻蚀步骤， 从而 实现了简化工艺且易于大量生产。 共形掺杂改善了掺杂剂在半导体鰭片的顶部和侧 壁附近的分布均匀性， 从而可以抑制阈值电压的随机波动。
在优选的实施例中， 该半导体器件还包括在半导体衬底和半导体鰭片之间的掺 杂穿通阻止层， 或者位于半导体衬底中的阱。 该掺杂穿通阻止层和 /或阱与源 /漏区 的掺杂类型相反， 以减小源 /漏区之间的漏电流。 附图说明
为了更好的理解本发明， 将根据以下附图对本发明进行详细描述：
图 1至 13示意性地示出根据本发明的方法的一个实施例在制造半导体器件的各 个阶段的半导体结构的截面图。 具体实施方式
以下将参照附图更详细地描述本发明。 在下文的描述中， 无论是否显示在不同 实施例中， 类似的部件采用相同或类似的附图标记表示。 在各个附图中， 为了清楚 起见， 附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处 理工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那 样， 可以不按照这些特定的细节来实现本发明。 除非在下文中特别指出， 半导体器 件中的各个部分可以由本领域的技术人员公知的材料构成， 或者可以采用将来开发 的具有类似功能的材料。
在本申请中， 术语 "半导体结构"指在经历制造半导体器件的各个步骤后形成 的半导体衬底和在半导体衬底上已经形成的所有层或区域。 术语 "源 /漏区"指一个 M0SFET的源区和漏区二者， 并且采用相同的一个附图标记标示。 术语 "负掺杂剂" 是指用于 N型 FinFET的可以减小有效功函数的掺杂剂。 术语 "正掺杂剂"是指用于 P型 FinFET的可以增加有效功函数的掺杂剂。
根据本发明的一个实施例， 参照图 1至 13说明制造半导体器件的方法， 其中， 在图 7a-9a中示出了半导体结构的俯视图及截面图的截取位置， 在图 1_6、 7b_9b和 13a中示出在半导体鰭片的宽度方向上沿线 A-A截取的半导体结构的截面图， 在图 10-11、 12B和 13b中示出在 P型 FinFET的半导体鰭片的长度方向上沿线 B-B截取 的半导体结构的截面图， 图 12A中示出在 N型 FinFET的半导体鰭片的长度方向上沿 线 C-C截取的半导体结构的截面图。 该半导体器件是包括在一个半导体衬底上形成 的 N型 FinFET禾口 P型 FinFET的 CMOS器件。
在图 1中所示的半导体结构已经完成了一部分 CMOS工艺。在半导体衬底 101(例 如， Si衬底）中的一定深度位置形成用于 N型 FinFET的 P阱 102a和用于 P型 FinFET 的 N阱 102b。 在图 1所示的示例中， 将 P阱 102a和 N阱 102b示出为矩形并且直接 邻接， 但实际上 P阱 102a和 N阱 102b可能没有清晰的边界， 并且可能由半导体衬 底 101的一部分隔开。 半导体层 103 (例如， Si ) 位于 P阱 102a和 N阱 102b上方， 并且将用于形成半导体鰭片。 半导体层 103的厚度大致等于将要形成的半导体鰭片 的高度。在一个示例中，半导体层 103由半导体衬底 101位于 P阱 102a和 N阱 102b 上方的一部分形成。 在替代的示例中， 半导体层 103由在 P阱 102a和 N阱 102b上 方外延生长的层形成。
然后， 例如通过旋涂在半导体层 103上形成光致抗蚀剂层 PR1， 并通过其中包 括曝光和显影的光刻工艺将光致抗蚀剂层 PR1形成用于限定半导体鰭片的形状 （例 如， 条带） 的图案。
采用光致抗蚀剂层 PR1作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、激光烧蚀， 或者通过使用蚀刻剂溶液的湿法蚀刻， 去除半导体层 103 的暴露部分， 在 P阱 102a和 N阱 102b中形成开口， 如图 2所示。 在开口之间将半 导体层 103限定为用于 N型 FinFET的半导体鰭片 103a和用于 P型 FinFET的半导体 鰭片 103b。通过控制蚀刻的时间， 可以控制改变开口的深度。在图 2所示的示例中， 将开口示出为其底部位于 P阱 102a和 N阱 102b中。 在替代的示例中， 通过延长蚀 刻的时间， 使得开口的底部位于 P阱 102a和 N阱 102b下方的半导体衬底 101中。
优选地， 在形成半导体鰭片 103a和 103b之前， 可以通过离子注入在半导体层 103 的下部形成与源 /漏区的掺杂类型相反的掺杂穿通阻止层。 半导体鰭片 103a和 103b 由半导体层 103 的上部形成。 该掺杂穿通阻止层可以减小源 /漏区之间经由半 导体衬底的漏电流。
然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层 PR1。 例如通过旋涂在半导 体结构的表面上形成光致抗蚀剂层 PR2。 将光致抗蚀剂层 PR2 形成用于限定 N型 FinFET和 P型 FinFET之间的浅沟槽的图案。 光致抗蚀剂层 PR2至少遮挡先前形成 的半导体鰭片 103a和 103b。
采用光致抗蚀剂层 PR2作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、激光烧蚀， 或者通过使用蚀刻剂溶液的湿法蚀刻， 去除半导体层 103 的暴露部分， 在 P阱 102a和 N阱 102b之间中形成浅沟槽， 如图 3所示。 通过控制 蚀刻的时间， 可以改变浅沟槽的深度。 该浅沟槽隔开 N型 FinFET和 P型 FinFET的 有源区。 在图 3所示的示例中， 将浅沟槽示出为其底部位于 P阱 102a和 N阱 102b 中。 在替代的示例中， 通过延长蚀刻的时间， 使得开口的底部可以位于 P阱 102a和 N阱 102b下方的半导体衬底 101中。 然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层 PR2。 通过已知的沉积工艺， 如电子束蒸发 （EBM)、 化学气相沉积 （CVD)、 原子层沉积 （ALD)、 溅射等， 在半导 体结构的表面上形成第一绝缘层 104 (例如， 氧化硅）。 第一绝缘层 104覆盖半导体 鰭片，并且填充用于限定半导体鰭片的开口以及用于隔开 N型 FinFET和 P型 FinFET 的浅沟槽，如图 4所示。如果需要，可以对第一绝缘层 104进行化学机械抛光（CMP)， 以获得平整的表面。
在一个示例中， 可以通过高密度等离子体沉积（HDP)工艺形成第一绝缘层 104。 通过控制工艺淀积参数， 使得第一绝缘层 104在半导体鰭片 103a和 103b的顶部上 的部分厚度远远小于位于半导体鰭片 103a和 103b之间的开口内的部分厚度， 优选 为半导体鰭片 103a和 103b的顶部上的部分厚度小于位于半导体鰭片 103a和 103b 之间的开口内的部分厚度的三分之一，优选小于四分之一，且优选为第一绝缘层 104 在半导体鰭片 103a和 103b的顶部上的部分的厚度小于半导体鰭片 103a和 103b之 间间距 （即开口宽度） 的一半。 在一个示例中， 第一绝缘层 104在开口内的部分的 厚度大于 80nm， 第一绝缘层 104位于半导体鰭片 103a和 103b顶部的部分的厚度小 于 20nm。
然后， 通过选择性的蚀刻工艺（例如， 反应离子蚀刻）， 回蚀刻第一绝缘层 104， 如图 5所示。 该蚀刻不仅去除第一绝缘层 104位于半导体鰭片 103a和 103b的顶部 上的部分， 而且减小第一绝缘层 104位于开口内的部分的厚度。 控制蚀刻的时间， 使得第一绝缘层 104的位于开口内的部分的顶部与半导体鰭片 103a和 103b的底部 齐平或更低， 从而可完全暴露半导体鰭片 103a和 103b的顶部和侧壁。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成假栅极电介质 105 (例如， 氧化硅或氮化硅）。 在一个示例中， 假栅极电介质 105为约 0. 8-1. 5nm厚的 氧化硅层。 假栅极电介质 105覆盖半导体鰭片 103a和 103b的顶部表面和侧面。 进 一步地， 通过上述已知的沉积工艺， 在半导体结构的表面上形成假栅导体 106 (例 如， 多晶硅或非晶硅层 （a _Si ))， 如图 6所示。 如果需要， 可以对假栅导体 106进 行化学机械抛光 （CMP)， 以获得平整的表面。
然后， 采用光致抗蚀剂掩模 （未示出） 或硬掩模 （未示出） 进行图案化以形成 假栅叠层。 在图案化中， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀 刻、 激光烧蚀， 或者通过其中使用蚀刻剂溶液的湿法蚀刻， 选择性地去除假栅导体 106的暴露部分， 分别形成 N型 FinFET和 P型 FinFET的假栅导体 106a和 106b， 如 图 7a和 7b所示。在图 7a所示的示例中， N型 FinFET和 P型 FinFET的假栅导体 106a 和 106b是两个隔开并且分别横跨半导体鰭片 103a和 103b的条带图案，但假栅导体 106a和 106b也可以是其他形状。
然后， 通过上述已知的沉积工艺， 在半导体结构的表面上形成氮化物层。 在一 个示例中， 该氮化物层为厚度约 5-30nm的氮化硅层。 通过各向异性的蚀刻工艺（例 如， 反应离子蚀刻）， 去除氮化物层的横向延伸的部分， 使得氮化物层位于假栅导体 106a和 106b的侧面上的垂直部分保留， 从而形成栅极侧墙 107a和 107b， 如图 8a 和 8b所示。假栅导体 106a和 106b的高度例如是半导体鰭片 103a和 103b的高度的 两倍或更大。 由于形状因子， 半导体鰭片 103a和 103b侧面上的氮化物层厚度比假 栅导体 106a和 106b的侧面上的氮化物层厚度小， 从而在该蚀刻步骤中可以完全去 除半导体鰭片 103a和 103b侧壁上的氮化物层。 否则， 半导体鰭片 103a和 103b侧 面上的氮化物层厚度太大可能妨碍形成栅极侧墙。 可以采用附加的掩模进一步去除 半导体鰭片 103a和 103b侧面上的氮化物层。 结果， 栅极侧墙 107a和 107b围绕假 栅导体 106a和 106b， 而没有形成在半导体鰭片 103a和 103b的侧壁上。
在形成栅极侧墙 107a和 107b之后， 可以采用假栅导体及其侧墙作为硬掩模进 行源 /漏离子注入， 并进行激活退火， 从而在半导体鰭片 103a和 103b中形成 N型 FinFET的源 /漏区 （未示出） 以及 P型 FinFET的源 /漏区 （未示出）。
然后， 通过上述已知的沉积工艺， 在半导体结构的表面上形成第二绝缘层 108 (例如，氧化硅）。第二绝缘层 108覆盖假栅导体 106a和 106b以及半导体鰭片 103a 和 103b。 对第二绝缘层 108进行化学机械抛光 （CMP)， 以获得平整的表面。 该 CMP 可以去除第二绝缘层 108位于假栅导体 106a和 106b的顶部的部分， 并且可以进一 步去除假栅导体 106a和 106b的一部分， 如图 9a和 9b所示。
然后， 以第二绝缘层 108以及栅极侧墙 107a和 107b作为硬掩模， 通过干法蚀 刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 或者通过其中使用蚀 刻剂溶液的湿法蚀刻， 选择性地去除假栅导体 106a和 106b， 并且进一步去除假栅 极电介质 105位于假栅导体 106a和 106b下方的部分，如图 10所示。在一个示例中， 假栅导体 106a和 106b由多晶硅组成， 并且在该蚀刻中， 通过其中使用合适的蚀刻 剂 （例如甲基氢氧化铵， 缩写为 TMAH) 溶液的湿法蚀刻去除。 该蚀刻形成暴露半导 体鰭片 103a和 103b的顶部表面和侧壁的栅极开口。
然后， 通过化学氧化或附加的热氧化， 在半导体鰭片 103a和 103b的暴露表面 和侧壁上形成界面氧化物层 109(例如，氧化硅）。在一个示例中，通过在约 600-900°C 的温度下进行 20— 120s的快速热氧化形成界面氧化物层 109。 在另一个示例中， 通 过含臭氧 （03) 的水溶液中进行化学氧化形成界面氧化物层 109。
优选地， 在形成界面氧化物层 109之前， 对半导体鰭片 103a和 103b的表面进 行清洗。 该清洗包括首先进行常规的清洗， 然后浸入包括氢氟酸、 异丙醇和水的混 合溶液中， 然后采用去离子水冲洗， 最后甩干。 在一个示例中， 该混合溶液的成分 为氢氟酸： 异丙醇： 水的体积比约为 0. 2-1. 5%: 0. 01-0. 10%： 1， 并且浸入时间约 为 1-10分钟。该清洗可以获得半导体鰭片 103a和 103b的洁净的表面， 抑制硅表面 自然氧化物的生成和颗粒污染， 从而有利于形成高质量的界面氧化物层 109。
然后，通过已知的沉积工艺，如 ALD (原子层沉积）、 CVD (化学气相沉积）、 M0CVD (金属有机化学气相沉积）、 PVD (物理气相沉积）、 溅射等， 在半导体结构的表面上 依次形成共形的高 K栅介质 110和第一金属栅层 111， 如图 11所示。
高 K栅介质 110由介电常数大于 Si02的合适材料构成， 例如可以是选自 Zr02、 ZrON、 ZrSiON、 HfZrO、 HfZrON、 HfON、 Hf02、 HfA10、 HfA10N、 HfSiO、 HfSiON、 HfLaO HfLaON及其任意组合的一种。 第一金属栅层 111由可以用于形成金属栅的合适材料 构成， 例如可以是选自 TiN、 TaN、 MoN、 WN、 TaC和 TaCN的一种。 在一个示例中， 界面氧化物层 109例如是厚度约为 0. 2-0. 8 nm的氧化硅层。 高 K栅介质 110例如是 厚度约 2-5nm的 Hf02层， 第一金属栅层 111例如是厚度约 1-lOnm的 TiN层。
优选地， 在形成高 K栅介质 110和形成第一金属栅层 111之间还可以包括高 K 栅介质沉积后退火 （post deposition annealing), 以改善高 K栅介质的质量， 这 有利于随后形成的第一金属栅层 111 获得均匀的厚度。 在一个示例中， 通过在 500-1000°C的温度进行 5-lOOs的快速热退火作为沉积后退火。
然后， 通过包含曝光和显影的光刻工艺， 形成含有图案的光致抗蚀剂掩模 （未 示出）， 以遮挡 P型 FinFET的有源区并暴露 N型 FinFET的有源区。采用该光致抗蚀 剂掩模， 采用共形掺杂 （conformal doping) 在 N型 FinFET的有源区的第一金属栅 层 111中注入负掺杂剂， 如图 12a所示。 用于金属栅的负掺杂剂可以是选自 P、 As、 Sb、 La、 Er、 Dy、 Gd、 Sc、 Yb、 Er禾 P Tb 的一种。 控制离子注入的能量和剂量， 使 得注入的掺杂剂仅仅分布在第一金属栅层 111中， 而没有进入高 K栅介质 110a， 并 且控制离子注入的能量和剂量， 使得第一金属栅层 111具有合适的掺杂深度和浓度 以获得期望的阈值电压。 在一个示例中， 离子注入的能量约为 0. 2KeV-30KeV， 剂量 约为 lE13-lE15cm— 2。 在该注入之后， 通过灰化或溶解去除光抗蚀剂掩模。
然后， 通过包含曝光和显影的光刻工艺， 形成含有图案的光致抗蚀剂掩模 （未 示出）， 以遮挡 N型 FinFET的有源区并暴露 P型 FinFET的有源区。采用该光致抗蚀 剂掩模， 采用共形掺杂 （conformal doping) 在 P型 FinFET的有源区的第一金属栅 层 111中注入正掺杂剂， 如图 12b所示。 用于金属栅的正掺杂剂可以是选自 In、 B、 BF2、 Ru、 W、 Mo、 Al、 Ga、 Pt 的一种。 控制离子注入的能量和剂量， 使得注入的掺 杂剂仅仅分布在第一金属栅层 111中， 而没有进入高 K栅介质 110b。 并且使得第一 金属栅层 111具有合适的掺杂深度和浓度， 以获得期望的阈值电压。在一个示例中， 离子注入的能量约为 0. 2KeV-30KeV， 剂量约为 lE13_lE15cm— 2。 在该注入之后， 通过 灰化或溶解去除光抗蚀剂掩模。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二金属栅层 112。 以第二绝缘层 108作为停止层进行化学机械抛光 （CMP)， 以去除第二金属栅层位于 栅极开口外的部分， 而仅仅保留位于栅极开口内的部分， 如图 13a和 13b所示。 第 二金属栅层可以由与第一金属栅层相同或不同的材料组成，例如可以是选自 W、 TiN、 TaN、MoN、WN、TaC和 TaCN的一种。在一个示例中，第二金属栅层例如是厚度约 2_30nm 的 W层。 在图中示出 N型 FinFET的栅叠层包括第二金属栅层 112a、 第一金属栅层 111a, 高 K栅介质 110a和界面氧化物层 109a， P型 FinFET的栅叠层包括第二金属 栅层 112b、 第一金属栅层 l l lb、 高 K栅介质 110b和界面氧化物层 109b。 尽管 N型 FinFET和 P型 FinFET的栅叠层由相同的层形成， 但两者的金属栅中包含相反类型 的掺杂剂对有效功函数起到相反的调节作用。
在针对金属栅的掺杂的步骤之后， 例如在形成第二金属栅层 113之前或之后， 上述半导体结构在惰性气氛 （例如 N2) 或弱还原性气氛 （例如 N2和 的混合气氛） 中进行退火。 在一个示例中， 在炉中进行退火， 退火温度约为 350°C-700°C， 退火 时间约为 5-30分钟。 退火驱使注入的掺杂剂扩散并聚积在高 K栅介质 110a和 110b 的上界面和下界面处， 并且进一步在高 K栅介质 110a和 110b的下界面处通过界面 反应形成电偶极子。 这里， 高 K栅介质 110a和 110b的上界面是指其与上方的第一 金属栅层 111a和 111b之间的界面， 高 K栅介质 110a和 110b的下界面是指其与下 方的界面氧化物层 109a和 109b之间的界面。
该退火改变了掺杂剂的分布。 一方面， 在高 K栅介质 110a和 110b的上界面处 聚积的掺杂剂改变了金属栅的性质，从而可以有利地调节相应的 M0SFET的有效功函 数。 另一方面， 在高 K栅介质 110a和 110b的下界面处聚积的掺杂剂通过界面反应 还形成合适极性的电偶极子，从而可以进一步有利地调节相应的 M0SFET的有效功函 数。 结果， N型 FinFET的栅叠层的有效功函数可以在 4. 1 eV至 4. 5 eV的范围内改 变， P型 FinFET的栅叠层的有效功函数可以在 4. 8 eV至 5. 2 eV的范围内改变。
在上文中并未描述制造半导体器件的所有细节， 例如源 /漏接触、 附加的层间电 介质层和导电通道的形成。本领域的技术人员熟知形成上述部分的标准 CMOS工艺以 及如何应用于上述实施例的半导体器件中， 因此对此不再详述。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。 对于本领域的技术人员明显可知的变型或更改， 均在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种半导体器件的制造方法， 所述方法包括：
在半导体衬底上形成半导体鰭片；
在半导体鰭片的顶部表面和侧壁上形成界面氧化物层；
在界面氧化物层上形成高 κ栅介质；
在高 κ栅介质上形成第一金属栅层；
通过共形掺杂在第一金属栅层中注入掺杂剂； 以及
进行退火以改变栅叠层的有效功函数， 其中栅叠层包括第一金属栅层、 高 κ栅 介质和界面氧化物层。
2、 根据权利要求 1所述的方法， 在形成半导体鰭片的步骤之前， 还包括在半导 体衬底和半导体鰭片之间形成掺杂穿通阻止层， 使得随后形成的半导体鰭片位于掺 杂穿通阻止层上。
3、根据权利要求 1所述的方法， 其中在形成半导体鰭片的步骤和形成界面氧化 物层的步骤之间还包括：
形成横跨半导体鰭片的假栅叠层， 假栅叠层包括假栅导体和位于假栅导体和半 导体鰭片之间的假栅极电介质；
形成围绕假栅导体的栅极侧墙；
在半导体鰭片中形成源 /漏区； 以及
去除假栅叠层以形成暴露半导体鰭片的顶部表面和侧壁的栅极开口。
4、根据权利要求 1所述的方法， 其中在第一金属栅层中注入掺杂剂的步骤和进 行退火的步骤之间还包括：
在第一金属栅层上形成第二金属栅层以填充栅极开口； 以及
去除高 K栅介质、 第一金属栅层和第二金属栅层位于栅极开口外的部分。
5、 根据权利要求 1所述的方法， 其中在第一金属栅层中注入掺杂剂的步骤中， 控制离子注入的能量和剂量使得掺杂剂仅仅分布在第一金属栅层中。
6、 根据权利要求 5所述的方法， 其中离子注入的能量约为 0. 2KeV-30KeV。
7、 根据权利要求 5所述的方法， 其中离子注入的剂量约为 lE13-lE15cm— 2。
8、根据权利要求 1所述的方法， 其中所述半导体器件包括在一个半导体衬底上 形成的 N型 FinFET和 P型 FinFET, 并且在第一金属栅层中注入掺杂剂的步骤包括： 在遮挡 P型 FinFET的情形下， 采用第一掺杂剂注入对 N型 FinFET的第一金属 栅层进行离子注入； 以及
在遮挡 N型 FinFET的情形下， 采用第二掺杂剂注入对 P型 FinFET的第一金属 栅层进行离子注入。
9、根据权利要求 8所述的方法， 其中第一掺杂剂是可以减小有效功函数的掺杂 剂。
10、 根据权利要求 9所述的方法， 其中第一掺杂剂是选 P、 As、 Sb、 La、 Er、 Dy、 Gd、 Sc、 Yb、 Er和 Tb的一种。
11、 根据权利要求 8所述的方法， 其中第二掺杂剂是可以增加有效功函数的掺 杂剂。
12、 根据权利要求 11所述的方法， 其中第二掺杂剂是选自 In、 B、 BF2、 Ru、 W、 Mo、 Al、 Ga、 Pt的一种。
13、根据权利要求 1所述的方法， 其中在惰性气氛或弱还原性气氛中执行退火， 退火温度约为 350°C-450°C， 退火时间约为 20-90分钟。
14、 一种半导体器件， 包括：
位于半导体衬底上的半导体鰭片；
位于半导体鰭片的顶部表面和侧壁上的界面氧化物层；
位于界面氧化物层上的高 K栅介质； 以及
位于高 K栅介质上的第一金属栅层，
其中掺杂剂分布在高 K栅介质与第一金属栅层之间的上界面和高 K栅介质与界 面氧化物之间的下界面处， 并且在高 K栅介质与界面氧化物之间的下界面处通过界 面反应产生电偶极子。
15、 根据权利要求 14所述的半导体器件， 还包括： 位于半导体衬底和半导体鰭 片之间的掺杂穿通阻止层。
16、 根据权利要求 14所述的半导体器件， 还包括：
位于第一金属栅层上的第二金属栅层；
栅极侧墙， 使得界面氧化物层、 高 K栅介质、 第一金属栅层和第二金属栅层由 栅极侧墙围绕； 以及
位于半导体鰭片中的源 /漏区。
17、 根据权利要求 14所述的半导体器件， 还包括： 位于半导体衬底中的阱，其中阱的掺杂类型与半导体器件的源 /漏区的掺杂类型 相反， 并且半导体鰭片位于阱上方。
18、根据权利要求 14所述的半导体器件， 包括在一个半导体衬底上形成的 N型 FinFET和 P型 FinFET, 其中 N型 FinFET中的第一掺杂剂可以减小有效功函数， P 型 FinFET中的第二掺杂剂可以增加有效功函数。
19、 根据权利要求 18所述的半导体器件， 其中第一掺杂剂是选 P、 As、 Sb、 La、 Er、 Dy、 Gd、 Sc、 Yb、 Er和 Tb的一种。
20、 根据权利要求 18所述的半导体器件， 其中第二掺杂剂是选自 In、 B、 BF2、 Ru、 W、 Mo、 Al、 Ga、 Pt的一种。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015111339A1 (de) * 2015-03-20 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und verfahren zum herstellen von dieser

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318574B2 (en) * 2014-06-18 2016-04-19 International Business Machines Corporation Method and structure for enabling high aspect ratio sacrificial gates
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US9583342B2 (en) * 2014-07-24 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET doping methods and structures thereof
US9812366B2 (en) * 2014-08-15 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of tuning work function for a semiconductor device
US9508719B2 (en) * 2014-11-26 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same
CN105720057A (zh) * 2014-12-02 2016-06-29 中国科学院微电子研究所 半导体器件
US9287403B1 (en) * 2014-12-05 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET and method for manufacturing the same
CN105990347B (zh) * 2015-01-30 2019-11-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9627277B2 (en) * 2015-06-09 2017-04-18 International Business Machines Corporation Method and structure for enabling controlled spacer RIE
US10050147B2 (en) 2015-07-24 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR102428659B1 (ko) * 2015-08-24 2022-08-04 삼성전자주식회사 반도체 소자의 제조 방법
US10032914B2 (en) 2015-10-20 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN106611710A (zh) 2015-10-22 2017-05-03 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9947592B2 (en) * 2015-11-16 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US9786737B2 (en) 2015-12-03 2017-10-10 International Business Machines Corporation FinFET with reduced parasitic capacitance
US9735156B1 (en) * 2016-01-26 2017-08-15 Samsung Electronics Co., Ltd. Semiconductor device and a fabricating method thereof
US10510608B2 (en) * 2016-03-04 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
US9608065B1 (en) 2016-06-03 2017-03-28 International Business Machines Corporation Air gap spacer for metal gates
US9768072B1 (en) * 2016-06-30 2017-09-19 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with reduced dimensional variations
CN107579108B (zh) * 2016-07-04 2020-06-09 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9741720B1 (en) * 2016-07-26 2017-08-22 Globalfoundries Inc. Higher ‘K’ gate dielectric cap for replacement metal gate (RMG) FINFET devices
KR20180059649A (ko) 2016-11-25 2018-06-05 삼성전자주식회사 반도체 장치의 제조 방법
CN108122840B (zh) * 2016-11-28 2020-12-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及制备方法、电子装置
US10347750B2 (en) * 2016-11-28 2019-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN108573927B (zh) * 2017-03-07 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109148290B (zh) * 2017-06-28 2020-12-04 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法
US10304835B1 (en) * 2018-08-15 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060071275A1 (en) * 2004-09-30 2006-04-06 Brask Justin K Nonplanar transistors with metal gate electrodes
US20100038721A1 (en) * 2008-08-18 2010-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process
US20100062590A1 (en) * 2008-09-05 2010-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Novel solution for polymer and capping layer removing with wet dipping in hk metal gate etching process
CN101924133A (zh) * 2009-04-14 2010-12-22 台湾积体电路制造股份有限公司 鳍式fet及其形成方法
US20110147839A1 (en) * 2009-12-17 2011-06-23 Toshiba America Electronic Components, Inc. Semiconductor device and method for manufacturing the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7629212B2 (en) * 2007-03-19 2009-12-08 Texas Instruments Incorporated Doped WGe to form dual metal gates
JP2009283685A (ja) * 2008-05-22 2009-12-03 Panasonic Corp 半導体装置およびその製造方法
US8237233B2 (en) * 2008-08-19 2012-08-07 International Business Machines Corporation Field effect transistor having a gate structure with a first section above a center portion of the channel region and having a first effective work function and second sections above edges of the channel region and having a second effective work function
CN102217074B (zh) * 2008-09-16 2015-08-12 台湾积体电路制造股份有限公司 鳍式场效应晶体管(finfet)
US8173499B2 (en) * 2009-06-12 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a gate stack integration of complementary MOS device
CN102074469B (zh) * 2009-11-25 2012-04-11 中国科学院微电子研究所 一种用于pmos器件的金属栅功函数的调节方法
CN102157554A (zh) * 2010-02-12 2011-08-17 中国科学院微电子研究所 鳍式晶体管结构及其制作方法
CN102280376B (zh) * 2010-06-08 2013-01-02 中国科学院微电子研究所 一种用于cmos器件的双金属栅双高介质的集成方法
US9269758B2 (en) * 2011-01-13 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Low TCR high resistance resistor
US8748271B2 (en) * 2011-03-11 2014-06-10 Globalfoundries Singapore Pte. Ltd. LDMOS with improved breakdown voltage
KR101850703B1 (ko) * 2011-05-17 2018-04-23 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8536038B2 (en) * 2011-06-21 2013-09-17 United Microelectronics Corp. Manufacturing method for metal gate using ion implantation
US8878310B2 (en) * 2012-01-20 2014-11-04 Texas Instruments Incorporated Flatband shift for improved transistor performance
CN102646599B (zh) * 2012-04-09 2014-11-26 北京大学 一种大规模集成电路中FinFET的制备方法
US8877623B2 (en) * 2012-05-14 2014-11-04 United Microelectronics Corp. Method of forming semiconductor device
US8841188B2 (en) * 2012-09-06 2014-09-23 International Business Machines Corporation Bulk finFET with controlled fin height and high-K liner
US9640385B2 (en) * 2015-02-16 2017-05-02 Applied Materials, Inc. Gate electrode material residual removal process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060071275A1 (en) * 2004-09-30 2006-04-06 Brask Justin K Nonplanar transistors with metal gate electrodes
US20100038721A1 (en) * 2008-08-18 2010-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process
US20100062590A1 (en) * 2008-09-05 2010-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Novel solution for polymer and capping layer removing with wet dipping in hk metal gate etching process
CN101924133A (zh) * 2009-04-14 2010-12-22 台湾积体电路制造股份有限公司 鳍式fet及其形成方法
US20110147839A1 (en) * 2009-12-17 2011-06-23 Toshiba America Electronic Components, Inc. Semiconductor device and method for manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015111339A1 (de) * 2015-03-20 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und verfahren zum herstellen von dieser
US9461043B1 (en) 2015-03-20 2016-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9786564B2 (en) 2015-03-20 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10157795B2 (en) 2015-03-20 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US10629491B2 (en) 2015-03-20 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor manufacturing method
DE102015111339B4 (de) 2015-03-20 2021-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und verfahren zum herstellen von dieser

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