TW201729340A - 多重閘極裝置 - Google Patents

多重閘極裝置 Download PDF

Info

Publication number
TW201729340A
TW201729340A TW105135763A TW105135763A TW201729340A TW 201729340 A TW201729340 A TW 201729340A TW 105135763 A TW105135763 A TW 105135763A TW 105135763 A TW105135763 A TW 105135763A TW 201729340 A TW201729340 A TW 201729340A
Authority
TW
Taiwan
Prior art keywords
layer
gate
epitaxial
epitaxial layer
field effect
Prior art date
Application number
TW105135763A
Other languages
English (en)
Inventor
江國誠
吳忠政
黃靖方
謝文興
梁英強
鍾政庭
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201729340A publication Critical patent/TW201729340A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一種半導體，包含第一電晶體和第二電晶體。第一電晶體包含第一和第二磊晶層，由第一半導體材料組成。第二磊晶層配置於第一磊晶層上方。第一電晶體也包含第一閘極介電層和第一金屬閘極層，第一閘極介電層環繞第一和第二磊晶層且從第一磊晶層的頂面延伸至第二磊晶層的底面，第一金屬閘極層環繞第一閘極介電層。第二電晶體包含由第一半導體材料組成的第三磊晶層及由第二半導體組成的第四磊晶層，第四磊晶層直接配置於第三磊晶層上。第二電晶體也包含第二閘極介電層，且配置於第三和第四磊晶層上方且第二金屬閘極層配置於第二閘極介電層上方。

Description

多重閘極裝置
本揭露內容實施例係有關一種半導體裝置，特別是關於一種具有多重閘極結構的半導體裝置。
電子產業正在面臨對於更小及更快的電子裝置的不斷增長的需求，同時這些電子裝置需要支援更多日益複雜和精密的功能。因此，半導體產業中存在製造低成本、高效能及低功率的積體電路(integrated circuits,ICs)的趨勢。目前為止，很大程度上是透過縮小半導體積體電路的尺寸(例如將特徵的尺寸最小化)來達成這些目標，從而提升生產效率及降低相關的成本。然而，這樣的微縮半導體也為製造半導體的製程帶來更多的複雜性。因此，為了使半導體積體電路和裝置持續地進步，需要製造半導體的製程和技術也有類似的進步。
近來，半導體產業引進多重閘極裝置，藉由增加閘極-通道的連接、降低關閉狀態(OFF-state)的電流且減少短通道效應(short-channel effects,SCEs)以提升對閘極的控制。
其中一種引進的多重閘極裝置是環繞式閘極電晶體(gate-all around transistor,GAA)。環繞式閘極裝置因其閘極結構能環繞著通道區域延伸，提供兩面或四面來接觸通道而得名。環 繞式閘極裝置能和傳統互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)的製程相容，而且環繞式閘極裝置的結構允許其更加地縮小，同時維持閘極的控制能力及減輕短通道效應。儘管現有製造環繞式閘極裝置的方法通常能夠滿足它們預期的目的，但在各方面都尚未完全令人滿意。例如，在維持對閘極的控制能力以及減輕短通道效應上仍然存在挑戰。
根據本揭露內容之多個實施方式，係提供一種裝置，包含第一電晶體及第二電晶體。第一電晶體具有第一導電類型，配置於半導體基板上。第一電晶體包含第一磊晶層、第二磊晶層、第一閘極介電層及第一金屬閘極層。第一磊晶層由第一半導體材料組成。第二磊晶層由第一半導體材料組成且配置於第一磊晶層上方。第一閘極介電層環繞第一磊晶層和第二磊晶層且從第一磊晶層的頂面延伸至第二磊晶層的底面，第一磊晶層的頂面背對半導體基板且第二磊晶層的底面面對半導體基板。第一金屬閘極層環繞第一閘極介電層，第一閘極介電層包含第一磊晶層和第二磊晶層。第二電晶體具有第二導電類型，配置於半導體基板上，第二導電類型和第一導電類型相反。第二電晶體包含第三磊晶層、第四磊晶層、第二閘極介電層及第二金屬閘極層。第三磊晶層由第一半導體材料組成。第四磊晶層由第二半導體材料組成且直接配置於第三磊晶層上方，第二半導體材料不同於第一半導體材料。第二閘極介電層配置於第三磊晶層和第四磊晶層上方。第二金屬閘極層配置於第二閘極介電層上方。
100‧‧‧方法
102、104、106、108、110、112、114、116、118、120、122、124、126、128、130、132、134‧‧‧步驟
200‧‧‧半導體裝置、多重閘極裝置
200N‧‧‧裝置
222‧‧‧抗擊穿佈植
210‧‧‧基板
212‧‧‧N型場效電晶體區域、第一區域
214‧‧‧P型場效電晶體區域、第二區域
214P‧‧‧裝置
310、310R、310RS‧‧‧磊晶堆疊
314‧‧‧第一磊晶層
316‧‧‧第二磊晶層
320‧‧‧硬遮罩層
325‧‧‧氧化層
326‧‧‧氮化層
410、410’‧‧‧鰭板元件、鰭板
414‧‧‧溝槽
510、510’‧‧‧淺溝槽隔離特徵
520‧‧‧虛設介電層
610‧‧‧虛設閘極堆疊、閘極堆疊
610’‧‧‧淺溝槽隔離特徵
614‧‧‧電極層
616‧‧‧閘極硬遮罩
618‧‧‧層、氧化層
619‧‧‧層、氮化層
620‧‧‧通道區域
630‧‧‧源極/汲極區域
730‧‧‧第一圖案化硬遮罩
810‧‧‧間隙
820‧‧‧間隔層
830‧‧‧第一源極/汲極特徵
835‧‧‧半導體材料
840‧‧‧第二圖案化硬遮罩
850‧‧‧第二源極/汲極特徵
855‧‧‧半導體材料
860‧‧‧第三圖案化硬遮罩
910‧‧‧層間介電層
920‧‧‧第一閘極溝槽
930‧‧‧第四圖案化硬遮罩
940‧‧‧間隙
1010‧‧‧第一最終閘極堆疊
1014‧‧‧高介電常數閘極介電層
1016‧‧‧第一閘極金屬層
1020‧‧‧第二閘極溝槽
1030‧‧‧第二最終閘極堆疊
1036‧‧‧第二閘極金屬層
由下文之詳細說明並同時參照附圖能夠最適當地理解本揭示內容之態樣。應注意，依據工業中之標凖實務，多個特徵並未按比例繪製。實際上，多個特徵之尺寸可任意增大或縮小，以便使論述明晰。
第1圖係根據本揭露內容一或多個態樣之製造多重閘極裝置或提供部分裝置的方法之流程圖，此裝置包含在閘極下方的隔離區域。
第2、3、4、5、6、7、8、9A、9B、9C、9D、10A、10B、11A、11B、12A、12B、13A、13B、14A、14B、15A、15B、16A、16B、17A及17B圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式的等角視圖。
第18A圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17A圖線段A-A等角視圖的剖面示意圖。
第18B圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17B圖線段B-B等角視圖的剖面示意圖。
第18C圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17C圖線段C-C等角視圖的剖面示意圖。
第19A圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17A圖線段A-A等角視圖的剖面示意圖。
第19B圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17B圖線段B-B等角視圖的剖面示意圖。
第19C圖係根據第1圖的方法的各種態樣之一種裝置200的實施方式，對應於第17C圖線段C-C等角視圖的剖面示意圖。
以下揭示內容提供眾多不同的實施例或實例以用於實施本揭露內容之不同特徵。下文中描述組件及排列之特定實例以簡化本揭示內容。此等組件及排列當然僅為例示實施例，且不意欲進行限制。例如，在下文之描述中，第一特徵形成在第二特徵上方或之上可包含其中第一特徵與第二特徵以直接接觸方式形成的實施例，且亦可包含其中在第一特徵與第二特徵之間形成額外特徵而使得第一特徵與第二特徵必非直接接觸之實施例。此外，本揭示內容在多個實例中使用重複的元件符號及/或字母。此重複是為了簡化及清楚之目的，而非意指所論述的各個實施例及/或構造之間的關係。
此外，在此使用諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等空間相對用語用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與其他元件或特徵結構的關係。該空間相對用語意欲涵蓋使用或操作中之元件在除了附圖描述的方向以外的不同方向。此裝置亦可被轉向(90°旋轉或其他方位)，且本文使用的空間相對用語可據此作類似的解釋。
需要注意的是，本揭露內容提供多重閘極電晶體的各種實施方式。多重閘極電晶體包含閘極結構形成於通道區域的至少兩面上的電晶體。這些多重閘極裝置可包含P型金屬氧化物半 導體的多重閘極裝置或N型金屬氧化物半導體的多重閘極裝置。此處可提供並參照的特定實施例為鰭式場效電晶體(FINFET)，因為它具有鰭狀結構。此處也提供一種多重閘極電晶體的參考實施方式，即環繞式閘極(gate-all-around,GAA)裝置。環繞式閘極裝置包含任何閘極結構或其部分形成於通道區域的四面上(例如環繞通道區域的一部分)的裝置。此處呈現的裝置也包含將通道區域配置於奈米線通道、條狀通道或/及其他適當的通道形態中的多個實施方式。此處提供的裝置的實施方式可具有一或多個通道區域(例如奈米線)，通道區域和單一且連續的閘極結構連接。然而，具有通常知識者將會理解這裡的教示適用於單一通道(例如單一奈米線)或/及任何數量的通道。
第1圖為製造半導體的方法100，方法100包含製造多重閘極裝置。多重閘極裝置是指具有至少一些閘極材料配置於此裝置的至少一通道的多個面上的裝置(例如半導體電晶體)。在某些實施例中，多重閘極裝置可為環繞式閘極裝置，此環繞式閘極裝置具有閘極材料配置於此裝置的至少一通道的至少四個面上。環繞式閘極裝置中的通道區域可為「奈米線」，奈米線包含各種幾何形狀(例如圓柱、條狀)和各種尺寸的通道區域。
第2圖至第17B圖為根據第1圖的方法100之各種階段之半導體裝置200的實施方式之等角視圖。第18A圖至第19C圖為根據第1圖的方法100之各種階段之半導體裝置200的實施方式剖面示意圖，分別對應至上述之等角視圖。如同此處討論的其他方法的實施方式和例示性的裝置，可使用CMOS技術流程製造部分的半導體裝置200，因此某些製程僅在此簡述。此外，例示性的 半導體裝置可包含各種其他裝置及特徵，例如其他類型的裝置，如附加電晶體(additional transistors)、雙載子接面電晶體(bipolar junction transistors)、電阻、電容、電感元件、二極體、保險絲、靜態隨機存取記憶體(static random access memory,SRAM)或/及其他邏輯電路等，但為了對本揭露內容的發明性概念有更佳的了解，這些都被簡化。在某些實施方式中，例示性的裝置包含多個半導體裝置(例如電晶體)，半導體裝置包含可相互連接的P型場效電晶體(P-type field-effect transistor,PFETs)、N型場效電晶體(N-type field-effect transistors,NFETs)等。此外，需要注意的是方法100的製程步驟包含任何參照附圖的敘述，連同本揭露內容提供的其他方法和例示性的圖式，都僅為例示性且不意欲超出所附專利範圍具體的內容。
請參照第1圖及第2圖，方法100起始於步驟102，使用抗擊穿(anti-punch through,APT)佈植222至基板210。在目前的實施方式中，基於裝置效能的考量，基板210包含第一區域212及分離的第二區域214。在某些實施方式中，第一區域212可包含N型場效電晶體區域而且第二區域214可包含P型場效電晶體區域。為了簡化，如圖所示，在揭露方法內容的第2-8圖中，繪示的方法100都執行於第一區域212和第二區域214。
在某些實施方式中，基板210可為半導體基板，例如矽基板。基板210可包含各種層，包含形成於半導體基板的導電層或絕緣層。基板210可包含各種摻雜型態，取決於設計上的需求。舉例來說，不同的摻雜分佈(例如n型井、p型井)可形成於基板210上及依不同裝置類型設計的區域(例如N型場效電晶體(NFET)、P 型場效電晶體(PFET))中。適當的摻雜可包含摻質的離子佈植或/及擴散製程。基板210基本上具有隔離特徵(例如淺溝槽隔離(shallow trench isolation,STI)特徵)插入於提供不同裝置類型的區域之間。基板210也可包含其他半導體，例如鍺、碳化矽、鍺化矽或鑽石。可替代地，基板210可包含化合物半導體或/及合金半導體。此外，基板210可選擇性地包含磊晶層(epitaxial layer,epi-layer)，可為了增強效能而施加應變於磊晶層；基板210也可包含絕緣層上覆矽(silicon-on-insulator,SOI)結構、或/及其他適當的強化特徵。
舉例來說，可執行抗擊穿佈植222於裝置的通道區的底下區域，避免擊穿或非期望的擴散。在某些實施方式中，執行第一微影製程(photolithography)步驟以圖案化P型的抗擊穿區域(P-type APT region)及執行第二微影製程步驟以圖案化N型的抗擊穿區域(N-type APT region)。舉例來說，在某些實施方式中，執行第一微影製程步驟包含形成光阻層(光阻)於基板210上方，曝光光阻形成圖案(例如P型抗擊穿佈植遮罩)，執行後曝光(post-exposure)烘烤製程，並且將光阻顯影以形成圖案化的光阻層。舉例而言，經由離子佈植製程佈植P型摻質形成P型的抗擊穿區域，P型摻質可包含硼、鋁、鎵、銦、或/及其他P型受體(acceptor)材料。之後，在某些實施方式中，可執行第二微影製程步驟，其中第二微影製程步驟可包含形成光阻層(光阻)於基板210上方，曝光光阻形成圖案(例如N型抗擊穿佈植遮罩)，執行後曝光烘烤製程，並且將光阻顯影以形成圖案化的光阻層。舉例而言，經由離子佈植製程佈植N型摻質形成N型的抗擊穿區域，N型摻質可包含 砷、磷、銻、或/及其他N型施體(donor)材料。此外，在各種實施方式中，抗擊穿佈植製程可具有高摻質濃度，舉例來說，摻質濃度介於1x1018cm-3至1x1019cm-3之間。在某些實施方式中，如下文所述，可有利地使用這樣的高抗擊穿摻質濃度，因為隔離層後續形成於抗擊穿佈植基板的上方，可作為摻質擴散阻障層。
請參照第1圖和第3圖，方法100進行至步驟104，形成磊晶堆疊(epitaxial stack)310於抗擊穿佈植後的基板210的上方，包含在N型場效電晶體區域212及P型場效電晶體區域214中。磊晶堆疊310包含第一磊晶層314和第二磊晶層316，具有第一組成的第一磊晶層314被多個具有第二組成的第二磊晶層316插入。第一和第二組成可為不同或相同。在一實施方式中，第一磊晶層314由鍺化矽組成，且第二磊晶層316由矽組成。然而，其他實施方式都是可能的，包含第一組成和第二組成具有不同的氧化率。在某些實施方式中，第一磊晶層314包含鍺化矽且第二磊晶層316包含矽。
第二磊晶層316或其部分可形成多重閘極裝置200的通道區域。舉例而言，第二磊晶層316可稱為「奈米線」，奈米線用於形成多重閘極裝置200(例如環繞式閘極裝置)的通道區域。這些「奈米線」也可用於形成多重閘極裝置200的部分源極/汲極特徵，如下文所述。下面會再討論使用第二磊晶層316定義裝置的一或多個通道。需要注意的是第二磊晶層316(奈米線)形成於N型場效電晶體212及P型場效電晶體214兩者的上方，第二磊晶層提供了製造裝置200的製程的簡易性。
需要注意的是，第3圖繪示第一磊晶層314的六個層和第二磊晶層316的五個層。這僅為了說明且並非為了限制。可以理解的是可形成任何數量的磊晶層於磊晶堆疊310中，層的數量取決於所欲之用於裝置200的通道區域的數量。在某些實施方式中，第二磊晶層316的數量介於2-10。在某些實施方式中，磊晶堆疊310最上面的磊晶層是第一磊晶層314。因此，第一磊晶層314的總數比第二磊晶層316的總數多一層。
以下將描述更細部的細節，在N型場效電晶體區域212中，各第二磊晶層316可作為後續的環繞式閘極裝置的第一通道區域，且可基於裝置效能的考量來選擇第二磊晶層316的厚度。第一磊晶層314可用於定義後續的環繞式閘極裝置的相鄰第一通道區域的間隙距離，且可基於裝置效能的考量來選擇第一磊晶層314的厚度。此外，在P型場效電晶體區域214中，各第一磊晶層314可作為後續的閘極堆疊裝置的第一通道區域，且可基於裝置效能的考量來選擇第一磊晶層314的厚度。第二磊晶層316可用於定義後續的閘極堆疊裝置的相鄰第二通道區域的距離，且可基於裝置效能的考量來選擇第二磊晶層316的厚度。在某些實施方式中，第二磊晶層316的厚度大於第一磊晶層314的厚度。舉例來說，第二磊晶層316厚度和第一磊晶層314厚度的比值(第二磊晶層316厚度/第一磊晶層314厚度)介於1.1至2。在一實施方式中，第一磊晶層314的厚度介於約2-6nm而且第一磊晶層316的厚度介於3-11nm。第一磊晶層314和第二磊晶層316的厚度基本上是均勻的。
舉例而言，可使用分子束磊晶製程(molecular beam epitaxial,MBE)、金屬有機化學氣相沉積(metalorganic chemical vapor deposition,MOCVD)製程、或/及其他適當的磊晶生長製程磊晶生長出磊晶堆疊310的層。在某些實施方式中，磊晶生長層可例如為第二磊晶層316，第二磊晶層316包含和基板210相同的材料。在某些實施方式中，第一磊晶生長層314和第二磊晶生長層316包含不同於基板210的材料。如同前文所述，至少在某些實施例中，第一磊晶層314包含磊晶生長鍺化矽(SiGe)層而且第二磊晶層316包含磊晶生長矽(Si)層。可替代地，在某些實施方式中，第一磊晶生長層314和第二磊晶生長層316中任何一個可包含其他材料，例如鍺、化合物半導體、合金半導體、或其組合；化合物半導體可例如為碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、或/及銻化銦；合金半導體可例如為SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP、或/及GaInAsP、或其組合。如前文所述，可基於不同的氧化程度、蝕刻選擇比性質來選擇第一磊晶生長層314和第二磊晶生長層316。在各種實施方式中，第一磊晶生長層314和第二磊晶生長層316中基本上是沒有摻質(例如外質摻質濃度(extrinsic dopant concentration)介於約0cm-3至1x1017cm-3)，舉例來說，在磊晶生長製程中不刻意執行摻雜。
如第3圖的實施例所示，硬遮罩(hard mask,HM)層320可形成於磊晶堆疊310上方。在某些實施方式中，硬遮罩層320包含氧化層325(例如襯墊氧化層，襯墊氧化層可包含矽)及氮化層326(例如襯墊氮化層，襯墊氧化層可包含Si3N4)形成於氧化層325上方。在某些實施例中，硬遮罩層320包含熱生長氧化層、化學氣相沉積(chemical vapor deposition,CVD)所沉積之氧化物、或/及原子層沉積(atomic layer deposition,ALD)所沉積之氧化物。 在某些實施方式中，硬遮罩層320包含使用化學氣相沉積或其他適當的技術沉積的氮化層。硬遮罩層320可使用於保護部分的基板210或/及磊晶堆疊310或/及用於定義如下文所述的圖案(例如鰭板元件)。
請參照第1圖及第4圖，方法100進行至步驟106，在N型場效電晶體區域212和P型場效電晶體區域214中，形成從基板210延伸出的鰭板元件410(也稱為鰭板)。在各種實施方式中，各鰭板410包含從基板210形成的一部分基板、磊晶堆疊的部份各磊晶層，包含磊晶層314和磊晶層316、及硬遮罩層320的一部分。
可使用適當的製程製造鰭板410，包含微影及蝕刻製程。微影製程可包含形成光阻層於基板210上方(例如第3圖的硬遮罩層320上方)，將光阻曝光形成圖案，執行後曝光烘烤製程，以及將光阻顯影以形成遮罩元件，遮罩元件包含光阻。在某些實施方式中，可使用電子束(electron beam,e-beam)微影製程執行圖案化光阻以形成遮罩元件。之後遮罩元件可用於保護基板210的區域及形成於基板210上的層，同時蝕刻製程穿過硬遮罩層320及磊晶堆疊310至基板210中，形成溝槽414於未被保護的區域，進而留下多個延伸的鰭板410。可使用乾式蝕刻(例如反應式離子蝕刻)、濕式蝕刻、或/及其組合蝕刻溝槽414。
可使用許多其他製造方法的實施方式在基板210上形成鰭板，包含，舉例來說，定義鰭板區域(例如使用遮罩或隔離區域)並將磊晶堆疊310磊晶生長成鰭板410的形式。在某些實施方式中，形成鰭板410可包含減少鰭板410寬度的修整(trim process)製程。修整製程可包含濕式或/及乾式蝕刻製程。
請參照第1圖和第5圖，方法100進行至步驟108，在N型場效電晶體區域212和P型場效電晶體區域214中形成淺溝槽隔離(shallow trench isolation,STI)特徵510於鰭板410之間。舉例來說，在某些實施方式中，先沉積介電層於基板210上方，使用介電材料填充溝槽414。在某些實施方式中，介電層可包含氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(fluorine-doped silicate glass,FSG)、低介電常數介電質、其組合、或/及其他適當的材料。在各種實施例中，可使用化學氣相沉積(CVD)製程、次大氣壓化學氣相沉積(subatmospheric CVD,SACVD)製程、可流動式化學氣相沉積(flowable CVD)、原子層沉積(ALD)製程、物理氣相沉積製程(physical vapor deposition,PVD)、或/及其他適當的製程沉積介電層。在某些實施方式中，舉例來說，在沉積介電層之後，可將裝置200退火以提升介電層的品質。在某些實施方式中，介電層(及後續形成的淺溝槽隔離特徵510)可包含多層結構，舉例來說，具有一或多個襯裡層。
在形成淺溝槽隔離特徵510中，在沉積介電層後，使用例如化學機械研磨(chemical mechanical polishing,CMP)製程將沉積的介電材料薄化及平坦化。化學機械研磨製程可平坦化介電層的頂面。在某些實施方式中，用於平坦化裝置200的頂面的化學機械研磨製程也可用於從各鰭板410移除硬遮罩層320。在某些實施方式中，可替代地使用適當的蝕刻製程(例如乾式或濕式蝕刻)執行移除硬遮罩層320。
請參照第1圖及第6圖，方法100進行至步驟110，在N型場效電晶體區域212和P型場效電晶體區域214中使淺溝槽隔 離特徵510凹陷成510’。淺溝槽隔離特徵510’插入於鰭板410之間，使鰭板410延伸高於凹陷的淺溝槽隔離特徵510’。在某些實施方式中，凹陷製程可包含乾式蝕刻製程、濕式蝕刻製程、或/及其組合。在某些實施方式中，控制凹陷的深度(例如控制蝕刻時間)以曝露出鰭板410上部的所欲高度，稱為410’。在某些實施方式中，鰭板410’包含磊晶堆疊310的各層。
請參照第1圖和第7圖，方法100進行至步驟112，在N型場效電晶體區域212和P型場效電晶體區域214中，形成虛設(dummy)介電層520於鰭板410’上方。在某些實施方式中，虛設介電層520可包含氧化矽、氮化矽、高介電常數介電材料、或/及其他適當的材料。在各種實施例中，可使用化學氣相沉積(CVD)製程、次大氣壓化學氣相沉積(subatmospheric CVD,SACVD)製程、可流動式化學氣相沉積(flowable CVD)、原子層沉積(ALD)製程、物理氣相沉積製程(physical vapor deposition,PVD)、或/及其他適當的製程沉積虛設介電層520。舉例而言，虛設介電層520可用於避免後續的製程傷害鰭板410’(例如後續形成虛設閘極堆疊的過程)。
請參照第1圖和第8圖，方法100進行至步驟114，在N型場效電晶體區域212和P型場效電晶體區域214中形成閘極堆疊610。在一實施方式中，閘極堆疊610是虛設(犧牲)閘極堆疊而且將會被裝置200後續製程階段中的最終閘極堆疊取代。尤其是，如下文所述，虛設閘極堆疊610在之後的製程階段中可被高介電常數(high K)介電層及金屬閘極(metal gate)堆疊取代。在某些實施方式中，虛設閘極堆疊610形成於基板210上方而且至少部分配置 於鰭板410’上方。虛設閘極堆疊610下方的鰭板410’的部分可稱為通道區域620。虛擬閘極堆疊610也可定義鰭板410’的源極/汲極(S/D)區域630，例如，鰭板410’鄰近通道區域620和鰭板410’相對側的區域。
在某些實施方式中，虛設閘極堆疊610包含虛設介電層520、電極層614及閘極硬遮罩616，閘極硬遮罩616可包含多層618及619(例如氧化層618及氮化層619)。在某些實施方式中，虛設閘極堆疊610不包含虛設介電層520，例如，在沉積虛設閘極堆疊610前移除虛設介電層520。在某些實施方式中，閘極堆疊包含額外的虛設閘極介電層增加或取代虛設介電層520。在某些實施方式中，使用各種製程步驟形成虛設閘極堆疊610，例如層沉積、圖案化、蝕刻及其他適當的製程步驟。例示性的層沉積製程包含化學氣相沉積(包含低壓化學氣相沉積及電漿增強化學氣相沉積)、物理氣相沉積、原子層氣相沉積、熱氧化、電子束蒸鍍(e-beam evaporation)、或其他適當的沉積技術、或其組合。舉例說明形成閘極堆疊，圖案化製程包含微影製程(例如光學微影或電子束微影)，微影製程可更包含塗覆光阻(例如旋轉塗覆)、軟烤、光罩對準、曝光、後曝光烘烤、光阻顯影、清洗、乾燥(例如旋轉乾燥或/及硬烤)、其他適當的微影技術、或/及其組合。在某些實施方式中，蝕刻製程可包含乾式蝕刻(例如反應式離子蝕刻)、濕式蝕刻、或/及其他蝕刻方式。
如前文所述，虛設閘極堆疊610可包含額外的閘極介電層。例如，虛設閘極堆疊610可包含氧化矽。可替代地或額外地，虛設閘極堆疊610的閘極介電層可包含氮化矽、高介電常數介電材 料或其他適當的材料。在某些實施方式中，電極層614可包含多晶矽(polysilicon)。在某些實施方式中，閘極硬遮罩616包含氧化層618，例如襯墊氧化層，襯墊氧化層包含氧化矽。在某些實施方式中，閘極硬遮罩616包含氮化層619，例如襯墊氮化層，襯墊氮化層可包含Si3N4、氮氧化矽、或/及碳化矽。
再次參照第8圖，在某些實施方式中，在形成虛設閘極610之後，從基板210曝露的區域，包含未被虛設閘極610覆蓋的鰭板410’，移除虛設介電層520。蝕刻製程可包含濕式蝕刻、乾式蝕刻、或/及其組合。
如前文所述，揭露製造方式的第2-8圖繪示在N型場效電晶體區域212和P型場效電晶體區域214上執行方法100。從第9A圖及以下圖式開始，本揭露內容繪示分別在於N型場效電晶體區域212中形成裝置200N及在P型場效電晶體區域214中形成裝置214P的不同製程步驟。
參照第1、9A及9B圖，方法100進行至步驟116，在N型場效電晶體區域212中的源極/汲極區域630中移除第一磊晶層314，同時用第一圖案化硬遮罩730覆蓋P型場效電晶體區域214。在某些實施方式中，在移除N型場效電晶體區域212中的第一磊晶層314之前，形成第一圖案化硬遮罩730覆蓋P型場效電晶體區域214。第一圖案化硬遮罩730可包含使用微影製程形成的圖案化光阻層。可替代地，可使用沉積硬遮罩層，再使用微影製程形成圖案化光阻層於硬遮罩層上方，並透過圖案化光阻層蝕刻硬遮罩材料層形成第一圖案化硬遮罩730。
在目前的實施方式中，在形成圖案化硬遮罩730後，從N型場效電晶體區域212中的源極/汲極區域630移除磊晶堆疊310的第一磊晶層314。為了清楚起見，在移除第一磊晶層314後，磊晶堆疊310稱為310R。第9A圖繪示間隙810取代磊晶層314(繪示於第8圖)。可使用周遭環境(例如空氣、氮氣)填充間隙810。在一實施方式中，使用選擇性濕式蝕刻製程移除第一磊晶層314。在某些實施方式中，選擇性濕式蝕刻製程包含APM蝕刻(例如氫氧化氨-過氧化氫-水的混和物)。在某些實施方式中，選擇性移除包含先氧化鍺化矽，再移除鍺化矽的氧化物(SiGeOx)。舉例來說，可使用O3清洗來氧化，然後使用蝕刻液例如NH4OH移除鍺化矽的氧化物(SiGeOx)。在一實施方式中，第一磊晶層314是鍺化矽而且第二磊晶層316是矽，能夠選擇性移除第一磊晶層314。
如第9C及9D圖所示，在移除N型場效電晶體區域212中的第一磊晶層314之後，使用蝕刻製程移除第一圖案化硬遮罩730。在一實施例中，第一圖案化硬遮罩730是光阻圖案，使用濕式去除光阻(wet stripping)或/及電漿灰化(plasma ashing)移除第一圖案化硬遮罩730。
參照第1圖及10A-10B圖，方法100進行至步驟118，形成間隔層820於N型場效電晶體區域212和P型場效電晶體區域214的上方。間隔層820可為形成於N型場效電晶體區域212和P型場效電晶體區域214上方的保形(conformal)介電層。間隔層820可形成間隔元件於虛設閘極堆疊610的側壁上。間隔層820也可填充上述步驟116移除磊晶層後提供的間隙810。為了清楚起見，在使用間隔層820填充間隙810後，磊晶堆疊310R稱為310RS。
間隔層820可包含介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽、氮碳化矽(SiCN)薄膜、碳氧化矽、SiOCN薄膜、或/及其組合。在某些實施方式中，間隔層820包含多層，例如主要間隔壁、襯裡層、及其類似物。舉例來說，可沉積介電材料於虛設閘極堆疊610上方形成間隔層820，使用的沉積製程例如化學氣相沉積製程、次大氣壓化學氣相沉積(subatmospheric CVD,SACVD)製程、可流動式化學氣相沉積(flowable CVD)、原子層沉積(ALD)製程、物理氣相沉積製程(physical vapor deposition,PVD)、或/及其他適當的製程沉積。在特定實施方式中，沉積之後可以回蝕(例如非等向性蝕刻)介電材料。
再次參照第1、10A及10B圖，方法100進行至步驟120，回蝕N型場效電晶體區域212和P型場效電晶體區域214中的間隔層820。在目前的實施方式中，回蝕間隔層820以曝露源極/汲極區域630中部分的鰭板410’。間隔層820可留在虛設閘極結構610的側壁上形成間隔元件，而從虛設閘極堆疊610的頂面移除間隔層820。在某些實施方式中，回蝕間隔層820可包含濕式蝕刻製程、乾式蝕刻製程、多重步驟蝕刻製程、或/及其組合。在N型場效電晶體區域212，當從曝露的磊晶堆疊310RS的頂面及水平面移除間隔層820，如第10A圖所示，間隔層820維持插入並配置於源極/汲極區域630中磊晶推疊310RS的第二磊晶層316的下方。間隔層配置於第二磊晶層316(例如奈米線)的下方。如第10B圖所示，在P型場效電晶體區域214中，從源極/汲極區域630中曝露的磊晶堆疊310移除間隔層820。
參照第1、11A及11B圖，方法100進行至步驟122，形成第一源極/汲極(S/D)區域特徵830於N型場效電晶體區域212中，同時使用第二圖案化硬遮罩840覆蓋P型場效電晶體區域214。第二圖案化硬遮罩840形成的方式在很多方面和上述第9B圖討論的第一圖案化硬遮罩730類似，包含前述討論的材料。
在N型場效電晶體區域212中，可執行磊晶生長製程形成第一源極/汲極(S/D)區域特徵830，磊晶生長製程提供磊晶材料包覆源極/汲極區域630中的磊晶堆疊310RS。在某些實施方式中，使用磊晶生長半導體材料835於第二磊晶層316上，形成第一源極/汲極(S/D)區域特徵830。換句話說，磊晶生長的半導體材料835形成於奈米線316周圍，這可被稱為形成「包覆物(cladding)」環繞奈米線316。
在各種實施方式中，磊晶生長半導體材料835可包含Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、SiP、或/及其他適當的材料。在某些實施方式中，磊晶生長半導體材料835可為在磊晶製程期間原處(in-situ)摻雜。在某些實施方式中，磊晶生長半導體材料835可不為原處(in-situ)摻雜，舉例來說，而是執行佈植製程摻雜磊晶生長半導體材料835。
因此，和虛設閘極堆疊610相關的第一源極/汲極特徵830包含第二磊晶層316及磊晶生長材料835。間隔層820的介電材料插入第二磊晶層316中。各磊晶層316(例如奈米線)延伸至通道區域620內，從而形成多重通道、多重源極/汲極區域的裝置。在一實施方式中，在N型場效電晶體區域212中，第一源極/汲極特徵830從上方包覆五個奈米線316並延伸至通道區域620內。在 形成第一源極/汲極特徵830於N型場效電晶體區域212中之後，使用蝕刻製程移除第二圖案化硬遮罩840。
參照第1、12A及12B圖，方法100進行至步驟124，在P型場效電晶體區域214的源極/汲極區域630中形成第二源極/汲極特徵850，同時使用第三圖案化硬遮罩860覆蓋N型場效電晶體區域212。形成第三圖案化硬遮罩860的方式在很多方面和上述第9B圖討論的第一圖案化硬遮罩730類似，包含前述討論的材料。
可執行磊晶生長製程形成第二源極/汲極特徵850，磊晶生長製程提供磊晶生長材料包覆磊晶堆疊310。在某些實施方式中，磊晶生長半導體材料855於磊晶堆疊310上方以形成第二源極/汲極特徵850，在磊晶堆疊310中，第一磊晶層314插入第二磊晶層316。因此，和第二源極/汲極特徵850相關的虛設閘極堆疊610，第二源極/汲極特徵850包含磊晶堆疊310及磊晶生長材料835並延伸至通道區域620中，進而形成單一磊晶堆疊源極/汲極區域的裝置。在某些實施方式中，形成第二源極/汲極特徵850的方式在很多方面和上述第11A圖討論的第一源極/汲極特徵830類似，包含前述討論的材料。在某些實施方式中，半導體材料855不同於半導體材料835。在P型場效電晶體區域214中形成第二源極/汲極特徵850，使用蝕刻製程移除第三圖案化硬遮罩860。
參照第1、13A及13B圖，方法100進行至步驟126，在N型場效電晶體區域212和P型場效電晶體區域214中形成層間介電層(inter-layer dielectric,ILD)910。在某些實施方式中，層間介電層910包含例如四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、未摻雜的矽玻璃、或摻雜氧化矽，摻雜氧化矽例 如為硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、熔融石英玻璃(fused silica glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼摻雜矽玻璃(boron doped silicon glass,BSG)、或/及其他適當的介電材料。可使用電漿增強化學氣相沉積(PECVD)製程或其他適當的沉積技術沉積層間介電層910。
在某些實施例中，在沉積層間介電層910後，可執行平坦化製程以曝露出虛設閘極堆疊610的頂面。例如，平坦化製程包含化學機械研磨製程(CMP)，化學機械研磨製程移除虛設閘極堆疊610上方的部分層間介電層910並平坦化半導體裝置200的頂面。此外，化學機械研磨製程可移除虛設閘極堆疊610上方的閘極硬遮罩616以曝露出電極層614，電極層614可例如為多晶矽電極層。之後，在某些實施方式中，從基板210移除剩餘的先前形成的虛設閘極堆疊610。在某些實施方式中，可移除電極層614而虛設介電層520未被移除。
參照第1、14A及14B圖，方法100進行至步驟128，移除虛設電極層614、虛設介電層520及第一磊晶層314以在N型場效電晶體區域212的通道區域620中形成第一閘極溝槽920，同時使用第四圖案化硬遮罩930覆蓋P型場效電晶體區域214。形成第四圖案化硬遮罩930的方式在很多方面和上述第9B圖討論的第一圖案化硬遮罩730類似，包含前述討論的材料。
可使用選擇性蝕刻製程，例如選擇性濕式蝕刻、選擇性乾式蝕刻、或其組合，移除虛設電極層614。移除虛設介電層520的方式在很多方面和上述第8圖討論的蝕刻製程類似。移除第一磊晶層314的方式在很多方面和上述第9A圖討論的蝕刻製程類 似。第14A圖繪示間隙940取代通道區域620中的第一磊晶層314。可使用周圍環境(例如空氣、氮氣)填充間隙940。藉由移除第一磊晶層314，通道區域620中的磊晶堆疊310轉變成到磊晶堆疊310R且曝露於第一閘極溝槽910內。然後使用蝕刻製程移除第四圖案化硬遮罩930。在一實施例中，第四圖案化硬遮罩930是光阻圖案，使用濕式去除光阻(wet stripping)或/及電漿灰化(plasma ashing)移除第四圖案化硬遮罩930。
參照第1、15A及15B圖，方法100進行至步驟130，形成第一最終閘極堆疊1010於第一閘極溝槽920內。第一最終閘極堆疊1010可為高介電常數介電質(high-K)/金屬(metal)閘極堆疊，然而其他組成都有可能。在目前的實施方式中，第一最終閘極堆疊1010形成閘極，和閘極相關的通道區域620中的第二磊晶層316(奈米線)提供的多重通道，通道區域620被稱為環繞式閘極(gate-all-around,GAA)裝置。在目前的實施方式中，第一高介電常數介電質/金屬閘極(HK/MG)結構1010形成於第一閘極溝槽920內。在各種實施方式中，第一高介電常數介電質/金屬閘極結構1010包含介面層(interfacial layer)、形成於介面層上方的高介電常數閘極介電層1014、或/及形成於高介電常數閘極介電層1014上方的第一閘極金屬層1016。此處使用和所述之高介電常數閘極介電質，包含具有高介電常數的介電材料，例如，大於熱氧化矽的介電常數(約3.9)。
在某些實施方式中，高介電常數介電質/金屬閘極堆疊1010的介面層可包含介電材料，例如氧化矽、矽氧化鉿(HfSiO)或氮氧化矽(SiON)。可使用化學氧化、熱氧化、原子層沉積、化 學氣相沉積、或/及其他適當的方法形成介面層。高介電常數介電質/金屬閘極堆疊1010的閘極介電層1014可包含高介電常數介電層，例如氧化鉿。可替代地，高介電常數介電質/金屬閘極堆疊1010的閘極介電層1014可包含其他高介電常數介電質，例如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、SiON、氮氧化物、或其組合、或其他適當的材料。可使用原子層沉積、物理氣相沉積、化學氣相沉積、氧化、或/及其他適當的方法形成高介電常數閘極介電層1014。高介電常數閘極介電層1014也形成於P型場效電晶體區域214上方，之後高介電常數閘極介電層1014會被移除。
第一閘極金屬層1016可包含單一層或替代性的多層結構、襯裡層、浸潤層(wetting layer)、黏著層(adhesion layer)、金屬合金或金屬矽化物；多層結構例如金屬層的各種組合，金屬層具有挑選過的功函數以增強裝置的效能(功函數金屬層)。舉例來說，第一閘極金屬層1016可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他適當的金屬材料或其組合。在各種實施方式中，可使用原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍、或其他適當的製程形成第一閘極金屬層1016。在某些實施方式中，閘極介電層1014及第一閘極金屬層1016也形成於P型場效電晶體區域214上方，之後會被移除。
在各種實施方式中，可執行化學機械研磨製程移除在P型場效電晶體區域214的高介電常數閘極介電層1014及第一閘極金屬層1016，並移除N型場效電晶體區域212中過多的高介電常數閘極介電層1014及第一閘極金屬層1016，進而提供基本上平坦的裝置200的頂面。
參照第1、16A及16B圖，方法100進行至步驟132，移除虛設電極層614及虛設介電層520以形成P型場效電晶體區域214中的通道區域620中的第二閘極溝槽1020。因此，磊晶堆疊310曝露於第二閘極溝槽1020內。蝕刻製程可包含濕式蝕刻、乾式蝕刻、或/及其組合。在某些實施方式中，蝕刻製程用以選擇性蝕刻虛設電極層614及虛設介電層520而基本上不蝕刻間隔層820、層間介電層910及第一最終閘極堆疊。因此，利用自我對準(self-alignment)的本質形成第二閘極溝槽1020，放寬製程上的限制。
參照第1、17A和17B圖，方法100進行至步驟134，在第二閘極溝槽1020內及磊晶堆疊310上方形成第二最終閘極堆疊1030以形成單一磊晶堆疊閘極。第二最終閘極堆疊1030可為高介電常數介電質/金屬閘極的閘極堆疊，然而，其他組合也有可能。在某些實施方式中，第二最終閘極堆疊1030形成閘極associated with磊晶堆疊310，磊晶堆疊310具有多個第一磊晶層314作為多重閘極通道，多重閘極通道藉由多個第二磊晶層316分隔以引入高效率的應變至閘極通道中，提升裝置效能。
在各種實施方式中，第二高介電常數介電質/金屬閘極堆疊1030包含介面層、形成於介面層上方的高介電常數閘極介 電層1014、或/及形成於高介電常數閘極介電層1014上方的第二閘極金屬層1036。形成第二高介電常數介電質/金屬閘極堆疊1030的方式可在很多方面和上述第15A圖討論的第一高介電常數介電質/金屬閘極堆疊1010類似，包含前文討論的材料。第二閘極金屬層1036可包含單一層或替代性的多層結構、襯裡層、浸潤層(wetting layer)、黏著層(adhesion layer)、金屬合金或金屬矽化物；多層結構例如金屬層的各種組合，金屬層具有挑選過的功函數以增強裝置的效能(功函數金屬層)。舉例來說，第二閘極金屬層1036可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他適當的金屬材料或其組合。在各種實施方式中，可使用原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍、或其他適當的製程形成第二閘極金屬層1036。
在各種實施方式中，可執行化學機械研磨製程移除在N型場效電晶體區域212的高介電常數閘極介電層1014及第二閘極金屬層1036，並移除P型場效電晶體區域214中過多的高介電常數閘極介電層1014及第二閘極金屬層1036，提供基本上平坦的裝置200的頂面。
如方法100所示，N型場效電晶體區域的裝置200N使用環繞式閘極結構且P型場效電晶體區域的裝置200P是單一磊晶堆疊閘極。裝置200N繪示於第17A圖中的等角視圖且對應第18A圖(沿線段A-A穿過第一最終閘極堆疊1010的剖面)的剖面示意圖、第18B圖(沿線段B-B穿過第一源極/汲極特徵830的剖面)的剖面示意圖、第18C圖(沿線段C-C穿過通道區域620及源極/汲極 區域630的剖面)的剖面示意圖。多重閘極裝置200P繪示於第17B圖中的等角視圖且對應第19A圖(沿線段A-A穿過第二最終閘極堆疊1030的剖面)的剖面示意圖、第19B圖(沿線段B-B穿過第二源極/汲極特徵850的剖面)的剖面示意圖、第19C圖(沿線段C-C穿過通道區域620及源極/汲極區域630的剖面)的剖面示意圖。
在N型場效電晶體區域212中，如第18A及18C圖所示，閘極介電層1014配置於第二磊晶層316(例如奈米線)的下方。然而，在其他的實施方式中，第一高介電常數介電層/金屬閘極堆疊1010的其他部分(例如第一閘極金屬層1016)也可配置於第二磊晶層316下。在某些實施方式中，裝置200可為鰭式場效電晶體裝置，鰭式場效電晶體裝置的閘極形成於通道區域620的至少兩面上(例如頂面和兩側壁)。在目前的實施方式中，裝置200在N型場效電晶體區域212中具有環繞式閘極。如前文所述，在目前的實施方式中，第二磊晶層316的厚度(奈米線的直徑)被選為大於第一磊晶層314以增強N型場效電晶體的閘極電流。第18B及18C圖的裝置200繪示第一源極/汲極特徵830，第一源極/汲極特徵830具有磊晶生長包覆層835配置於第二磊晶層316(例如奈米線)的多個面上，而間隔層820配置於第二磊晶層316之間。間隔層820接觸通道區域620中的閘極介電層1014。第一極/汲極特徵830形成於磊晶堆疊310RS的上方，磊晶堆疊310RS具有多重奈米線且各奈米線(第二磊晶材料316)延伸至通道區域620中，進而形成環繞式閘極、多重源極/汲極的結構。在某些實施方式中，源極/汲極區域630的奈米線總數和通道區域中奈米線的總數相同。
在P型場效電晶體區域214中，如第19A及19C圖繪示，閘極介電層1014包覆磊晶堆疊310周圍，磊晶堆疊310具有被第二磊晶層316插入的第一磊晶層314。在某些實施方式中，裝置200可為鰭式場效電晶體裝置，鰭式場效電晶體裝置的閘極形成於通道區域620的至少兩面上(例如頂面和兩側壁)或/及具有其他的構造。在目前的實施方式中，裝置200P在P型場效電晶體區域214中具有單一磊晶堆疊閘極。需要注意的是P型場效電晶體區域214的通道區域620中，第一磊晶層314的總數比N型場效電晶體區域212的通道區域620中的奈米線(第二磊晶層316)的總數多1，這是基於P型場效電晶體的效能考量，例如增強P型場效電晶體的閘極電流。
第19B及19C圖中的裝置200N繪示的第二源極/汲極特徵850具有磊晶生長包覆層855配置於磊晶堆疊310上方。第二源極/汲極特徵850延伸至通道區域620中，進而形成單一磊晶堆疊閘極、單一源極/汲極區域的結構。
額外的製程步驟可在方法100之前、期間及之後補充，而且根據方法100的各種實施方式，上述某些製程步驟可被取代或刪除。
作為一實施例，形成裝置200，使P型場效電晶體區域214的通道區域620中的第一磊晶層314總數相同於N型場效電晶體區域214的通道區域620中的奈米線(第二磊晶層316)總數。因為此緣故，在步驟104中，磊晶堆疊310的最上方的磊晶層式第二磊晶層316，而非第一磊晶層314。而且，在步驟124中，在形成在P型場效電晶體區域214的源極/汲極區域630中的第二源極/汲 極特徵850之前，使用選擇性蝕刻製程移除最上方的第二磊晶層316。類似地，在步驟132中，在移除虛設電極層614及虛設介電層520以形成P型場效電晶體區域214中的通道區域620中的第二閘極溝槽1020之後，使用另一選擇性蝕刻製程移除磊晶堆疊310最上方的第二磊晶層316。
基於前文所述，可以知道本揭露內容提供裝置和形成裝置的方法，此裝置中N型場效電晶體中包含環繞式閘極、多重源極/汲極區域結構而且P型場效電晶體中包含單一磊晶堆疊閘極、單一磊晶堆疊源極/汲極結構。藉由如此簡單而且可實行的製程整合，此裝置的P型場效電晶體區域中配備更多的通道層以增強P型場效電晶體的通道電流而且N型場效電晶體區域中具有更大的奈米線直徑以增強N型場效電晶體的通道電流。
本揭露內容提供一種半導體裝置的許多不同實施方式，半導體裝置包含第一電晶體配置於半導體基板的上方，第一電晶體具有第一導電類型。第一電晶體包含第一磊晶層和第二磊晶層，第一磊晶層由第一半導體材料組成，第二磊晶層由第一半導體材料組成且配置於第一磊晶層上方。第一電晶體也包含第一閘極介電層，第一閘極介電層環繞第一和第二磊晶層且從第一磊晶層的頂面延伸至第二磊晶層的底面。第一磊晶層的頂面背對半導體基板而且第二磊晶層的底面面向半導體基板。第一電晶體也包含第一金屬閘極層，第一金屬閘極層環繞第一閘極介電層，第一閘極介電層包含第一和第二磊晶層。此裝置也包含第二電晶體，第二電晶體具有第二導電類型且配置於半導體基板上方，第二導電類型和第一導電類型相反。第二電晶體包含第三磊晶層和 第四磊晶層，第三磊晶層由第一半導體材料組成，第四磊晶層直接配置於第三磊晶層上且由第二半導體材料組成，第二半導體材料不同於第一半導體材料。第二電晶體也包含第二閘極介電層，第二閘極介電層配置於第三和第四磊晶層上方而且第二金屬閘極層配置於第二閘極介電層上方。
在另一實施方式中，一種裝置包含N型場效電晶體(NFET)，N型場效電晶體配置於半導體基板上方。N型場效電晶體包含多個第一磊晶層，第一磊晶層由第一半導體材料組成。N型場效電晶體也包含第一閘極介電層，第一閘極介電層環繞各第一磊晶層且從一第一磊晶層的頂面延伸至下一第一磊晶層的底面。第一磊晶層的頂面背向半導體基板且第二磊晶層的底面面向半導體基板。N型場效電晶體也包含第一金屬閘極層，第一金屬閘極層環繞第一閘極介電層，第一閘極介電層包含磊晶層及第一側壁間隔件，第一側壁間隔件沿第一金屬閘極層的側壁配置。此裝置也包含P型場效電晶體，P型場效電晶體配置於半導體基板上方。P型場效電晶體包含磊晶層的堆疊，磊晶層的堆疊具有第二磊晶層和第一磊晶層，第二磊晶層由第二半導體材料組成，第二半導體材料不同於第一半導體材料。一第一磊晶層插入各兩相鄰的第二磊晶層之間。第一磊晶層直接配置於第二磊晶層上。P型場效電晶體也包含第二閘極介電層，第二閘極介電層直接配置於磊晶層的堆疊的側壁上，而且第二金屬閘極層配置於第二閘極介電層上方。
在又一實施方式中，一種方法包含在第一區域和第二區域中分別形成第一鰭板及第二鰭板於基板上方。第一鰭板具 有第一源極/汲極區域及第一通道區域而且第二鰭板具有第二源極/汲極區域及第二通道區域。第一鰭板和第二鰭板都由磊晶層的堆疊組成，磊晶層的堆疊包含第一磊晶層和第二磊晶層，具有第一組成的第一磊晶層被具有第二組成的第二磊晶層插入。此方法也包含從部分的第一鰭板移除第二磊晶層以在第一源極/汲極區域中形成第一間距；使用介電材料填充第一間距；生長第三磊晶材料於第一源極/汲極區域中的各第一磊晶層的至少兩表面上以形成第一源極/汲極特徵，同時介電材料填充第一間距。此方法也包含生長第四磊晶材料於第二源極/汲極區域中的第二鰭板以形成第二源極/汲極特徵；形成介電層於第一源極/汲極特徵和第二源極/汲極特徵上方；以及從第一通道區域中的部分第一鰭板移除第二磊晶層。方法也包含，在移除第二磊晶層之後，形成第一閘極堆疊於第一通道區域的第一鰭板上方。第一閘極堆疊配置於第一通道區域的各第一磊晶層的下方。此方法也包含形成第二閘極堆疊於第二通道區域的第二鰭板的上方。第二閘極堆疊包覆環繞第二通道區域的第二鰭板。
前文概括數個實施例之特徵，以便彼等熟習此項技術者可更佳地理解本揭示內容之態樣。彼等熟習此項技術者應瞭解，本揭示內容可易於作為設計或修正其他製程及結構之基礎，而實現與本案介紹之實施例相同的目的及/或達到與其相同的優勢。彼等熟習此項技術者亦應瞭解，此種同等構造不脫離本揭示內容之精神及範疇，而且可在不脫離本揭示內容精神及範疇之情況下進行多種變更、取代及更動。
200N‧‧‧裝置
210‧‧‧基板
212‧‧‧N型場效電晶體區域、第一區域
310RS‧‧‧磊晶堆疊
316‧‧‧第二磊晶層
610’‧‧‧淺溝槽隔離特徵
620‧‧‧通道區域
630‧‧‧源極/汲極區域
820‧‧‧間隔層
830‧‧‧第一源極/汲極特徵
835‧‧‧半導體材料
910‧‧‧層間介電層
1010‧‧‧第一最終閘極堆疊
1016‧‧‧第一閘極金屬層

Claims (1)

  1. 一種多重閘極裝置，包含：一第一電晶體，該第一電晶體具有一第一導電類型，配置於一半導體基板上，該第一電晶體包含：一第一磊晶層，該第一磊晶層由一第一半導體材料組成；一第二磊晶層，該第二磊晶層由一第一半導體材料組成且配置於該第一磊晶層上方；一第一閘極介電層環繞該第一磊晶層和該第二磊晶層且從該第一磊晶層的一頂面延伸至該第二磊晶層的一底面，該第一磊晶層的該頂面背對該半導體基板且該第二磊晶層的該底面面對該半導體基板；以及一第一金屬閘極層環繞該第一閘極介電層，該第一閘極介電層包含該第一磊晶層和該第二磊晶層；以及一第二電晶體，該第二電晶體具有一第二導電類型，配置於一半導體基板上，該第二導電類型和該第一導電類型相反，該第二電晶體包含：一第三磊晶層，該第三磊晶層由該第一半導體材料組成；一第四磊晶層，該第四磊晶層直接配置於該第三磊晶層上方且由一第二半導體材料組成，該第二半導體材料不同於該第一半導體材料；一第二閘極介電層，配置於該第三磊晶層和該第四磊晶層上方；以及 一第二金屬閘極層，配置於該第二閘極介電層上方。
TW105135763A 2015-11-16 2016-11-03 多重閘極裝置 TW201729340A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/941,745 US9899387B2 (en) 2015-11-16 2015-11-16 Multi-gate device and method of fabrication thereof

Publications (1)

Publication Number Publication Date
TW201729340A true TW201729340A (zh) 2017-08-16

Family

ID=58692146

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105135763A TW201729340A (zh) 2015-11-16 2016-11-03 多重閘極裝置

Country Status (3)

Country Link
US (2) US9899387B2 (zh)
CN (1) CN106711221A (zh)
TW (1) TW201729340A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817618A (zh) * 2017-11-22 2019-05-28 格芯公司 互补场效应晶体管中的外延结构
TWI669269B (zh) * 2017-08-18 2019-08-21 美商格芯（美國）集成電路科技有限公司 在奈米片場效電晶體之內間隔件形成
TWI761980B (zh) * 2019-10-31 2022-04-21 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

Families Citing this family (108)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490459B2 (en) * 2017-08-25 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method for source/drain contact formation in semiconductor devices
WO2015047354A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
US9960273B2 (en) * 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10115807B2 (en) * 2015-11-18 2018-10-30 Globalfoundries Inc. Method, apparatus and system for improved performance using tall fins in finFET devices
US10749032B2 (en) * 2016-03-11 2020-08-18 Intel Corporation Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers
US9620590B1 (en) 2016-09-20 2017-04-11 International Business Machines Corporation Nanosheet channel-to-source and drain isolation
US10340340B2 (en) * 2016-10-20 2019-07-02 International Business Machines Corporation Multiple-threshold nanosheet transistors
JP6859088B2 (ja) * 2016-12-14 2021-04-14 エイブリック株式会社 半導体装置の製造方法
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US11121131B2 (en) 2017-06-23 2021-09-14 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US10211307B2 (en) * 2017-07-18 2019-02-19 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement
US10403550B2 (en) * 2017-08-30 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US10699956B2 (en) 2017-08-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US10236220B1 (en) * 2017-08-31 2019-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
US10714394B2 (en) * 2017-09-28 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Fin isolation structures of semiconductor devices
US10269965B1 (en) 2017-10-25 2019-04-23 Taiwan Semiconductor Manufacturing Company Ltd. Multi-gate semiconductor device and method for forming the same
US10243061B1 (en) 2017-11-15 2019-03-26 International Business Machines Corporation Nanosheet transistor
US10714475B2 (en) 2017-11-27 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10727320B2 (en) * 2017-12-29 2020-07-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of manufacturing at least one field effect transistor having epitaxially grown electrodes
US10516064B1 (en) 2018-08-14 2019-12-24 International Business Machines Corporation Multiple width nanosheet devices
US11069793B2 (en) 2018-09-28 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
CN110970369B (zh) * 2018-09-30 2022-08-02 中芯国际集成电路制造(上海)有限公司 Cmos反相器结构及其形成方法
KR102524803B1 (ko) 2018-11-14 2023-04-24 삼성전자주식회사 소스/드레인 영역을 갖는 반도체 소자
US11101360B2 (en) * 2018-11-29 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11031298B2 (en) * 2018-11-30 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11742410B2 (en) * 2019-01-03 2023-08-29 Intel Corporation Gate-all-around integrated circuit structures having oxide sub-fins
US11830933B2 (en) 2019-01-04 2023-11-28 Intel Corporation Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
US11164866B2 (en) * 2019-02-20 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for manufacturing the same
CN112018113A (zh) 2019-05-29 2020-12-01 台湾积体电路制造股份有限公司 半导体装置及其形成方法
US11430892B2 (en) 2019-05-29 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Inner spacers for gate-all-around transistors
US10879379B2 (en) * 2019-05-30 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11456368B2 (en) 2019-08-22 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with hard mask layer over fin structure and method for forming the same
US11355363B2 (en) * 2019-08-30 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing
US11201243B2 (en) * 2019-09-03 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Nanowire stack GAA device and methods for producing the same
US10978567B2 (en) * 2019-09-17 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Gate stack treatment for ferroelectric transistors
US11205650B2 (en) 2019-09-26 2021-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Input/output semiconductor devices
US11205711B2 (en) 2019-09-26 2021-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Selective inner spacer implementations
CN111312819B (zh) * 2019-11-14 2024-04-09 中国科学院微电子研究所 一种堆叠纳米线或片环栅器件及其制备方法
US11362096B2 (en) 2019-12-27 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
DE102020110792B4 (de) * 2019-12-27 2022-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtungsstruktur mit Finnenstruktur und mehreren Nanostrukturen und Verfahren zum Bilden derselben
US11430867B2 (en) 2020-01-24 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Channel mobility improvement
US11264508B2 (en) 2020-01-24 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage prevention structure and method
US11862712B2 (en) * 2020-02-19 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases
US11404417B2 (en) 2020-02-26 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Low leakage device
US11152477B2 (en) 2020-02-26 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Transistors with different threshold voltages
US11855225B2 (en) 2020-02-27 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with epitaxial bridge feature and methods of forming the same
US11424338B2 (en) 2020-03-31 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Metal source/drain features
DE102020119940A1 (de) 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Mehrfachgatetransistorstruktur
US11195937B2 (en) 2020-03-31 2021-12-07 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate transistor structure
US11532711B2 (en) 2020-04-16 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. PMOSFET source drain
US11417766B2 (en) 2020-04-21 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Transistors having nanostructures
US11289584B2 (en) 2020-04-24 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Inner spacer features for multi-gate transistors
US11342413B2 (en) 2020-04-24 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Selective liner on backside via and method thereof
US11670723B2 (en) 2020-05-12 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon channel tempering
US11670692B2 (en) 2020-05-13 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around devices having self-aligned capping between channel and backside power rail
US11532627B2 (en) 2020-05-22 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain contact structure
US11948987B2 (en) 2020-05-28 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned backside source contact structure
US11532626B2 (en) 2020-05-29 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Reduction of gate-drain capacitance
US11232988B2 (en) 2020-05-29 2022-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Wavy profile mitigation
US11508736B2 (en) 2020-06-08 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming different types of devices
US11158634B1 (en) 2020-06-15 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Backside PN junction diode
US11222892B2 (en) 2020-06-15 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Backside power rail and methods of forming the same
DE102021112556A1 (de) * 2020-06-17 2021-12-23 Taiwan Semiconductor Manufacturing Co., Ltd. Dreischichtiger high-k gate-dielektrikumstapell für austrittsarbeitskontrolle
US11348919B2 (en) * 2020-06-25 2022-05-31 Intel Corporation Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
US11264513B2 (en) * 2020-06-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures for transistors
US11233005B1 (en) 2020-07-10 2022-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing an anchor-shaped backside via
US11245036B1 (en) 2020-07-21 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Latch-up prevention
US11735669B2 (en) 2020-07-30 2023-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertically-oriented complementary transistor
US11450673B2 (en) 2020-07-31 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Connection between source/drain and gate
US11329168B2 (en) 2020-07-31 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with fish bone structure and methods of forming the same
US11984488B2 (en) 2020-07-31 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Multigate device with air gap spacer and backside rail contact and method of fabricating thereof
DE102020131140A1 (de) 2020-08-10 2022-02-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gateisolierungsstruktur
US11450662B2 (en) 2020-08-10 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation structure
US11437373B2 (en) 2020-08-13 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device structure
US11482594B2 (en) 2020-08-27 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside power rail and method thereof
US11355502B2 (en) 2020-09-21 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with gate recess and methods of forming the same
US11990472B2 (en) * 2020-09-23 2024-05-21 Intel Corporation Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates
US11437245B2 (en) 2020-09-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium hump reduction
US11404576B2 (en) 2020-10-13 2022-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric fin structure
US11600625B2 (en) 2020-10-14 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having an offset source/drain feature and method of fabricating thereof
US11532744B2 (en) 2020-10-26 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Gate cut structure and method of forming the same
US11489078B2 (en) 2020-10-27 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Lightly-doped channel extensions
US11658119B2 (en) 2020-10-27 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Backside signal interconnection
US11462612B2 (en) 2020-10-28 2022-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure
US11444178B2 (en) 2020-11-13 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Inner spacer liner
US11362217B1 (en) 2020-11-23 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming transistors of different configurations
CN112599588B (zh) * 2020-12-15 2023-08-25 陈小建 SiC半导体器件及其制备方法
US11699760B2 (en) 2021-01-04 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure for stacked multi-gate device
US11527534B2 (en) 2021-01-06 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Gap-insulated semiconductor device
US11749566B2 (en) 2021-01-15 2023-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Inner filler layer for multi-patterned metal gate for nanostructure transistor
US11735647B2 (en) 2021-01-26 2023-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming semiconductor device
US11728394B2 (en) 2021-01-27 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming backside power rails
US11710737B2 (en) 2021-02-05 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid semiconductor device
US11605720B2 (en) 2021-02-26 2023-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate cap
US11444170B1 (en) 2021-03-12 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with backside self-aligned power rail and methods of forming the same
US11615987B2 (en) 2021-03-26 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Backside via with a low-k spacer
US11916105B2 (en) 2021-03-26 2024-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with corner isolation protection and methods of forming the same
US11854896B2 (en) 2021-03-26 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with S/D bottom isolation and methods of forming the same
US11784228B2 (en) 2021-04-09 2023-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process and structure for source/drain contacts
US11848372B2 (en) 2021-04-21 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for reducing source/drain contact resistance at wafer backside
US11605638B2 (en) 2021-04-21 2023-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with multiple threshold voltages
US11791402B2 (en) 2021-05-14 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having strained channels
US11973128B2 (en) 2021-05-27 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming multi-gate transistors
CN113611743B (zh) 2021-06-11 2022-06-07 联芯集成电路制造(厦门)有限公司 半导体晶体管结构及其制作方法
US11532733B1 (en) 2021-06-25 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric isolation structure for multi-gate transistors
US11855081B2 (en) 2021-07-16 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epitaxial features
US20240170563A1 (en) 2022-11-22 2024-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric Layer for Nanosheet Protection and Method of Forming the Same

Family Cites Families (167)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002088683A1 (en) * 2001-04-30 2002-11-07 The Board Of Trustees Of The University Of Illinois Method and apparatus for characterization of ultrathin silicon oxide films using mirror-enhanced polarized reflectance fourier transform infrared spectroscopy
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
US7074657B2 (en) * 2003-11-14 2006-07-11 Advanced Micro Devices, Inc. Low-power multiple-channel fully depleted quantum well CMOSFETs
FR2864457B1 (fr) * 2003-12-31 2006-12-08 Commissariat Energie Atomique Procede de nettoyage par voie humide d'une surface notamment en un materiau de type silicium germanium.
KR100555567B1 (ko) * 2004-07-30 2006-03-03 삼성전자주식회사 다중가교채널 트랜지스터 제조 방법
KR100594327B1 (ko) * 2005-03-24 2006-06-30 삼성전자주식회사 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
JP4310399B2 (ja) * 2006-12-08 2009-08-05 株式会社東芝 半導体装置及びその製造方法
US7821061B2 (en) * 2007-03-29 2010-10-26 Intel Corporation Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
CN101657889B (zh) * 2007-05-03 2011-11-02 硅绝缘体技术有限公司 制备应变硅的清洁表面的改善的方法
FR2921757B1 (fr) * 2007-09-28 2009-12-18 Commissariat Energie Atomique Structure de transistor double-grille dotee d'un canal a plusieurs branches.
US7863176B2 (en) * 2008-05-13 2011-01-04 Micron Technology, Inc. Low-resistance interconnects and methods of making same
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
CN102473642B (zh) * 2009-07-08 2014-11-12 株式会社东芝 半导体装置及其制造方法
US8216902B2 (en) * 2009-08-06 2012-07-10 International Business Machines Corporation Nanomesh SRAM cell
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8890233B2 (en) * 2010-07-06 2014-11-18 Macronix International Co., Ltd. 3D memory array with improved SSL and BL contact layout
US8183104B2 (en) * 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US8901537B2 (en) * 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US9099388B2 (en) * 2011-10-21 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. III-V multi-channel FinFETs
US8580624B2 (en) * 2011-11-01 2013-11-12 International Business Machines Corporation Nanowire FET and finFET hybrid technology
US8709888B2 (en) * 2011-12-16 2014-04-29 International Business Machines Corporation Hybrid CMOS nanowire mesh device and PDSOI device
US8722472B2 (en) * 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8563376B2 (en) * 2011-12-16 2013-10-22 International Business Machines Corporation Hybrid CMOS nanowire mesh device and bulk CMOS device
CN106887453B (zh) * 2011-12-19 2020-08-21 英特尔公司 Ⅲ族-n纳米线晶体管
CN106847814B (zh) * 2011-12-19 2020-12-08 英特尔公司 在栅绕式架构中的锗和iii-v纳米线及纳米带的cmos实现
US9059024B2 (en) * 2011-12-20 2015-06-16 Intel Corporation Self-aligned contact metallization for reduced contact resistance
CN107195671B (zh) * 2011-12-23 2021-03-16 索尼公司 单轴应变纳米线结构
US9087863B2 (en) * 2011-12-23 2015-07-21 Intel Corporation Nanowire structures having non-discrete source and drain regions
DE112011106004B4 (de) * 2011-12-23 2017-07-13 Intel Corporation Halbleiterstruktur und Verfahren zum Herstellen einer CMOS-Nanodraht-Halbleiterstruktur
KR101767352B1 (ko) * 2011-12-23 2017-08-10 인텔 코포레이션 변조된 나노와이어 카운트를 갖는 반도체 구조물 및 그 제조 방법
WO2013095656A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition
US9012284B2 (en) * 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
CN104137228A (zh) * 2011-12-23 2014-11-05 英特尔公司 具有环绕式接触部的纳米线结构
CN104054181B (zh) * 2011-12-30 2017-10-20 英特尔公司 全包围栅晶体管的可变栅极宽度
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9105654B2 (en) * 2012-03-21 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain profile for FinFET
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
KR101352433B1 (ko) * 2012-04-04 2014-01-24 주식회사 동부하이텍 이미지 센서 및 그 제조 방법
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8536029B1 (en) * 2012-06-21 2013-09-17 International Business Machines Corporation Nanowire FET and finFET
US10535735B2 (en) * 2012-06-29 2020-01-14 Intel Corporation Contact resistance reduced P-MOS transistors employing Ge-rich contact layer
US9484447B2 (en) * 2012-06-29 2016-11-01 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
US8809131B2 (en) * 2012-07-17 2014-08-19 International Business Machines Corporation Replacement gate fin first wire last gate all around devices
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US9006829B2 (en) * 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
US8785909B2 (en) * 2012-09-27 2014-07-22 Intel Corporation Non-planar semiconductor device having channel region with low band-gap cladding layer
US8679902B1 (en) * 2012-09-27 2014-03-25 International Business Machines Corporation Stacked nanowire field effect transistor
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8765563B2 (en) * 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
US8716751B2 (en) * 2012-09-28 2014-05-06 Intel Corporation Methods of containing defects for non-silicon device engineering
CN103730366B (zh) * 2012-10-16 2018-07-31 中国科学院微电子研究所 堆叠纳米线mos晶体管制作方法
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US8748940B1 (en) * 2012-12-17 2014-06-10 Intel Corporation Semiconductor devices with germanium-rich active layers and doped transition layers
US8896101B2 (en) * 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US9859429B2 (en) * 2013-01-14 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of fabricating same
KR102033579B1 (ko) * 2013-01-25 2019-10-17 삼성전자주식회사 나노 와이어 채널 구조의 반도체 소자 및 그 제조 방법
KR20140106270A (ko) * 2013-02-26 2014-09-03 삼성전자주식회사 집적 회로 장치 및 그 제조 방법
US9209302B2 (en) * 2013-03-13 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching
US9048087B2 (en) * 2013-03-14 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for wet clean of oxide layers over epitaxial layers
KR102037304B1 (ko) * 2013-03-15 2019-10-29 인텔 코포레이션 하층 에칭 정지를 갖는 나노와이어 트랜지스터
US8969149B2 (en) * 2013-05-14 2015-03-03 International Business Machines Corporation Stacked semiconductor nanowires with tunnel spacers
JP6106024B2 (ja) * 2013-05-21 2017-03-29 株式会社ジャパンディスプレイ 薄膜トランジスタの製造方法及び薄膜トランジスタ
KR102021765B1 (ko) * 2013-06-17 2019-09-17 삼성전자 주식회사 반도체 장치
KR102077447B1 (ko) * 2013-06-24 2020-02-14 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
CN104282560B (zh) * 2013-07-02 2018-07-27 中国科学院微电子研究所 级联堆叠纳米线mos晶体管制作方法
US9293333B2 (en) * 2013-07-17 2016-03-22 Globalfoundries Inc. FinFET work function metal formation
US9716174B2 (en) * 2013-07-18 2017-07-25 Globalfoundries Inc. Electrical isolation of FinFET active region by selective oxidation of sacrificial layer
US9209086B2 (en) * 2013-07-22 2015-12-08 Globalfoundries Inc. Low temperature salicide for replacement gate nanowires
US9171843B2 (en) * 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
KR102069609B1 (ko) * 2013-08-12 2020-01-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9184269B2 (en) * 2013-08-20 2015-11-10 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US8872161B1 (en) * 2013-08-26 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrate circuit with nanowires
US9257545B2 (en) * 2013-09-12 2016-02-09 Globalfoundries Inc. Stacked nanowire device with variable number of nanowire channels
WO2015047354A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
KR102083494B1 (ko) * 2013-10-02 2020-03-02 삼성전자 주식회사 나노와이어 트랜지스터를 포함하는 반도체 소자
US9263520B2 (en) * 2013-10-10 2016-02-16 Globalfoundries Inc. Facilitating fabricating gate-all-around nanowire field-effect transistors
US9263338B2 (en) * 2013-10-23 2016-02-16 Stmicroelectronics, Inc. Semiconductor device including vertically spaced semiconductor channel structures and related methods
US10586868B2 (en) * 2013-12-19 2020-03-10 Intel Corporation Non-planar semiconductor device having hybrid geometry-based active region
EP3087590A4 (en) * 2013-12-23 2017-11-22 Intel Corporation Pre-sculpting of si fin elements prior to cladding for transistor channel applications
US9508712B2 (en) * 2014-01-02 2016-11-29 Globalfoundries Inc. Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
FR3016237B1 (fr) * 2014-01-07 2017-06-09 Commissariat Energie Atomique Dispositif a nanofils de semi-conducteur partiellement entoures par une grille
US9111986B2 (en) * 2014-01-09 2015-08-18 International Business Machines Corporation Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base
US9391171B2 (en) * 2014-01-24 2016-07-12 International Business Machines Corporation Fin field effect transistor including a strained epitaxial semiconductor shell
US9257527B2 (en) * 2014-02-14 2016-02-09 International Business Machines Corporation Nanowire transistor structures with merged source/drain regions using auxiliary pillars
US9257450B2 (en) * 2014-02-18 2016-02-09 Stmicroelectronics, Inc. Semiconductor device including groups of stacked nanowires and related methods
CN104867873B (zh) * 2014-02-21 2018-03-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9893167B2 (en) * 2014-03-24 2018-02-13 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
US9318552B2 (en) * 2014-05-21 2016-04-19 Globalfoundries Inc. Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
KR102158963B1 (ko) * 2014-05-23 2020-09-24 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US20150357433A1 (en) * 2014-06-09 2015-12-10 GlobalFoundries, Inc. INTEGRATED CIRCUITS WITH VERTICAL JUNCTIONS BETWEEN nFETS AND pFETS, AND METHODS OF MANUFACTURING THE SAME
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
US9502518B2 (en) * 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
EP3161870B1 (en) * 2014-06-24 2022-05-25 Intel Corporation Techniques for forming ge/sige-channel and iii-v-channel transistors on the same die
US9966471B2 (en) * 2014-06-27 2018-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Gate-All-Around FinFET and method forming the same
US9608116B2 (en) * 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9881993B2 (en) * 2014-06-27 2018-01-30 Taiwan Semiconductor Manufacturing Company Limited Method of forming semiconductor structure with horizontal gate all around structure
US9443978B2 (en) * 2014-07-14 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor device having gate-all-around transistor and method of manufacturing the same
US10396152B2 (en) * 2014-07-25 2019-08-27 International Business Machines Corporation Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction
US9306019B2 (en) * 2014-08-12 2016-04-05 GlobalFoundries, Inc. Integrated circuits with nanowires and methods of manufacturing the same
US10199502B2 (en) * 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US9576856B2 (en) * 2014-10-27 2017-02-21 Globalfoundries Inc. Fabrication of nanowire field effect transistor structures
US9614056B2 (en) * 2014-10-28 2017-04-04 Globalfoundries Inc. Methods of forming a tri-gate FinFET device
US9276064B1 (en) * 2014-11-07 2016-03-01 Globalfoundries Inc. Fabricating stacked nanowire, field-effect transistors
US10170537B2 (en) * 2014-12-23 2019-01-01 International Business Machines Corporation Capacitor structure compatible with nanowire CMOS
US20160190239A1 (en) * 2014-12-26 2016-06-30 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9543323B2 (en) * 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions
KR20160112778A (ko) * 2015-03-20 2016-09-28 삼성전자주식회사 핀 액티브 영역들을 갖는 반도체
US9780166B2 (en) * 2015-03-30 2017-10-03 International Business Machines Corporation Forming multi-stack nanowires using a common release material
US9385218B1 (en) * 2015-04-23 2016-07-05 International Business Machines Corporation Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
US9437502B1 (en) * 2015-06-12 2016-09-06 International Business Machines Corporation Method to form stacked germanium nanowires and stacked III-V nanowires
KR102377909B1 (ko) * 2015-06-27 2022-03-23 인텔 코포레이션 희생층으로서 gaas를 가지는 ge 나노와이어 트랜지스터
US9818872B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10170608B2 (en) * 2015-06-30 2019-01-01 International Business Machines Corporation Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET
US9859430B2 (en) * 2015-06-30 2018-01-02 International Business Machines Corporation Local germanium condensation for suspended nanowire and finFET devices
EP3112316B1 (en) * 2015-07-02 2018-05-02 IMEC vzw Method for manufacturing transistor devices comprising multiple nanowire channels
US9613871B2 (en) * 2015-07-16 2017-04-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US9425259B1 (en) * 2015-07-17 2016-08-23 Samsung Electronics Co., Ltd. Semiconductor device having a fin
US9837416B2 (en) * 2015-07-31 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Multi-threshold voltage field effect transistor and manufacturing method thereof
US9607990B2 (en) * 2015-08-28 2017-03-28 International Business Machines Corporation Method to form strained nFET and strained pFET nanowires on a same substrate
US9647139B2 (en) * 2015-09-04 2017-05-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
DE112015006966T5 (de) * 2015-09-25 2018-07-12 Intel Corporation Herstellung von multikanal-nanodrahtvorrichtungen mit selbstausrichtenden internen abstandhaltern und soi finfets unter verwendung einer selektiven siliziumnitridkappe
US9853101B2 (en) * 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
US9716142B2 (en) * 2015-10-12 2017-07-25 International Business Machines Corporation Stacked nanowires
KR102379701B1 (ko) * 2015-10-19 2022-03-28 삼성전자주식회사 멀티-채널을 갖는 반도체 소자 및 그 형성 방법
US9590038B1 (en) * 2015-10-23 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor device having nanowire channel
US10276572B2 (en) * 2015-11-05 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9754840B2 (en) * 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
FR3043837B1 (fr) * 2015-11-17 2017-12-15 Commissariat Energie Atomique Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes
US9887269B2 (en) * 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9627540B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10164012B2 (en) * 2015-11-30 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9601569B1 (en) * 2015-12-07 2017-03-21 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure
US9899269B2 (en) * 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
KR102366953B1 (ko) * 2016-01-06 2022-02-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9929266B2 (en) * 2016-01-25 2018-03-27 International Business Machines Corporation Method and structure for incorporating strain in nanosheet devices
KR102343470B1 (ko) * 2016-01-28 2021-12-24 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9620590B1 (en) * 2016-09-20 2017-04-11 International Business Machines Corporation Nanosheet channel-to-source and drain isolation
US9728621B1 (en) * 2016-09-28 2017-08-08 International Business Machines Corporation iFinFET
KR102551589B1 (ko) * 2016-09-29 2023-07-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9842835B1 (en) * 2016-10-10 2017-12-12 International Business Machines Corporation High density nanosheet diodes
FR3057702B1 (fr) * 2016-10-13 2018-12-07 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un transistor a effet de champ a grille enrobante
US9660028B1 (en) * 2016-10-31 2017-05-23 International Business Machines Corporation Stacked transistors with different channel widths
US9923055B1 (en) * 2016-10-31 2018-03-20 International Business Machines Corporation Inner spacer for nanosheet transistors
CN108231590B (zh) * 2016-12-09 2023-03-14 Imec 非营利协会 水平纳米线半导体器件
US10002939B1 (en) * 2017-02-16 2018-06-19 International Business Machines Corporation Nanosheet transistors having thin and thick gate dielectric material
EP3369702A1 (en) * 2017-03-03 2018-09-05 IMEC vzw Internal spacers for nanowire semiconductor devices
US9991254B1 (en) * 2017-03-09 2018-06-05 International Business Machines Corporation Forming horizontal bipolar junction transistor compatible with nanosheets
KR102285641B1 (ko) * 2017-03-10 2021-08-03 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US10103065B1 (en) * 2017-04-25 2018-10-16 International Business Machines Corporation Gate metal patterning for tight pitch applications
KR102465537B1 (ko) * 2017-10-18 2022-11-11 삼성전자주식회사 반도체 장치
US10672742B2 (en) * 2017-10-26 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10141403B1 (en) * 2017-11-16 2018-11-27 International Business Machines Corporation Integrating thin and thick gate dielectric nanosheet transistors on same chip
US10833157B2 (en) * 2017-12-18 2020-11-10 International Business Machines Corporation iFinFET
US10600889B2 (en) * 2017-12-22 2020-03-24 International Business Machines Corporation Nanosheet transistors with thin inner spacers and tight pitch gate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI669269B (zh) * 2017-08-18 2019-08-21 美商格芯（美國）集成電路科技有限公司 在奈米片場效電晶體之內間隔件形成
US10651291B2 (en) 2017-08-18 2020-05-12 Globalfoundries Inc. Inner spacer formation in a nanosheet field-effect transistor
CN109817618A (zh) * 2017-11-22 2019-05-28 格芯公司 互补场效应晶体管中的外延结构
TWI685967B (zh) * 2017-11-22 2020-02-21 美商格芯（美國）集成電路科技有限公司 在互補場效電晶體中之磊晶結構
CN109817618B (zh) * 2017-11-22 2023-07-28 格芯(美国)集成电路科技有限公司 互补场效应晶体管中的外延结构
TWI761980B (zh) * 2019-10-31 2022-04-21 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

Also Published As

Publication number Publication date
US20180175036A1 (en) 2018-06-21
US10790280B2 (en) 2020-09-29
US9899387B2 (en) 2018-02-20
CN106711221A (zh) 2017-05-24
US20170141112A1 (en) 2017-05-18

Similar Documents

Publication Publication Date Title
US10790280B2 (en) Multi-gate device and method of fabrication thereof
US11942548B2 (en) Multi-gate device and method of fabrication thereof
US11355611B2 (en) Multi-gate device and method of fabrication thereof
US10157799B2 (en) Multi-gate device and method of fabrication thereof
US11955554B2 (en) Method of fabricating a multi-gate device
US10522424B2 (en) FinFET doping methods and structures thereof
US11276695B2 (en) Multi-gate device and related methods
TWI737296B (zh) 半導體裝置及其製造方法
TWI804735B (zh) 半導體裝置及其製造方法
US11121036B2 (en) Multi-gate device and related methods
US11532625B2 (en) Semiconductor device and method of fabrication thereof
US11328963B2 (en) Multi-gate device and related methods
TW202339013A (zh) 半導體裝置及其製造方法