JP4310399B2 - 半導体装置及びその製造方法 - Google Patents
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Description
図7(a)(b)は、本発明の第2の実施形態に係わるマルチゲートCMOS構造の半導体装置の素子構造を示す断面図である。なお、図7(a)は図3(a)と同様に、図1のB1−B1’断面に相当し、図7(b)は図3(b)と同様に、図1のB2−B2’断面に相当している。また、図3(a)(b)と同一部分には同一符号を付して、その詳しい説明は省略する。
図8(a)(b)は、本発明の第2の実施形態に係わるマルチゲートCMOS構造の半導体装置の素子構造を示す断面図である。なお、なお、図8(a)は図3(a)と同様に、図1のB1−B1’断面に相当し、図8(b)は図3(b)と同様に、図1のB2−B2’断面に相当している。図3と同一部分には同一符号を付して、その詳しい説明は省略する。
図9(a)(b)は、本発明の第4の実施形態に係わるマルチゲートCMOS構造の半導体装置の素子構造を示す断面図である。なお、図9(a)は図3(a)と同様に、図1のB1−B1’断面に相当し、図9(b)は図3(b)と同様に、図1のB2−B2’断面に相当している。図3と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。実施形態ではnMISFET及びpMISFET共に1本のFinで構成される例について説明したが、それぞれが複数本のFinで構成されるMISFETに対しても本発明は有効である。また、第2の半導体領域はSiGeに限るものではなくGeであっても良い。さらに、埋め込み絶縁膜の下地となる基板は必ずしも単結晶Si基板に限るものではなく、各種の半導体基板を用いることが可能である。
2…埋め込み絶縁膜
3…2軸引っ張り歪みSi層
4…選択成長用マスク材
5…SiGe層
6…Si層
7…酸化膜
8…2軸圧縮歪みSiGe層
10…1軸引っ張り歪みSi層(第1の半導体領域)
11…第1のゲート絶縁膜
12…第2のゲート絶縁膜
13,23…ゲート側壁絶縁膜
14…第1のソース/ドレイン領域
16,26…Fin形成用マスク材
18,28…素子分離用酸化膜
20…1軸圧縮歪みSiGe層(第2の半導体層)
21…第1のゲート絶縁膜
22…第2のゲート絶縁膜
24…第2のソース/ドレイン領域
Claims (12)
- 絶縁体上の半導体層にnチャネルMISトランジスタとpチャネルMISトランジスタを形成した半導体装置であって、
前記nチャネルMISトランジスタのチャネルがチャネル長方向に1軸引っ張り歪みを有するSi層で形成され、前記pチャネルMISトランジスタのチャネルがチャネル長方向に1軸圧縮歪みを有するSiGe又はGe層で形成され、前記各トランジスタの電流方向が共に<110>方向であることを特徴とする半導体装置。 - 絶縁体と、
前記絶縁体上に一方向に沿って形成され、長手方向が<110>方向であり、<110>方向に1軸引っ張り歪みを有するSiからなる第1の半導体領域と、この第1の半導体領域の少なくとも両側面に第1のゲート絶縁膜を介して形成され、且つ<110>方向をチャネル長方向とするように形成された第1のゲート電極と、前記第1の半導体領域に形成された第1のソース/ドレイン領域と、を含んで形成されたnチャネルMISトランジスタと、
前記絶縁体上に前記第1の半導体領域と平行に形成され、長手方向が<110>方向であり、<110>方向に1軸圧縮歪みを有するSiGe又はGeからなる第2の半導体領域と、この第2の半導体領域の少なくとも両側面に第2のゲート絶縁膜を介して形成され、且つ<110>方向をチャネル長方向とするように形成された第2のゲート電極と、前記第2の半導体領域に形成された第2のソース/ドレイン領域と、を含んで形成されたpチャネルMISトランジスタと、
を具備したことを特徴とする半導体装置。 - 前記第1及び第2の半導体領域の上面は、それぞれ(100)面であることを特徴とする請求項2記載の半導体装置。
- 前記第1及び第2の半導体領域の上面は、それぞれ(110)面であることを特徴とする請求項2記載の半導体装置。
- 前記第1及び第2の半導体領域の長手方向と直交する方向の幅は、それぞれ5〜500nmであることを特徴とする請求項2〜4の何れかに記載の半導体装置。
- 前記第1及び第2のゲート電極は、前記第1及び第2の半導体領域の両側面に加え上面にも形成されたトライゲート構造であることを特徴とする請求項2〜5の何れかに記載の半導体装置。
- 前記第1及び第2のゲート電極は、前記第1及び第2の半導体領域の両側面に加え上面及び下面にも形成されたゲートオールアラウンド構造であることを特徴とする請求項2〜5の何れかに記載の半導体装置。
- 絶縁体と、
前記絶縁体上に一方向に沿って形成され、長手方向が<110>方向であり、<110>方向に1軸引っ張り歪みを有するSiからなる第1の半導体領域と、この第1の半導体領域の両側面を埋め込むように形成された第1の素子分離絶縁膜と、前記第1の半導体領域の上面に第1のゲート絶縁膜を介して形成され、且つ<110>方向をチャネル長方向とするように形成された第1のゲート電極と、前記第1の半導体領域に形成された第1のソース/ドレイン領域と、を含んで形成されたnチャネルMISトランジスタと、
前記絶縁体上に前記第1の半導体領域と平行に形成され、長手方向が<110>方向であり、<110>方向に1軸圧縮歪みを有するSiGe又はGeからなる第2の半導体領域と、この第2の半導体領域の両側部を埋め込むように形成された第2の素子分離絶縁膜と、前記第2の半導体領域の上面に第2のゲート絶縁膜を介して形成され、且つ<110>方向をチャネル長方向とするように形成された第2のゲート電極と、前記第2の半導体領域に形成された第2のソース/ドレイン領域と、を含んで形成されたpチャネルMISトランジスタと、
を具備したことを特徴とする半導体装置。 - 絶縁体上に2軸引っ張り歪みを有するSi層を形成する工程と、
前記Si層上の一部にSiGe層をエピタキシャル成長する工程と、
前記SiGe層に酸化処理を施すことにより、前記絶縁体上に圧縮歪みを有するSiGe又はGe層を形成する工程と、
前記各層をエッチングにより<110>方向と平行なストライプ状に残すことにより、<110>方向に1軸引っ張り歪みを有するSi層からなる第1の半導体領域と、<110>方向に1軸圧縮歪みを有するSiGe又はGe層からなる第2の半導体領域を形成する工程と、
前記第1の半導体領域にチャネル長方向に1軸引っ張り歪みを有するnチャネルMISトランジスタを形成し、前記第2の半導体領域にチャネル長方向に1軸圧縮歪みを有するpチャネルMISトランジスタを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記絶縁体上に形成する前記Si層は、表面が(001)面を有することを特徴とする請求項9記載の半導体装置の製造方法。
- 前記Si層上の一部に前記SiGe層をエピタキシャル成長するに際し、前記Si層のnチャネルMISトランジスタ形成領域上にマスク材を形成したのち、該マスク材で覆われていないpチャネルMISトランジスタ形成領域に前記SiGe層をエピタキシャル成長することを特徴とする請求項9記載の半導体装置の製造方法。
- 前記nチャネルMISトランジスタを形成するに際し、前記第1の半導体領域を<110>方向と直交する方向に横断する第1のゲート電極を形成した後、前記第1のゲート電極をマスクに前記第1の半導体領域に第1のソース/ドレイン領域を形成し、
前記pチャネルMISトランジスタを形成するに際し、前記第2の半導体領域を<110>方向と直交する方向に横断する第2のゲート電極を形成した後、前記第2のゲート電極をマスクに前記第2の半導体領域に第2のソース/ドレイン領域を形成することを特徴とする請求項9記載の半導体装置の製造方法。
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