CN112018113A - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
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- CN112018113A CN112018113A CN202010241453.9A CN202010241453A CN112018113A CN 112018113 A CN112018113 A CN 112018113A CN 202010241453 A CN202010241453 A CN 202010241453A CN 112018113 A CN112018113 A CN 112018113A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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Abstract
提供半导体装置及其形成方法。依据本发明实施例的半导体装置包含第一源极/漏极部件、第二源极/漏极部件、位于第一源极/漏极部件与第二源极/漏极部件之间的第一半导体通道元件和第二半导体通道元件,以及第一介电部件和第二介电部件的每一者包含第一介电层和不同于第一介电层的第二介电层。第一介电部件和第二介电部件夹设于第一半导体通道元件与第二半导体通道元件之间。
Description
技术领域
本发明实施例涉及半导体技术,且特别涉及半导体装置及其形成方法。
背景技术
集成电路(integrated circuit,IC)产业已经历了快速成长。在集成电路材料和设计上的技术进步产生了数代集成电路,每一代都比前一代具有更小且更复杂的电路。在集成电路的发展史中,功能密度(即每一芯片区互连的装置数目)增加,同时几何尺寸(即制造过程中所产生的最小的组件(或线路))缩小。此元件尺寸微缩化的制程提供增加生产效率与降低相关费用的益处。元件尺寸微缩化也增加了加工及制造集成电路的复杂性。
举例来说,随着集成电路(IC)技术朝更小的技术节点发展,已引进多栅极装置通过增加栅极通道耦合、降低关态电流及减少短通道效应(short-channel effects,SCEs)来改善栅极控制。多栅极装置一般代表具有栅极结构或栅极结构的一部分设置于通道区的多于一面上方的装置。鳍式场效晶体管(Fin-like field effect transistors,FinFETs)和栅极环绕(gate-all-around,GAA)晶体管(两者也被称为非平面晶体管)为高效能且低漏电应用的已流行且有潜力的候选的多栅极装置的范例。鳍式场效晶体管具有由栅极在多于一面围绕的升高的通道,举例来说,栅极围绕从基底延伸的半导体材料的“鳍”的顶部和侧壁。相较于平面晶体管,此配置提供通道的较佳控制以及大幅地减少短通道效应(特别来说,通过减少次临界漏电流(即在关态的鳍式场效晶体管的源极与漏极之间的耦合)来达到)。栅极环绕晶体管具有可部分延伸或完全延伸于通道区周围的栅极结构,以在两面或更多面上提供入口至通道区。栅极围绕晶体管的通道区可由纳米线、纳米片、其他纳米结构及/或其他合适的结构形成。在一些实施例中,此通道区包含垂直堆叠的多个纳米结构(其水平延伸,进而提供水平定向的通道)。这种栅极环绕晶体管可被称为垂直堆叠水平式栅极环绕(vertically-stacked horizontal GAA,VGAA)晶体管。
在栅极环绕装置中,使用内部间隙壁来降低栅极结构与源极/漏极部件之间的电容及漏电。虽然传统具有内部间隙壁的栅极环绕装置一般来说已满足其预期目的,但是这些传统栅极环绕装置在各个方面不令人满意。
发明内容
在一些实施例中,提供半导体装置,半导体装置包含一第一半导体通道元件;第二半导体通道元件,位于第一半导体通道元件上方;以及介电部件,包含第一介电层和不同于第一介电层的第二介电层,其中介电部件夹设于第一半导体通道元件与第二半导体通道元件之间。
在一些其他实施例中,提供半导体装置,半导体装置包含第一半导体通道元件;第二半导体通道元件,位于第一半导体通道元件上方;以及第一介电部件和第二介电部件,设置于第一半导体通道元件与第二半导体通道元件之间,其中第一介电部件和第二介电部件的每一者包括第一介电层,第一介电层围绕第二介电层。
在另外一些实施例中,提供半导体装置的形成方法,此方法包含提供鳍结构,鳍结构包含交错的多个第一半导体层与多个第二半导体层;在鳍结构的通道区上方形成虚设栅极结构;将鳍结构的源极/漏极区凹陷,源极/漏极区与通道区相邻;将多个第二半导体层选择性且部分凹陷以形成多个凹口;在多个凹口上形成第一内部间隔层;以及在第一内部间隔层上形成第二内部间隔层,其中第一内部间隔层的组成不同于第二内部间隔层的组成。
附图说明
根据以下的详细说明并配合附图可以更加理解本发明实施例。应注意的是,根据本产业的标准惯例,图示中的各种部件(feature)并未必按照比例绘制。事实上,可能任意的放大或缩小各种部件的尺寸,以做清楚的说明。
图1显示依据本发明实施例的一个或多个方面的形成包含内部间隙壁部件的栅极环绕(GAA)装置的方法的流程图。
图2A、图2B、图3A、图3B、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A-图9G、图10A、图10B、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A和图20B显示依据本发明一个或多个方面的工件在依据图1的方法的制造过程期间的剖面示意图。
图21和图22显示依据本发明一个或多个方面的内部间隙壁部件的放大剖面示意图。
其中,附图标记说明如下:
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134:方块
200:工件
202:基底
204:外延堆叠物
206,208:外延层
210:鳍元件
212:浅沟槽隔离部件
214:介电鳍
216:沟槽
218:源极/漏极沟槽
222:虚设栅极堆叠物
224:虚设介电层
226:虚设电极层
228:硬遮罩
230:氧化层
232:氮化层
234:栅极间隙壁
236:内部间隙壁凹口
238:介电部件
240:第一内部间隔层
242:第二内部间隔层
244:外延源极/漏极部件
244N:n型外延源极/漏极部件
244P:p型外延源极/漏极部件
246:接触蚀刻停止层
248:层间介电层
250:栅极沟槽
252:金属栅极堆叠物
254:源极/漏极接点
260:第三内部间隔层
300:源极/漏极区
302,302’:图案膜
304:光阻层
400:通道区
450:第一介电部件
500:第二介电部件
1000:n型金属氧化物半导体装置区
2000:p型金属氧化物半导体装置区
D:横向深度
D1:第一厚度
D2:第二深度
D3:第三厚度
D4:第四深度
H:开口高度
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例,以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例,以求简化公开内容的说明。当然,这些仅为范例并非用以限定本发明。例如,以下的公开内容叙述了将一第一部件形成于一第二部件之上或上方,即表示其包含了所形成的上述第一部件与上述第二部件是直接接触的实施例,亦包含了尚可将附加的部件形成于上述第一部件与上述第二部件之间,而使上述第一部件与上述第二部件可能未直接接触的实施例。此外,公开内容中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的,并非用以限定各个实施例及/或所述外观结构之间的关系。
再者,为了方便描述附图中一元件或部件与另一(多个)元件或(多个)部件的关系,可使用空间相关用语,例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所示出的方位之外,空间相关用语也涵盖装置在使用或操作中的不同方位。所述装置也可被另外定位(例如,旋转90度或者位于其他方位),并对应地解读所使用的空间相关用语的描述。再者,除非另有详细说明,否则当用“大约”、“近似”及类似术语描述数字或数字范围时,此术语目的在涵盖在所描述的数字的+/-10%之内的数字。举例来说,术语“约5nm”涵盖4.5nm至5.5nm的尺寸范围。
本发明实施例整体上为有关于多栅极晶体管及其制造方法,且特别为有关于当制造栅极环绕(GAA)晶体管时的内部间隙壁(有时也被称为内部间隔层)的形成。
多栅极晶体管包含栅极结构形成于通道区的至少两面上的晶体管。这些多栅极晶体管可包含p型金属氧化物半导体装置或n型金属氧化物半导体装置。多栅极晶体管的范例包含因其鳍状结构来而命名的鳍式场效晶体管和栅极环绕(GAA)装置。栅极环绕装置包含具有其栅极结构或栅极结构的一部分形成于通道区的四面上(例如围绕通道区的一部分)的任何装置。本发明实施例可具有设置于纳米线通道、棒状通道、纳米片通道、纳米结构通道、圆柱状通道、柱状通道及/或其他合适的通道配置中的通道区。依据本发明实施例的装置可具有与单一、连续的栅极结构相关联的一个或多个通道区(例如纳米线、纳米片、纳米结构)。然而,本发明所属技术领域中具通常知识者将理解本发明实施例的启示可应用于单一通道(例如单一纳米线、单一纳米片、单一纳米结构)或任何数量的通道。本发明所属技术领域中具通常知识者可理解半导体装置的其他范例可受益于本发明实施例的各种方面。
随着鳍式场效晶体管的鳍宽度的尺寸缩小,通道宽度变化可导致不期望的变化和移动率的损失。目前正在研究以栅极环绕晶体管取代鳍式场效晶体管。在栅极环绕晶体管中,晶体管的栅极围绕通道形成,使得栅极围绕或环绕通道。这样的晶体管具有改善栅极对通道的静电控制,也减少了漏电流。栅极环绕晶体管包含各种间隙壁,例如内部间隙壁和栅极间隙壁(也被称为外部间隙壁、顶部间隙壁或主要间隙壁)。内部间隙壁用于降低栅极结构与源极/漏极部件之间的电容并防止栅极结构与源极/漏极部件之间的漏电。将内部间隙壁整合至栅极环绕晶体管中并非没有挑战性。举例来说,内部间隙壁和不同类型的源极/漏极部件的形成可包含一个或多个回蚀刻步骤,由于一个或多个回蚀刻制程可引起其他的缺陷,因此这些回蚀刻步骤可防止低介电常数介电材料用于各种间隙壁(例如设置于鳍的侧壁上的多晶间隙壁)中。这些其他的缺陷包含栅极间隙壁损坏、栅极顶部硬遮罩耗损、浅沟槽隔离(shallow-trench isolation,STI)结构耗损和内部间隙壁损坏。本发明实施例提供多层内部间隙壁部件,多层内部间隙壁部件包含第一内部间隙壁以及在第一内部间隙壁上方的一额外内部间隙壁。第一内部间隙壁可作为在用于形成源极/漏极部件或内部间隙壁的回蚀刻操作期间的至少一额外间隙壁的蚀刻停止层(etch stop layer,ESL)。此至少一额外内部间隙壁可包含第二间隙壁和选择性的第三间隙壁,第二间隙壁由低介电常数介电材料形成以降低寄生电容,第三间隙壁进一步防止回蚀刻操作引起的缺陷。
图1显示形成半导体装置(例如多栅极装置)的方法100。如本文所用,使用术语“多栅极装置”来描述具有一些栅极材料设置于装置的至少一通道的多个面上的装置,例如半导体装置。在一些范例中,多栅极装置可被称为栅极环绕装置,栅极环绕装置具有栅极材料设置于装置的至少一通道的至少四面上。通道区可被称为纳米线、纳米片、纳米结构、通道元件、半导体通道元件,本文使用的通道区包含各种几何形状(例如圆柱状、棒状、片状)和各种尺寸的通道区。
如本文所讨论的其他方法实施例和例示性装置,可以理解的是图2A、图2B、图3A、图3B、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A-图9G、图10A、图10B、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A和图20B所示的工件200的一部分可通过互补式氧化物半导体场效晶体管(complementary metal oxide semiconductor,CMOS)技术制程流程,且因此本文仅简要地描述一些制程。在完成制造过程之后,工件200将变为半导体装置。从这个层面来看,可互换使用术语工件200和半导体装置。再者,例示性的半导体装置可包含各种其他装置和部件,例如其他类型的装置,这些装置包含其他晶体管、双极性晶体管、电阻、电容、电感、二极管、熔丝、静态随机存取存储存储器(static random accessmemory,SRAM)及/或其他逻辑电路等,但是为了更好地理解本发明实施例的发明概念而将其简化。在一些实施例中,例示性装置包含多个半导体装置(例如晶体管),这些半导体装置包含可互连的n型栅极环绕晶体管、p型栅极环绕晶体管、p型场效晶体管(p-type fieldeffect transistors,PFETs)、n型场效晶体管(n-type field effect transistors,NFETs)等。再者,可以注意的是,方法100的制程步骤,包含参考图2A、图2B、图3A、图3B、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A-图9G、图10A、图10B、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A和图20B的任何描述以及本发明实施例提供的此方法的其他部分和例示性附图仅为例示性且不意图限制所附权利要求所具体记载的内容。
以A结尾的附图(例如图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、图17A、图18A、图19A或图20A)显示横跨多个鳍元件的多个源极/漏极区的局部剖面示意图(如下所述)。以B结尾的附图(例如图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B、图13B、图14B、图15B、图16B、图17B、图18B、图19B或图20B)显示沿鳍元件的局部剖面示意图。
请参照图1、图2A和图2B所示,方法100包含方块102,其中将基底202上的外延堆叠物204图案化以形成鳍元件210。在一些实施例中,基底202可为半导体基底,例如硅基底。基底202可包含各种层,其包含形成于半导体基底上的导电层或绝缘层。依据本发明所属技术领域已知的设计需求,基底202可包含各种掺杂配置。举例来说,不同的掺杂轮廓(例如n型井、p型井)可形成于基底202上设计用于不同的装置类型(例如n型栅极环绕晶体管、p型栅极环绕晶体管)的区域中。合适的掺杂步骤可包含掺杂物的离子布植及/或扩散制程。基底202可具有隔离部件设置于提供不同装置类型的区域之间。基底202可包含其他半导体,例如锗、碳化硅(SiC)、硅锗(SiGe)或钻石。或者,基底202可包含化合物半导体及/或合金半导体。再者,基底202可选择性地包含外延层(epi-layer),可应变以增强效能,可包含绝缘层上覆硅(silicon-on-insulator,SOI)结构,及/可具有其他合适的增强部件。在方法100的一实施例中,进行抗击穿(anti-punch through,APT)布植。举例来说,可在装置的通道区下方的区域中进行抗击穿布植,以防止击穿或不想要的扩散。
在一些实施例中,形成于基底202上方的外延堆叠物204包含第一组成的外延层206设置于第二组成的外延层208之间。第一组成不同于第二组成。在一实施例中,外延层206为SiGe,且外延层208为硅(Si)。然而,可能有包含提供有着不同氧化速率及/或蚀刻选择性的第一组成和第二组成的其他实施例。在一些实施例中,外延层206包含SiGe,且外延层208包含Si。
可以注意的是,如图2所示,4层的外延层206和4层的外延层208交替排列,其仅为例示性目的且不意图限制所附权利要求所具体记载的内容。可理解的是,任何数量的外延层可形成于外延堆叠物204中。外延层的数量取决于所期望的工件200的通道元件的数量。在一些实施例中,外延层208的数量在2与10之间。
在一些实施例中,每个外延层206具有厚度在约2nm至6nm的范围,例如3nm。外延层206可具有大致均匀的厚度。在一些实施例中,每个外延层208具有厚度在约6nm至12nm的范围,例如9nm。在一些实施例中,外延堆叠物204的外延层208可具有大致均匀的厚度。如以下进一步描述,外延层208或外延层208的一部分可作为后续形成的多栅极装置的通道元件,且依据装置效能考量选择外延层208的厚度。可最终移除通道区的外延层206,且外延层206作为定义后续形成的多栅极装置的通道区之间的垂直距离,且依据装置效能考量选择外延层206的厚度。因此,外延层206也可被称为牺牲层,而外延层208也可被称为通道层。
举例来说,外延堆叠物204的各层的外延成长可通过分子束外延(molecular beamepitaxy,MBE)制程、金属有机化学气相沉积(metalorganic chemical vapor deposition,MOCVD)制程及/或其他合适的外延成长制程进行。在一些实施例中,外延成长层例如外延层208包含与基底202相同的材料。在一些实施例中,外延层206和208包含与基底202不同的材料。如上所述,在一些范例中,外延层206包含外延成长硅锗(SiGe)层,且外延层208包含外延成长硅(Si)层。或者,在一些实施例中,外延层206和208的任一者可包含其他材料(例如锗)、化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP及/或GaInAsP)或前述的组合。如以上讨论,可依据所提供的不同氧化性质及蚀刻选择性来选择外延层206和208的材料。在一些实施例中,外延层206和208大致不含掺杂物(即具有外在掺杂物浓度在约0cm-3至约1x1017cm-3)。举例来说,在外延成长制程期间不意图进行掺杂。
在方块102中,将基底202上方的外延堆叠物204图案化以形成从基底202延伸的鳍元件210。在一些实施例中,此图案化也蚀刻基底202,使得每个鳍元件210包含从基底202形成的下部及由外延堆叠物204形成的上部。上部包含外延堆叠物204的每个外延层,即包含外延层206和208。鳍元件210可通过使用合适的制程制造,合适的制程包含双重图案化或多重图案化制程。一般来说,双重图案化或多重图案化制程结合了光微影和自对准制程,以创造具有较小间距的图案,举例来说,此图案具有比使用单一直接光微影制程可获得的间距更小的图案。举例来说,在一实施例中,牺牲层形成于基底上方,并通过使用光微影制程图案化。间隔物通过使用自对准制程形成于图案化牺牲层旁边。接着,移除牺牲层,且可接着通过蚀刻外延堆叠物204来使用剩下的间隔物或心轴将鳍元件210图案化。蚀刻制程可包含干蚀刻、湿蚀刻、反应性离子蚀刻(reactive ion etching,RIE)及/或其他合适的制程。
请参照图1和图2A,方法100包含方块104,其中形成浅沟槽隔离(shallow trenchisolation,STI)部件212。举例来说,在一些实施例中,先在基底202上方沉积介电层,介电材料填充沟槽216。在一些实施例中,介电层可包含氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(fluorine-doped silicate glass,FSG)、低介电常数介电质、前述的组合及/或其他合适的材料。在各种范例中,介电层可通过化学气相沉积制程、次常压化学气相沉积(subatmospheric CVD,SACVD)制程、可流动化学气相沉积制程、原子层沉积(atomic layerdeposition,ALD)制程、物理气相沉积(physical vapor deposition,PVD)制程及/或其他合适的制程沉积。接着,例如通过化学机械研磨(chemical mechanical polishing,CMP)制程将沉积的介电材料变薄及平坦化。平坦化的介电层进一步通过干蚀刻制程、湿蚀刻制程及/或前述的组合凹陷以形成浅沟槽隔离部件212。鳍元件210突出于浅沟槽隔离部件212之上。在一些实施例中,介电层(及后续形成的浅沟槽隔离部件212)可包含多层结构,例如具有一个或多个衬垫层。
在一些实施例中,如图2A所示,在方法100的方块104中,也形成介电鳍214。在一些实施例中,在沉积介电材料以形成介电层之后,将介电层图案化以形成与鳍元件210平行延伸的狭缝。接着,介电鳍214的材料沉积于工件200上方以填充狭缝。介电鳍214的材料不同于形成浅沟槽隔离部件212的介电材料。这使得当将介电层凹陷蚀,可选择性蚀刻浅沟槽隔离部件212的介电层,留下也突出于浅沟槽隔离部件212之上的介电鳍214。在一些实施例中,介电鳍214的材料可包含氮化硅、氮碳化硅、碳化硅、氧化铝、氧化锆或其他合适的材料。如图2A所示,介电鳍214设置于鳍元件210之间并用以将相邻装置的源极/漏极部件隔开。介电鳍214也可被称为虚设鳍或混合鳍。在一些其他实施例中,介电鳍214的上部可在栅极切割制程期间移除并以不同或相似于介电鳍的介电材料取代。
请参照图1和图3B,方法100包含方块106,其中在鳍元件210的通道区400上方形成虚设栅极堆叠物222。在一些实施例中,采用栅极取代或栅极后制制程,虚设栅极堆叠物222作为高介电常数金属栅极堆叠物的占位物,且将移除虚设栅极堆叠物222并以高介电常数金属栅极堆叠物取代。可能为其他制程或配置。在一些实施例中,虚设栅极堆叠物222形成于基底202上方,且至少部分沉积于鳍元件210上方。鳍元件210在虚设栅极堆叠物222下方的部分为通道区400。虚设栅极堆叠物222也可定义与通道区400相邻且在通道区400两侧的源极/漏极(source/drain,S/D)区300。可以注意的是,图3A看不到通道区400。
在显示的实施例中,方块106先在鳍元件210上方形成虚设介电层224。在一些实施例中,虚设介电层224可包含氧化硅、氮化硅、高介电常数介电材料及/或其他合适的材料。在各种范例中,虚设介电层224可通过化学气相沉积制程、次常压化学气相沉积(SACVD)制程、可流动化学气相沉积制程、原子层沉积制程、物理气相沉积制程及/或其他合适的制程沉积。举例来说,可使用虚设介电层224以防止后续制程(例如后续虚设栅极堆叠物的形成)对鳍元件210造成损坏。之后,方块106形成虚设栅极堆叠物222的其他部分,虚设栅极堆叠物222的其他部分包含虚设电极层226和硬遮罩228,硬遮罩228可包含多层,例如氧化层230和氮化层232。在一些实施例中,虚设栅极堆叠物222通过各种制程步骤形成,例如层沉积、图案化、蚀刻和其他合适的加工步骤。例示层沉积制程包含化学气相沉积(包含低压化学气相沉积(low pressure CVD,LPCVD)和等离子体辅助化学气相沉积(plasma enhanced CVD,PECVD))、物理气相沉积、原子层沉积、热氧化、电子束蒸镀、其他合适的沉积技术或前述的组合。举例来说,图案化制程可包含微影制程(例如光微影或电子束微影),微影制程可还包含光阻涂布(例如旋涂)、软烤、遮罩对准、曝光、曝光后烘烤、光阻显影、清洗、干燥(例如旋干及/或硬烤)、其他合适的微影技术及/或前述的组合。在一些实施例中,蚀刻制程可包含干蚀刻(例如反应性离子蚀刻)、湿蚀刻及/或其他蚀刻方法。在一些实施例中,虚设电极层226可包含多晶硅(polycrystalline silicon,polysilicon)。在一些实施例中,硬遮罩228包含氧化层230,例如垫氧化层,垫氧化层可包含氧化硅。在一些实施例中,硬遮罩228包含氮化层232,例如垫氮化层,垫氮化层可包含氮化硅、氮氧化硅及/或碳化硅。
请参照图3B,在一些实施例中,在形成虚设栅极堆叠物222之后,移除鳍元件210的源极/漏极区300中的虚设介电层224,也就是移除虚设电极层226未覆盖的虚设介电层224。移除制程可包含湿蚀刻、干蚀刻及/或前述的组合。选择蚀刻制程以选择性蚀刻虚设介电层224而大致不蚀刻鳍元件210、硬遮罩228和虚设电极层226。
请参照图1、图4A和图4B,方法100包含方块108,其中在虚设栅极堆叠物222的侧壁上形成栅极间隙壁。在一些实施例中,在工件200上方(包含在虚设栅极堆叠物222的顶表面和侧壁上)顺应性沉积用于形成栅极间隙壁的间隙壁材料,以形成间隔材料层。本文可使用术语“顺应性”以便于描述在各区域上方具有大致均匀厚度的一层。间隔材料层可包含介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅、氮碳化硅、碳氧化硅、氮碳氧化硅及/或前述的组合。在一些实施例中,间隔材料层包含多层,例如主要间隙壁、衬垫层和类似物。间隙壁材料可通过使用例如化学气相沉积制程、次常压化学气相沉积(SACVD)制程、可流动化学气相沉积制程、原子层沉积制程、物理气相沉积制程或其他合适的制程沉积于虚设栅极堆叠物222上方。接着,在非等向性蚀刻制程中回蚀刻间隔材料层,以形成栅极间隙壁234。非等向性蚀刻制程暴露出鳍元件210与虚设栅极堆叠物222相邻且未被虚设栅极堆叠物222覆盖的部分(例如在源极/漏极区中)。间隔材料层在虚设栅极堆叠物222正上方的部分可通过此非等向性蚀刻制程完全移除,而栅极间隙壁234保留在虚设栅极堆叠物222的侧壁上。
请参照图1、图4A和图4B,方法100包含方块110,其中将鳍元件210的源极/漏极区300凹陷。在一些实施例中,通过干蚀刻或合适的蚀刻制程来蚀刻鳍元件210未被虚设栅极堆叠物222和栅极间隙壁234覆盖的部分,以形成源极/漏极沟槽218。举例来说,干蚀刻制程可使用含氧气体、含氟气体(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯气体(例如CHCl3、CCl4及/或BCl3)、含溴气体(例如HBr及/或CHBr3)、含碘气体、其他合适的气体及/或等离子体及/或前述的组合。在图4A和图4B所示的一些实施例中,将鳍元件210的上部凹陷,以暴露出外延层206和208。在一些实施例中,也将鳍元件210的下部的至少一部分凹陷。也就是说,源极/漏极沟槽218可延伸至最底部外延层206下方。在方块110的操作之后,鳍元件210的源极/漏极区300可变得齐平于或低于浅沟槽隔离部件212的顶表面。
请参照图1和图5B,方法100包含方块112,其中将鳍元件210的外延层206凹陷。在图5B显示的一些实施例中,选择性蚀刻并部分凹陷暴露于源极/漏极沟槽218中的外延层206以形成内部间隙壁凹口236,而大致未蚀刻暴露的外延层208。在一实施例中,其中外延层208基本上由硅组成,而外延层206基本上由SiGe组成,外延层206的选择性凹陷可包含SiGe氧化制程紧接着SiGe氧化物移除。在这些实施例中,SiGe氧化制程可包含使用臭氧。在一些实施例中,选择性凹陷可为选择性等向性蚀刻制程(例如选择性干蚀刻制程或选择性湿蚀刻制程),且外延层206的凹陷程度通过蚀刻制程的持续时间来控制。在一些实施例中,选择性湿蚀刻制程可包含氟化氢(HF)或NH4OH蚀刻剂,如图5B所示,内部间隙壁凹口236从源极/漏极沟槽218向内延伸。
请参照图1、图6A和图6B,方法100包含方块114,其中沉积第一内部间隔层240。在一些实施例中,第一内部间隔层240可通过化学气相沉积、等离子体辅助化学气相沉积、低压化学气相沉积、原子层沉积或其他合适的方法沉积。在一些范例中,形成第一内部间隔层240至厚度在约1nm与约3nm之间。第一内部间隔层240用以保护栅极间隙壁234、硬遮罩228和外延层208免于在内部间隔层的后撤(回蚀刻)期间损坏。在一些实施例中,第一内部间隔层240可由金属氧化物或富含碳的氮碳化硅形成。此处的金属氧化物可包含氧化铝、氧化锆、氧化钽、氧化钇、氧化钛、氧化镧或其他合适的金属氧化物。富含碳的氮碳化硅可包含碳含量大于5%。在图6A和图6B显示的实施例中,第一内部间隔层240可顺应性沉积于硬遮罩228的顶表面、栅极间隙壁234的顶表面和侧壁、基底202暴露于源极/漏极沟槽218中的部分、介电鳍214的顶表面和侧壁上方。
请参照图1、图7A和图7B,方法100包含方块116,其中沉积第二内部间隔层242。在一些实施例中,第二内部间隔层242可通过化学气相沉积、等离子体辅助化学气相沉积、低压化学气相沉积、原子层沉积或其他合适的方法沉积。在一些范例中,形成第二内部间隔层242至厚度在约3nm与约5nm之间。由于内部间隙壁凹口236未被第一内部间隔层240填满,因此第二内部间隔层242也沉积于内部间隙壁凹口236中。在内部间隙壁凹口236中的第二内部间隔层242的厚度可在约5nm与约20nm之间。在一些实施例中,第二内部间隔层242可由氧化硅、氮碳氧化硅、碳氧化硅或其他低介电常数材料形成。第二内部间隔层242可为多孔的以进一步降低介电常数。在一些范例中,第二内部间隔层242的碳含量小于第一内部间隔层240的碳含量。在图7A和图7B显示的实施例中,第二内部间隔层242可顺应性沉积于第一内部间隔层240上方。
请参照图1、图8A和图8B,方法100包含方块118,其中将第二内部间隔层242后撤。在一些实施例中,等向性且选择性回蚀刻第二内部间隔层242直到完全移除在硬遮罩288的顶表面上、栅极间隙壁234的顶表面和侧壁上、基底202暴露于源极/漏极沟槽218中的部分以及介电鳍214的顶表面和侧壁上的第二内部间隔层242。如上所述,第一内部间隔层240的组成不同于第二内部间隔层242的组成,使得可选择性蚀刻第二内部间隔层242,而第一内部间隔层240经历缓慢的蚀刻速率。在一些实施例中,在方块118中,第二内部间隔层242对第一内部间隔层240的蚀刻选择性大于5。在一些实施例中,方块118进行的等向性蚀刻可包含使用氟化氢、氟气、氢、氨、三氟化氮或其他氟基蚀刻剂。在图8A和图8B显示的一些实施例中,蚀刻内部间隙壁凹口236中的第二内部间隔层242,使得第二内部间隔层242的外表面不与栅极间隙壁234的侧壁共平面。
请参照图1、图9A和图9B,方法100包含方块124,其中形成外延源极/漏极部件244。在外延成长制程期间,虚设栅极堆叠物222和栅极间隙壁234将外延源极/漏极部件244限制于鳍元件210的源极/漏极区300。在一些范例中,介电鳍214可用于防止由不同鳍元件210形成的外延源极/漏极部件244彼此接触。在不存在介电鳍214的其他实施例中,与鳍元件210相邻的外延源极/漏极部件244可能合并,假使这种合并不会导致半导体装置的故障。合适的外延制程包含化学气相沉积的沉积技术(例如气相外延(vapor-phase epitaxy,VPE)及/或超高真空化学气相沉积(ultra-high vacuum CVD,UHV-CVD))、分子束外延(MBE)及/或其他合适的制程。外延成长制程可使用气体及/或液体前驱物,这些前驱物与基底202和外延层208的组成反应。在图9B显示的实施例中,外延源极/漏极部件244与外延层208和基底202暴露于源极/漏极沟槽218中的部分直接接触。在这些实施例中,外延源极/漏极部件244不与外延层206直接接触。取而代之的是,外延源极/漏极部件244与第一内部间隔层240和沉积于内部间隙壁凹口236中的第二内部间隔层242直接接触。
在各种实施例中,外延源极/漏极部件244可包含Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、SiP或其他合适的材料。外延源极/漏极部件244可在外延制程期间通过引进掺杂物种来原位掺杂,掺杂物种包含p型掺杂物(例如硼或BF2)、n型掺杂物(例如磷或砷)及/或其他合适的掺杂物,其包含前述的组合。如果外延源极/漏极部件244并非原位掺杂,则进行布植制程(例如接面布植制程)以对外延源极/漏极部件244掺杂。在一例示性的实施例中,在n型金属氧化物半导体(n-type MOS,NMOS)装置中的外延源极/漏极部件244包含SiP,而在p型金属氧化物半导体(p-type MOS,PMOS)装置中的外延源极/漏极部件244包含SiGeB。在一些实施例中,n型金属氧化物半导体和p型金属氧化物半导体装置的外延源极/漏极部件244个别形成,使n型金属氧化物半导体和p型金属氧化物半导体装置具有不同的外延源极/漏极部件244。如第9C-9G图所示的例示性制程,在方块118中,将第二内部间隔层242后撤之后,沉积图案膜302以覆盖p型金属氧化物半导体装置区2000和n型金属氧化物半导体装置区1000。沉积光阻层304并将光阻层304图案化以暴露出在n型金属氧化物半导体装置区1000上方的图案膜302,使得可移除暴露的图案膜302。接着,移除p型金属氧化物半导体装置区2000的图案化光阻层304。图案化光阻层的移除也可移除在p型金属氧化物半导体装置区2000上方(硬遮罩288的顶表面上、栅极间隙壁234的顶表面和侧壁上、基底202暴露于源极/漏极沟槽218中的部分以及介电鳍214的顶表面和侧壁上)的第一内部间隔层240。有着图案膜302遮蔽p型金属氧化物半导体装置区2000,对n型金属氧化物半导体装置区1000进行方块124的操作以形成n型外延源极/漏极部件244N。之后,可使用相似技术以形成p型外延源极/漏极部件244P。形成不同的图案膜302’并将图案膜302’图案化以遮蔽n型金属氧化物半导体装置区1000,接着对p型金属氧化物半导体装置区2000进行方块124的操作以形成p型外延源极/漏极部件244P。外延源极/漏极部件244的形成顺序可颠倒,可先形成p型金属氧化物半导体装置区2000的p型外延源极/漏极部件244P。在形成外延源极/漏极部件244期间不移除第一内部间隔层240(在硬遮罩288的顶表面上、栅极间隙壁234的顶表面和侧壁上、介电鳍214的表面上方)的范例中,可进行湿清洁制程以移除第一内部间隔层240(在硬遮罩288的顶表面上、栅极间隙壁234的顶表面和侧壁上、介电鳍214的表面上方)。在一些实施例中,湿清洁制程可包含使用硫酸和过氧化氢的混合物(sulfuric acid and hydrogenperoxide mixture,SPM)溶液、RCA标准清洁-1(RCA standard clean-1,SC-1)溶液或RCA标准清洁-2(RCA standard clean-2,SC-2)溶液。在图9A和图9B显示的实施例中,第一内部间隔层240仅显示于内部间隙壁凹口236中。
再者,硅化物或锗硅化物可形成于外延源极/漏极部件244上。举例来说,可通过在外延源极/漏极部件244上方沉积金属层,并将金属层退火使得金属层与外延源极/漏极部件244中的硅反应以形成金属硅化物,以形成金属硅化物,例如硅化镍、硅化钛、硅化钽或硅化钨。可移除未反应的金属层。
请参照图1、图10A和图10B,方法100包含方块126,其中形成层间介电(interlayerdielectric,ILD)层248。在一些实施例中,在形成层间介电层248之前,形成接触蚀刻停止层(contact etch stop layer,CESL)246。在一些范例中,接触蚀刻停止层246包含氮化硅层、氧化硅层、氮氧化硅层及/或本发明所属技术领域者已知的其他材料。接触蚀刻停止层246可通过原子层沉积、等离子体辅助化学气相沉积(PECVD)制程及/或其他合适的沉积或氧化制程形成。在一些实施例中,层间介电层248包含材料例如四乙氧基硅烷(tetraethylorthosilicate,TEOS)氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅,例如硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、熔融硅石玻璃(fused silica glass,FSG)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼掺杂硅酸盐玻璃(boron dopedsilicon glass,BSG)及/或其他合适的介电材料。层间介电层248可通过等离子体辅助化学气相沉积制程或其他合适的沉积技术沉积。在一些实施例中,在形成层间介电层248之后,可将工件200退火以改善层间介电层248的完整性。
在一些范例中,在沉积层间介电层248之后,可进行平坦化制程以移除多余的介电材料。举例来说,平坦化制程包含化学机械平坦化(chemical mechanical planarization,CMP)制程,化学机械平坦化制程移除层间介电层248(和如果存在的接触蚀刻停止层246)在虚设栅极堆叠物222上方的部分,并将工件200的顶表面平坦化。在一些实施例中,如图10A和图10B所示,化学机械平坦化制程也移除硬遮罩228并暴露出虚设电极层226。
在一些范例中,栅极间隙壁234沿虚设栅极堆叠物222的侧壁和介电鳍214的侧壁形成,且可具有由栅极间隙壁234定义的间隙。如图10A所示,间隙可填充介电部件238。介电部件238可由氧化硅、氮氧化硅、氮碳化硅、碳氧化硅、氮碳氧化硅及/或前述的组合。在一些实施例中,介电部件238可包含在间隙形成之后沉积的一个或多个介电材料。举例来说,第一内部间隔层240、第二内部间隔层242、第三内部间隔层260(以下将描述,如图14B和图15B所示)和接触蚀刻停止层(CESL)246可沉积于间隙中,并部分或完全填充间隙,形成介电部件238的全部或一部分。
请参照图1、图11A和图11B,方法100包含方块128,其中移除虚设栅极堆叠物222。在一些实施例中,虚设栅极堆叠物222的移除导致在通道区400上方形成栅极沟槽250。最终的高介电常数栅极结构(例如包含高介电常数介电层和金属栅极电极)可后续形成于栅极沟槽250中,如以下将描述。方块128可包含对虚设栅极堆叠物222中的材料有选择性的一个或多个蚀刻制程。举例来说,虚设栅极堆叠物222的移除可通过对虚设电极层226有选择性的选择性湿蚀刻、选择性干蚀刻或前述的组合来进行。鳍元件210的外延层206和208暴露于栅极沟槽250中。
请参照图1、图11A和图11B,方法100包含方块130,其中释放外延层208。方块130的操作移除第一内部间隔层240之间的外延层206,且在通道区400的外延层208在垂直方向上间隔开每个外延层206的厚度。外延层206的选择性移除将外延层208释放为通道元件。可以注意的是,为了简单起见,使用相同的符号208标注通道元件。方块130可通过选择性干蚀刻、选择性湿蚀刻或其他选择性蚀刻制程来进行。在一些实施例中,选择性湿蚀刻包含氢氧化铵-过氧化氢-水混合物(ammonia hydroxide-hydrogen peroxide-water mixture,APM)蚀刻。在一些实施例中,选择性移除包含SiGe氧化紧接着硅锗氧化物移除。举例来说,氧化可通过臭氧清洁提供,且接着硅锗氧化物通过蚀刻剂(例如NH4OH)移除。
请参照图1、图12A和图12B,方法100包含方块132,其中形成金属栅极堆叠物252。金属栅极堆叠物252可为高介电常数金属栅极堆叠物,然而也可能有其他组成。在一些实施例中,金属栅极堆叠物252形成于工件200上方的栅极沟槽250中,且沉积于外延层206移除后留下的空间中。就此而言,金属栅极堆叠物252环绕每个鳍元件210中的每个外延层208。在各种实施例中,金属栅极堆叠物252(或高介电常数金属栅极堆叠物)包含界面层、形成于界面层上方的高介电常数栅极介电层及/或形成于高介电常数栅极介电层上方的栅极电极层。如本文所使用及描述的高介电常数栅极介电层包含具有高介电常数的介电材料,例如大于热氧化硅的介电常数(~3.9)。用于金属栅极堆叠物252中的栅极电极层可包含金属、金属合金或金属硅化物。此外,金属栅极堆叠物252的形成可包含沉积以形成各种栅极材料、一个或多个衬垫层以及一个或多个化学机械研磨制程以移除多余的栅极材料,并进而将工件200的顶表面平坦化。
在一些实施例中,金属栅极堆叠物252的界面层可包含介电材料,例如氧化硅、硅酸铪或氮氧化硅。界面层可通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法形成。金属栅极堆叠物252的高介电常数栅极介电层可包含高介电常数介电层,例如氧化铪。或者,金属栅极堆叠物252的高介电常数栅极介电层可包含其他高介电常数介电质,例如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)、前述的组合或其他合适的材料。高介电常数栅极介电层可通过原子层沉积、物理气相沉积(PVD)、化学气相沉积、氧化及/或其他合适的方法形成。
金属栅极堆叠物252的栅极电极层可包含单一层或多层结构,例如有着选择的功函数的金属层以增强装置效能(功函数金属层)、衬垫层、润湿层、粘着层、金属合金或金属硅化物各种组合。举例来说,金属栅极堆叠物252的栅极电极层可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合适的金属材料或前述的组合。在各种实施例中,金属栅极堆叠物252的栅极电极层可通过原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀或其他合适的制程形成。再者,可个别形成n型场效晶体管(N-FET)和p型场效晶体管(P-FET)的栅极电极层,其可使用不同的金属层(例如用于提供不同的n型和p型功函数金属层)。在各种实施例中,可进行化学机械研磨制程以移除金属栅极堆叠物252的栅极电极层的多余金属,且进而提供金属栅极堆叠物252大致平坦的顶表面。金属栅极堆叠物252包含设置于通道区400中的外延层208之间的部分。
请参照图1、图13A和图13B,方法100包含方块134,其中进行进一步制程。工件200可经历进一步制程以形成半导体装置。这些进一步制程可包含例如源极/漏极接点254的形成。在此范例中,源极/漏极接点254的开口形成通过层间介电层248,且金属填充层形成于开口中。在一些实施例中,阻障层或衬垫可形成于外延源极/漏极部件244与源极/漏极接点254之间。源极/漏极接点254与栅极接点(未显示)允许形成于方法100中的栅极环绕晶体管电性耦接至多层互连结构,多层互连结构包含一个或多个金属间介电层中的多个接触导通孔和金属线层。多层互连结构被配置以连接各种多栅极装置、存储器装置、输入/输出装置、功率栅极装置、被动装置和其他装置,以形成功能电路。
请参照图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A和图20B,在一些其他实施例中,方法100可包含选择性的操作方块120和122以整合第三内部间隔层260。请参照图1、图14A和图14B,方法100可选择性包含方块120,其中在方块118完成之后,在工件200上方沉积第三内部间隔层260。也就是说,第三内部间隔层260沉积于后撤的第二内部间隔层242上方。在一些实施例中,第三内部间隔层260的沉积方法和材料可大致相似于第一内部间隔层240的沉积方法和材料。相似于第一内部间隔层240,第三内部间隔层260可由金属氧化物或有着碳含量大于5%的氮碳化硅形成。第三内部间隔层260用以保护低介电常数的第二内部间隔层242。已观察到的是,低介电常数介电材料倾向于比高介电常数介电材料蚀刻得更快。在本发明实施例中,第一内部间隔层240和第三内部间隔层260具有比第二内部间隔层242更大的介电常数。
请参照图1、图15A和图15B,方法100可选择性包含方块122,其中将第三内部间隔层260后撤。在一些实施例中,等向性回蚀刻第三内部间隔层260直到完全移除在虚设栅极堆叠物222的顶表面上、栅极间隙壁234的顶表面和侧壁上以及介电鳍214的顶表面和侧壁上的第三内部间隔层260。在一些实施例中,方块122进行的等向性蚀刻可包含使用氟化氢、氟气、氢、氨、三氟化氮或其他氟基蚀刻剂。在一些其他实施例中,方块122进行的等向性蚀刻可包含湿清洁制程,湿清洁制程包含使用SPM溶液、SC-1溶液或SC-2溶液。
如图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A和图20B所示,方块122完成之后的操作与以上缺少第三内部间隔层260的实施例所描述的方块124、126、128、130、132和134相似。将省略这些操作的细节,且为了简洁起见提供对这些附图的简要描述。图16A和图16显示移除在硬遮罩228、栅极间隙壁234和介电鳍214上方的第一内部间隔层240,且与外延源极/漏极部件244形成期间的光阻层或湿清洁制程一同移除。图17A和图17B显示在移除虚设栅极堆叠物222之前,将工件200平坦化以暴露出虚设电极层226。在图18A和图18B中,移除虚设栅极堆叠物222,暴露出通道区400上方的栅极沟槽250中的外延层206和208。在图19A和图19B中,选择性移除栅极沟槽250中的外延层206,以释放外延层208作为通道元件。此外,逐层沉积金属栅极堆叠物252以环绕通道区400中释放的外延层208。在图20A和图20B中,将工件200平坦化并形成源极/漏极接点254,以将栅极环绕晶体管连接至多层互连结构(未显示)。
取决于是否存在第三内部间隔层260,内部间隙壁凹口236中或周围的内部间隔层的配置是不同的。图13B中的点状矩形区域的放大视图显示于图21。请参照图21,内部间隙壁凹口236可具有横向深度D在约5nm与约20nm之间,且开口高度H在约5nm与约20nm之间。第一内部间隔层240可具有第一厚度D1在约1nm与约3nm之间。第二内部间隔层242可具有第二深度D2(从第一内部间隔层240开口测量)在约2nm与约15nm之间。在第一内部间隔层240的外缘与外延层208的侧壁之间的第四深度D4可在约0nm与约3nm之间。也就是说,在一些范例中,第一内部间隔层240的外缘与外延层208的侧壁可为共平面。图21中的第一内部间隔层240和第二内部间隔层242可被共同视为第一介电部件450。第一介电部件450的第一内部间隔层240为曲面并环绕第二内部间隔层242。如图21所示,两相邻的外延层208通过第一介电部件450隔开。换句话说,第一介电部件450夹设于两相邻的外延层208之间。在图21显示的实施例中,金属栅极堆叠物252在两相邻外延层208之间的部分直接接触第一内部间隔层240。第一介电部件450的第二内部间隔层242与金属栅极堆叠物252在两相邻外延层208之间的部分间隔开。低介电常数的第二内部间隔层242设置于金属栅极堆叠物252(在两相邻外延层208之间)的部分与外延源极/漏极部件244之间,以降低寄生电容。选择在第一介电部件450中的第一内部间隔层240和第二内部间隔层242的厚度,使得第一内部间隔层240可作为蚀刻停止层,且将第二内部间隔层242的厚度最大化以降低电容。
相似地,图20B中的点状矩形区域的放大视图显示于图22。在设置第三内部间隔层260的实施例中,第三内部间隔层260可具有第三厚度D3在约1nm与3nm之间。图22中的其他部件尺寸(例如D、D1、D2、D4和H)可相似于图21显示的部件尺寸,故不重复描述。图22中的第一内部间隔层240、第二内部间隔层242和第三内部间隔层260可被共同视为第二介电部件500。第二介电部件500的第一内部间隔层240为曲面并环绕第二内部间隔层242和第三内部间隔层260。如图22所示,两相邻的外延层208通过第二介电部件500隔开。换句话说,第二介电部件500夹设于两相邻的外延层208之间。在图22显示的实施例中,金属栅极堆叠物252在两相邻外延层208之间的部分直接接触第一内部间隔层240。第二介电部件500的第二内部间隔层242和第三内部间隔层260与金属栅极堆叠物252在两相邻外延层208之间的部分间隔开。低介电常数的第二内部间隔层242设置于金属栅极堆叠物252(在两相邻外延层208之间)的部分与外延源极/漏极部件244之间,以降低寄生电容。选择在第一介电部件450中的第一内部间隔层240、第二内部间隔层242和第三内部间隔层260的厚度,使得第一内部间隔层240可作为蚀刻停止层,且将第二内部间隔层242的厚度最大化以降低电容,而第三内部间隔层260充分保护第二内部间隔层242。
虽然不意图限制,但是本发明一个或多个实施例为半导体装置及其形成提供了许多优点。举例来说,半导体装置提供多层内部间隔层以保护硬遮罩、栅极间隙壁、通道层,并整合低介电常数介电材料。在一些实施例中,沉积第一内部间隔层作为蚀刻停止层,同时沉积第二内部间隔层以引进低介电常数介电材料。在其他实施例中,沉积第三内部间隔层以保护低介电常数的第二内部间隔层。再者,多层内部间隔层的形成方法可容易地整合至现有的半导体装置制造过程中。
在一例示性方面,本发明实施例为有关于半导体装置,半导体装置包含一第一半导体通道元件和位于第一半导体通道元件上方的第二半导体通道元件,以及包含第一介电层和不同于第一介电层的第二介电层的介电部件。介电部件夹设于第一半导体通道元件与第二半导体通道元件之间。
在一些实施例中,第一介电层环绕第二介电层。在一些实施例中,第一介电层直接接触第一半导体通道元件和第二半导体通道元件。在一些实施例中,第二介电层通过第一介电层与第一半导体通道元件和第二半导体通道元件间隔开。在一些实施例中,半导体装置还包含金属栅极堆叠物,金属栅极堆叠物环绕第一半导体通道元件和第二半导体通道元件,且金属栅极堆叠物的一部分直接接触介电部件。在一些实施例中,其中第二介电层通过第一介电层与金属栅极堆叠物间隔开。在一些实施例中,半导体装置还包含源极/漏极部件,且介电部件的第一介电层和第二介电层直接接触源极/漏极部件。在一些范例中,介电部件还包含第三介电层,第三介电层设置于源极/漏极部件与介电部件的第二介电层之间。
在另一例示性的方面中,本发明实施例为有关于半导体装置,半导体装置包含第一半导体通道元件和位于第一半导体通道元件上方的第二半导体通道元件,以及设置于第一半导体通道元件与第二半导体通道元件之间的第一介电部件和第二介电部件。第一介电部件和第二介电部件的每一者包含第一介电层,第一介电层围绕第二介电层。在一些实施例中,第一介电层的介电常数大于第二介电层的介电常数。在一些实施例中,第一介电层包含氮氧化硅、氮碳化硅、碳氧化硅或氮碳氧化硅,且第二介电层包含多孔的氮碳氧化硅或氧化硅。在一些实施例中,半导体装置还包含金属栅极堆叠物,金属栅极堆叠物环绕第一半导体通道元件和第二半导体通道元件,且金属栅极堆叠物的一部分延伸于第一介电部件与第二介电部件之间。在一些实施例中,第一介电部件和第二介电部件的第二介电层通过第一介电层与金属栅极堆叠物间隔开。在一些实施例中,第一介电部件和第二介电部件的每一者还包含第三介电层,且第一介电层和第三介电层共同完全地环绕第二介电层。
在另一例示性的方面中,本发明实施例为有关于半导体装置的形成方法,半导体装置的形成方法包含提供鳍结构,鳍结构包含交错的多个第一半导体层与多个第二半导体层,在鳍结构的通道区上方形成虚设栅极结构,将鳍结构的源极/漏极区凹陷,源极/漏极区与通道区相邻,将多个第二半导体层选择性且部分凹陷以形成多个凹口,在多个凹口上形成第一内部间隔层,以及在第一内部间隔层上形成第二内部间隔层,第一内部间隔层的组成不同于第二内部间隔层的组成。
在一些实施例中,此方法还包含将第二内部间隔层选择性凹陷。在一些实施例中,将第二内部间隔层选择性凹陷的步骤移除未设置于多个凹口中的第二内部间隔层。在一些实施例中,此方法还包含在第二内部间隔层上形成第三内部间隔层,并将第三内部间隔层选择性凹陷。在一些范例中,第一内部间隔层和第三内部间隔层包含氮氧化硅、氮碳化硅、碳氧化硅或氮碳氧化硅,且第二内部间隔层包含多孔的氮碳氧化硅或氧化硅。在一些实施例中,第一内部间隔层或第三内部间隔层的碳含量大于第二内部间隔层的碳含量。
前述内文概述了许多实施例的特征,使本技术领域中技术人员可以从各个方面更加了解本发明实施例。本技术领域中技术人员应可理解,且可轻易地以本发明实施例为基础来设计或修饰其他制程及结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本发明的发明精神与范围。在不背离本发明的发明精神与范围的前提下,可对本发明实施例进行各种改变、置换或修改。
Claims (1)
1.一种半导体装置,包括:
一第一半导体通道元件;
一第二半导体通道元件,位于该第一半导体通道元件上方;以及
一介电部件,包括一第一介电层和不同于该第一介电层的一第二介电层,其中该介电部件夹设于该第一半导体通道元件与该第二半导体通道元件之间。
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