CN109817618A - 互补场效应晶体管中的外延结构 - Google Patents

互补场效应晶体管中的外延结构 Download PDF

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CN109817618A
CN109817618A CN201810960672.5A CN201810960672A CN109817618A CN 109817618 A CN109817618 A CN 109817618A CN 201810960672 A CN201810960672 A CN 201810960672A CN 109817618 A CN109817618 A CN 109817618A
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transistor
source
drain region
substrate
region
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CN109817618B (zh
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朱利安·弗罗吉尔
谢瑞龙
史帝文·本利
帕尼特·H·苏瓦纳
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GlobalFoundries US Inc
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GlobalFoundries Inc
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    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Abstract

本发明涉及互补场效应晶体管中的外延结构，揭示形成集成电路结构的方法，该集成电路结构包括延伸至衬底中的隔离元件，以及接触该隔离元件的第一晶体管的源/漏区。该隔离元件自该衬底延伸至该第一晶体管的该源/漏区中。隔离层接触该第一晶体管的该源/漏区，且第二晶体管的源/漏区也接触该隔离层。因此，该隔离层位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间。该第一晶体管的沟道区接触并延伸于该第一晶体管的该源/漏区之间，且该第二晶体管的沟道区接触并延伸于该第二晶体管的该源/漏区之间。栅极导体围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面。

Description

互补场效应晶体管中的外延结构
技术领域
本发明涉及集成电路结构，尤其涉及三维单片互补场效应晶体管(complementaryfield effect transistor；CFET)中的外延结构。
背景技术
集成电路装置使用晶体管执行许多不同的功能，且这些晶体管可采取许多不同的形式，从平面晶体管到使用“鳍片”模式结构的晶体管。鳍式晶体管的鳍片是自衬底延伸的薄而长的六面矩形，具有长度大于宽度的侧面、长度与该侧面相同的顶部及底部(但具有较窄的宽度)，以及自衬底的高度与该侧面的宽度相同但仅与该顶部及底部一样宽的端部。
在一个例子中，多个水平的环绕栅极场效应晶体管(horizontal gate-all-around field effect transistor；h-GAAFET)通常会具有位于一侧上的一行N型GAAFET，位于相对侧上的相应一行P型GAAFET，以及横贯并包覆并排对N型与P型GAAFET的沟道区的共用栅极。相反，具有多个垂直堆叠对GAAFET的互补FET(CFET)布局会具有位于一个层级上的P型GAAFET，位于相邻层级上(也就是，在上方或下方)的N型GAAFET，以及共用栅极，其中，各共用栅极垂直贯穿并包覆堆叠对N型与P型GAAFET的沟道区。在此类结构中，下方GAAFET的源/漏区通过介电层与上方GAAFET的源/漏区电性隔离。
发明内容
依据本文中的结构实施例，隔离元件(其可为衬底中的隔离塞或埋置氧化物部分)可延伸至衬底的表面中。第一晶体管的源/漏区接触该隔离元件，且该隔离元件自该衬底延伸至该第一晶体管的该源/漏区中。隔离层接触该第一晶体管的该源/漏区。第二晶体管的源/漏区也接触该隔离层。因此，该第一晶体管位于该第二晶体管与该衬底之间，且该隔离层位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间。
另外，该第一晶体管的沟道区接触并延伸于该第一晶体管的该源/漏区之间。类似地，该第二晶体管的沟道区接触并延伸于该第二晶体管的该源/漏区之间。该第一晶体管的该沟道区与该第二晶体管的该沟道区平行于该衬底的该表面而延伸。
此外，栅极导体围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面。衬里介电质横向邻近该栅极导体。该衬里介电质不同于该隔离层及该隔离元件。
本文中的方法实施例在衬底上形成多层结构以包括由间隙壁层隔开的半导体层，以及图案化该多层结构以形成凹槽，该凹槽穿过该多层结构伸至该衬底中，从而定义鳍片。此类方法形成延伸至该鳍片之间的该衬底的表面中的隔离元件，以及在该凹槽中形成第一晶体管的源/漏区，以接触该隔离元件。该隔离元件经形成以自该衬底延伸至该第一晶体管的该源/漏区中。该隔离元件可被形成为位于该衬底中的绝缘体塞或埋置氧化物区。
另外，此类方法在该鳍片之间的该凹槽中形成隔离层以接触该第一晶体管的该源/漏区，以及在该凹槽中形成第二晶体管的源/漏区以接触该隔离层。该第一晶体管经形成以位于该第二晶体管与该衬底之间。
该隔离层可经形成以位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间。该隔离层可经形成以具有小于或等于该第一晶体管的该源/漏区的宽度的宽度(其中，沿平行于该衬底的该表面的方向测量该宽度)。另外，该第一晶体管的该源/漏区可经形成以接触与该衬底连接的埋置氧化物层。此外，该隔离层的高度(其垂直于上述宽度)经形成以小于该源/漏区的高度。
该半导体层的其中一个是接触并延伸于该第一晶体管的该源/漏区之间的该第一晶体管的沟道区，而该半导体层的另一个是接触并延伸于该第二晶体管的该源/漏区之间的该第二晶体管的沟道区。
这些方法还形成横向邻近该鳍片的衬里介电质。该衬里介电质不同于该隔离层及该隔离元件。该衬里介电质可经形成以位于该隔离元件与该衬底之间。另外，这些方法用围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面的栅极导体替代该间隙壁层的部分。
附图说明
通过参照附图自下面的详细说明将更能理解本文中的实施例，该些附图并不一定按比例绘制，且其中：
图1至6显示依据本文中的实施例的各种结构的示意图；
图7至23显示可用以制作图1中所示的结构的各种示例制程步骤的示意图；
图24至31显示可用以制作图2中所示的结构的各种示例制程步骤的示意图；
图32至36显示可用以制作图3中所示的结构的各种示例制程步骤的示意图；
图37至50显示可用以制作图4中所示的结构的各种示例制程步骤的示意图；
图51至62显示可用以制作图5中所示的结构的各种示例制程步骤的示意图；以及
图63至72显示可用以制作图6中所示的结构的各种示例制程步骤的示意图。
具体实施方式
如上所述，各种类型的互补晶体管结构使用相反极性的晶体管(例如，n型场效应晶体管(nFET)及p型场效应晶体管(pFET))。此类nFET及pFET具有外延生长的导电掺杂源/漏(S/D)区，且此类外延源/漏区被独立生长于它们接触半导体沟道区之处(例如，在纳米片堆叠中)。该nFET及pFET外延源/漏区可被垂直集成于互补场效应晶体管(CFET)中；不过，为避免短路，该nFET及pFET外延源/漏区应当彼此电性绝缘。
当在块体衬底上利用纳米片状架构形成晶体管(例如，CFET)时，通常自(i)硅纳米片的侧面以及(ii)底部硅衬底生长外延源/漏区。这可能导致穿过衬底的寄生源/漏泄漏，从而损害装置性能。外延源/漏区(以及位于纳米片堆叠下方的区域)与衬底的介电隔离有利于优化电性性能。鉴于此，本文中所述的装置及制程在nFET外延制程期间结合衬里使用pFET选择性保护。另外，一些实施例可利用氧化物塞形成底部隔离，或者形成外延间隙壁进行外延源/漏断开。本文中的其它实施例利用pFET伪栅极(例如，外延硼掺杂硅锗(SiGe:B))的选择性氧化在nFET与pFET外延源/漏区之间形成自对准外延间隙壁来提供源/漏区的电性隔离，从而解决这些问题。
现在请参照附图，图1至6显示依据本文中的实施例的各种结构的示意图。图1显示本文中的一个示例结构，且图7至23(下面讨论)显示可用以制作图1中所示的结构的各种示例制程步骤。
更具体地说，图1显示硅衬底102以及延伸至衬底102的表面中的隔离元件(在此情况下是由隔离绝缘体104制成的隔离塞103)。在一些例子中，该绝缘体可为氧化物，例如氧化硅。该隔离元件自衬底102延伸至nFET源/漏区146，且这使隔离塞103能够提供nFET源/漏区146与衬底102的额外电性隔离(且这有助于防止穿过衬底102的相邻鳍片的横向相邻源/漏区之间的电流流动)。
第一晶体管(例如，nFET 166)的源/漏区146接触隔离塞103，且隔离塞103自衬底102延伸至第一晶体管166的源/漏区146。隔离层144接触第一晶体管166的源/漏区146。另外，第二晶体管(例如，pFET 162)的源/漏区142接触隔离层144。因此，第一晶体管166位于第二晶体管162与衬底102之间，且隔离层144位于第一晶体管166的源/漏区146与第二晶体管162的源/漏区142之间。
如下面更详细所述，隔离层144可为高质量绝缘体(例如SiO2、SiBCN、SiOC、SiOCN等)的共形沉积，且隔离层144与nFET源/漏区146及pFET源/漏区142自对准，以一致形成于nFET源/漏区146与pFET源/漏区142之间，并一致地在nFET源/漏区146与pFET源/漏区142之间提供高质量电性绝缘体。
另外，第一晶体管166的沟道区114接触并延伸于第一晶体管166的源/漏区146之间。类似地，第二晶体管162的沟道区114接触并延伸于第二晶体管162的源/漏区142之间。第一晶体管166的沟道区114及第二晶体管162的沟道区118平行于衬底102的顶部表面(隔离塞103延伸至其中)延伸。换句话说，衬底102的顶部表面是最接近晶体管162、166的表面。
在图1中，潜在单个、连续的栅极导体150围绕两个晶体管162、166的长条形沟道区114的侧面。堆叠GAAFET的栅极结构可包括单个栅极导体，或者邻近下方沟道的第一功函数金属层(例如，针对NFET性能最优)、邻近上方沟道的第二功函数金属层(例如，针对PFET性能最优)，以及视需要地，某种填充金属，且这些可被称为共用栅极结构。栅极绝缘体152将栅极导体150与沟道区114电性绝缘。
另外，衬里介电质110将相邻鳍片的组件彼此电性隔离(例如，将栅极导体150与其它鳍片中的横向相邻的栅极导体150绝缘)。栅极(侧壁)间隙壁136横向邻近栅极导体150的上部(上侧壁)，且各种接触154延伸穿过衬里介电质110以接触各种源/漏区(不是所有接触都显示于所提供的视图中)。此外，栅极覆盖层132可位于栅极导体150的顶部(该“顶部”是位于衬底102远侧的栅极导体150的部分)。衬里介电层110不同于(例如，不同材料、不同形成、不同结构等)隔离层144及该隔离元件(在此例中，该隔离元件为隔离塞103)。
图2显示本文中的替代结构，其类似图1(因此，使用相同的识别标记来识别类似的特征，而没有多余的说明，以保持读者关注)；不过，在图2中，该隔离元件是埋置氧化物层(buried oxide layer；BOX)或相对于衬底的其余部分具有较低导电性(较大电性绝缘(较高K))的其它类似介电衬底元件160。此外，此隔离元件(BOX 160)用以提供nFET源/漏区146与衬底102的额外电性隔离，以防止在相邻鳍片之间的穿过衬底102的不想要的电流流动。在图2中所示的结构中，隔离层144额外位于BOX 160与第一晶体管166的源/漏区146之间，以进一步绝缘源/漏区146与衬底102。图24至31(下面说明)是显示可用以制作图2中所示的结构的各种示例制程步骤的示意图。
图3也显示本文中的一种替代结构，其类似先前所述的附图(因此，使用相同的识别标记来识别类似的特征，同样没有多余的说明)；不过，在图3中，隔离层144与源/漏区142、146的宽度相同。要注意的是，在图1中所示的结构中，与源/漏区142、146相比，隔离层144具有较小的宽度。在此例中，“宽度”沿平行于衬底102的顶部表面以及平行于沟道区114的方向测量。图32至36(下面说明)是显示可用以制作图3中所示的结构的各种示例制程步骤的示意图。
图4另外显示本文中的一种替代结构，其类似先前所述的附图(且同样，使用相同的识别标记来识别类似的特征，而没有多余的说明)；不过，在图4中，衬里介电质110位于隔离元件(在此例中为隔离塞103)与衬底102之间，以进一步绝缘源/漏区146与衬底102。另外，图4包括较窄(不太宽)的隔离层144。图37至50(下面说明)是显示可用以制作图4中所示的结构的各种示例制程步骤的示意图。
图5额外显示本文中的一种替代结构，其类似先前所述的附图(同样，使用相同的识别标记来识别类似的特征)；不过，在图5中，第一晶体管166的源/漏区146接触埋置氧化物层160。相对于本文中所讨论的其它结构中的源/漏区146的高度，这增加源/漏区146的高度，其中，晶体管162、166的源/漏区142、146的高度是相同的(且其中，该“高度”方向垂直于先前所述的“宽度”方向(例如，垂直于衬底102的顶部))。在本文中所示的结构中，隔离层144的高度小于源/漏区142、146的高度。另外，在图5中所示的结构中，沟道区114之间的间距大于第一晶体管166的沟道区114与衬底102之间的间距。栅极导体150包括横向邻近隔离层144将源/漏区142、146彼此电性隔离之处的延伸区156。此类延伸区156是来自用以增加沟道间距的纳米片堆叠中的层(116，下面说明)的制品。图51至62(下面说明)是显示可用以制作图5中所示的结构的各种示例制程步骤的示意图。
图6也显示本文中的一种替代结构，其类似图5中所示的结构(且同样，使用相同的识别标记来识别类似的特征，而没有多余的说明)；不过，在图6中，交换第一晶体管166与第二晶体管162的位置，以使第二晶体管162位于第一晶体管166与衬底102之间。图63至72(下面说明)是显示可用以制作图6中所示的结构的各种示例制程步骤的示意图。
如上所述，图7至23显示可用以制作图1中所示的结构的各种示例制程步骤。如图7中所示，该制程利用多个外延生长制程在衬底102上形成多层结构112、114，以包括被间隙壁层112(可为SiGe等)隔开的半导体层114(例如，半导体掺杂硅)，例如，形成纳米片堆叠。
如图8中所示，这些方法形成绝缘体层120(例如，氧化物)并形成额外层(例如，非晶硅122、氧化物130、SiN 132、SiO 134)，其被图案化成鳍片。在图8中，此类制程在该鳍片上方沉积共形保护层136(例如，SiBCN)。在图9中，此类制程利用例如反应离子蚀刻(reactive ion etching；RIE)图案化该多层结构，以形成穿过该多层结构延伸至衬底102中的凹槽。此制程将保护层136重新成形为侧间隙壁136。在图10中，为减小间隙壁层112的宽度，利用选择性移除该间隙壁层材料(例如，SiGe等)而基本不影响其它暴露材料的制程，以相对于其它材料凹入间隙壁层112。
在图11中，利用例如SiN的共形沉积等在该鳍片上方形成衬里介电质110(利用制程例如氧化物的原位自由基辅助沉积(in-situ radical assisted deposition；iRAD)形成例如层等)。在图12中，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中使衬里介电质110自对准共形保护层136的形状。接着，如图13中所示，此制程通过例如在例如可流动化学气相沉积(flowable chemical vapor deposition；FCVD)、非等向性高密度等离子体(anisotropic high density plasma；HDP)制程等制程中沉积厚的共形氧化物衬里(例如，SiO等)在该结构上方形成隔离绝缘体104。要注意的是，此步骤可导致与图示不同的几何，或者可能不会完全填充该栅极之间。在图14中，利用制程例如氧化物非等向性凹入(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)、完全等向性蚀刻或其组合向下凹入隔离绝缘体104至高于下方半导体层114(在此例中，其将最终成为nFET)的水平。
通过共形形成额外量的衬里介电质110包覆上方半导体层118(在此例中，其将最终成为pFET)，如图15中所示。同样，如参照图11所述，衬里介电质110可通过氧化物的iRAD形成(例如，形成例如4纳米层等)。随后，如图16中所示，蚀刻衬里介电质110，以将其自隔离绝缘体104的顶部移除(例如，在非等向回蚀刻中，例如伴随选择性凹入的反应离子蚀刻(RIE)Ge注入等)。在图17中，由于隔离绝缘体104暴露，执行材料移除制程(例如，氧化物等向性凹入(oxide isotropic recess；BHS))，以向下移除隔离绝缘体104至下方半导体层114与衬底102之间的水平，从而暴露下方半导体层114的侧面。要注意的是，在此阶段，上方半导体层118仍被衬里介电质110保护，如图17中所示。由于下方半导体层114的侧面暴露，且上方半导体层118仍被保护，如图18中所示，所以在下方半导体层114的暴露表面上外延生长该下方晶体管的源/漏区146，以包括nFET源/漏型掺杂物(例如，Si:P)。
如图19中所示，利用制程例如SiO2、SiBCN、SiOC、SiOCN等的共形沉积在该结构上方形成隔离层材料144。要注意的是，可使用多个层，该些层可不同。这里，该间隙壁形成提供下方晶体管源/漏极146的包覆，并防止在下方晶体管源/漏极146上发生后续的上方源/漏极142成核。要注意的是，在一些实施例中，如图19中所示，在区域148中，通过在顶部过填充以最大限度地降低接缝，且隔离层材料144在该鳍片之间足够厚，以促进在后续所形成的栅极之间的夹止。利用例如等向性或非等向性凹入等的制程减小隔离层材料144的高度，如图20中所示。接着，如图21中所示，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露上方半导体层118。
由于上方半导体层118的侧面暴露，且下方半导体层114仍被保护，如图22中所示，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。图23显示与图22中所示相同的结构；不过，在图23中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。此外，图23显示延伸至衬底102中并形成隔离塞103的隔离绝缘体104的部分。接着，额外处理图22及23中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图1中所示的结构。
如上所述，图24至31显示可用以制作图2中所示的结构的各种示例制程步骤的示意图。要注意的是，图2及24至31中所示的结构不使用隔离塞103；相反，在此实施例中，该衬底包括(或是附着至)埋置绝缘体层160(其可为仅相对于衬底102提供较大电性绝缘的任意类型介电质，且出于方便，在本文中被简单地称为埋置氧化物层(BOX))。因此，在图2及24至31中所示的例子中，该隔离元件为BOX 160，而不是隔离塞103。
图24显示在已完成与图7至16中所示的制程类似的制程以后的结构(不过，包括BOX 160而不是隔离塞103)，并避免关于此类制程的多余的讨论/说明，以保持关注此实施例的突出态样。在图25中，利用例如氧化物非等向性凹入的制程(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)向下完全凹入隔离绝缘体104至BOX 160。这里，可完全移除隔离绝缘体104，因为底部BOX 160已提供与衬底102的隔离。要注意的是，这里，上方半导体层118仍被衬里介电质110保护，如图25中所示。由于下方半导体层114的侧面暴露，且上方半导体层118仍被保护，如图26中所示，在下方半导体层114的暴露表面上外延生长该下方晶体管的源/漏区146，以包括nFET源/漏型掺杂物(例如，Si:P)。
接着，在图27中，利用制程例如SiO2、SiBCN、SiOC、SiOCN等的共形沉积在该结构上方形成隔离层材料144。这里，该共形沉积提供下方晶体管源/漏极146的包覆，并防止在下方晶体管源/漏极146上发生后续的上方源/漏极142成核。要注意的是，如图27中所示，在区域148中，通过在顶部过填充以最大限度地降低接缝，且隔离层材料144在该鳍片之间足够厚，以促进在后续所形成的栅极之间的夹止。利用例如非等向性凹入等的制程减小隔离层材料144的高度，如图28中所示。接着，如图29中所示，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露上方半导体层118。
由于上方半导体层118的侧面暴露，且下方半导体层114仍被保护，如图30中所示，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。图31显示与图30中所示相同的结构；不过，在图31中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。接着，额外处理图30及31中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图2中所示的结构。
如上所述，图32至36显示可用以制作图3中所示的结构的各种示例制程步骤的示意图。要注意的是，图3及32至36中所示的结构再次使用隔离塞103而不是埋置绝缘体层160。因此，在图3及32至36中所示的例子中，隔离元件是隔离塞103，而不是BOX 160。
图32显示在已完成与图7至18中所示的制程类似的制程以后的结构，除了已回蚀刻在间隙壁136对准之外的衬里110的部分以外，其中，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，此外，避免关于此类项目的多余的讨论/说明，以保持读者关注。接着，在图33中，利用制程例如SiO2、SiBCN、SiOC、SiOCN等的共形沉积在该结构上方形成隔离层材料144。这里，该共形沉积提供下方晶体管源/漏极146的包覆，并防止在下方晶体管源/漏极146上发生后续的上方源/漏极142成核。要注意的是，如图33中所示，在区域148中，通过在顶部过填充以最大限度地降低接缝，且隔离层材料144在该鳍片之间足够厚，以促进在后续所形成的栅极之间的夹止。利用例如非等向性凹入等的制程减小隔离层材料144的高度，如图34中所示，以暴露上方半导体层118的侧面。由于上方半导体层118的侧面暴露，且下方半导体层114仍被保护，如图35中所示，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。
图36显示与图35中所示相同的结构；不过，在图36中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。此外，图36显示延伸至衬底102中并形成隔离塞103的隔离绝缘体104的部分。接着，额外处理图35及36中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图3中所示的结构。
如上所述，图37至50显示可用以制作图4中所示的结构的各种示例制程步骤的示意图。要注意的是，图3及37至50中所示的结构再次使用隔离塞103而不是埋置绝缘体层160。因此，在图3及37至50中所示的例子中，该隔离元件为隔离塞103，而不是BOX 160。
图37显示在已完成与图7至13中所示的制程类似的制程以后的结构，除了未执行图12中所示的衬里介电质110移除制程以外，并避免关于此类制程的多余的讨论/说明，以保持关注此实施例的突出态样。这使图37中所示的结构具有在该鳍片上及在隔离绝缘体104与衬底102之间保留于原位的衬里介电质110。这使隔离塞103经形成以包括接触该衬底的衬里介电质110，且在此处，衬里介电质110位于后续所形成的间隙壁材料144与衬底102之间。
图38显示利用例如氧化物非等向性凹入的制程(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)向下凹入隔离绝缘体104至低于下方半导体层114的水平(至下方半导体114与衬底102之间的水平)。在图39中，在向下至被凹入的隔离绝缘体104的顶部的材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状。接着，如图40中所示，此制程通过例如在例如可流动化学气相沉积(FCVD)、非等向性高密度等离子体(HDP)制程等制程中沉积厚的共形氧化物衬里(例如，SiO等)以在该结构上方重新形成隔离绝缘体104。
在图41中，利用例如氧化物非等向凹入的制程(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)向下凹入隔离绝缘体104至高于下方半导体层114的水平(至下方半导体层114与上方半导体层118之间的水平)。接着，通过共形形成额外量的衬里介电质110包覆该鳍片，如图42中所示。同样，如关于图11所述，可利用氧化物的iRAD形成衬里介电质110。随后，如图43中所示，蚀刻衬里介电质110，以将其自隔离绝缘体104的顶部移除(例如，在非等向性回蚀刻中，例如伴随选择性凹入的反应离子蚀刻(RIE)Ge注入等)。
在图44中，利用例如氧化物非等向性凹入的制程(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)完全凹入隔离绝缘体104。要注意的是，这里，上方半导体层118仍被衬里介电质110保护，如图44中所示。由于下方半导体层114的侧面暴露，且上方半导体层118仍被保护，如图45中所示，在下方半导体层114的暴露表面上外延生长该下方晶体管的源/漏区146，以包括nFET源/漏型掺杂物(例如，Si:P)。
如图46中所示，利用例如SiO2、SiBCN、SiOC、SiOCN等的共形沉积制程在该结构上方形成隔离层材料144。要注意的是，如图46中所示，在区域148中，通过在顶部过填充以最大限度地降低接缝，且隔离层材料144在该鳍片之间足够厚，以促进在该栅极之间的夹止。利用例如非等向性凹入等的制程减小隔离层材料144的高度至下方半导体层114与上方半导体层118之间的水平，如图47中所示。接着，如图48中所示，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露上方半导体层118。由于上方半导体层118的侧面暴露，且下方半导体层114仍被保护，如图49中所示，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。
图50显示与图49中所示相同的结构；不过，在图50中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。此外，图50显示由延伸至衬底102中并形成隔离塞103的衬里介电质110加衬的间隙壁材料144的部分。接着，额外处理图49及50中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图4中所示的结构。
如上所述，图51至62显示可用以制作图5中所示的结构的各种示例制程步骤的示意图。要注意的是，图5及51至62中所示的结构不使用隔离塞103；相反，在此实施例中，该衬底包括(或是附着至)埋置绝缘体层160(其可为任意类型介电质，且出于方便，在本文中被简单称为埋置氧化物层(BOX))。因此，在图5及51至62中所示的例子中，该隔离元件为BOX160，而不是隔离塞103。另外，图5及51至62中所示的结构形成纳米片堆叠，以包括额外硅层116，此额外硅层116是不连续的且薄于下方及上方半导体层114、118。另外，由于下方与上方半导体层114、118之间的双间隙壁层112，因此相对于BOX层160与下方半导体层114之间的间距，此纳米片堆叠在下方与上方半导体层114、118之间提供更多的空间。因此，图51显示在已完成与图7至9中所示的制程类似的制程及相关鳍片形成以后的结构(不过，包括BOX160，及该不同的纳米片堆叠)，并避免关于此类制程的多余的讨论/说明，以保持关注此实施例的突出态样。
在图52中，为减小间隙壁层112的宽度，利用选择性移除该间隙壁层材料(例如，SiGe等)而基本不影响其它暴露材料的制程，以相对于其它材料凹入间隙壁层112。在图53中，利用例如SiN的共形沉积等在该鳍片上方形成衬里介电质110(利用例如氧化物的原位自由基辅助沉积(iRAD)的制程，以形成60A层等)。接着，如图54中所示，此制程通过例如在例如可流动化学气相沉积(FCVD)、非等向性高密度等离子体(HDP)制程等制程中沉积厚的共形氧化物衬里(例如，SiO等)以在该结构上方形成隔离绝缘体104；以及利用例如氧化物非等向性凹入(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)的制程向下凹入隔离绝缘体104至高于下方半导体层114的水平。
在图55中，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露上方半导体层118的侧面。由于上方半导体层118的侧面暴露，且下方半导体层114仍被保护，如图56中所示，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。在图57中，利用例如氧化物等向性凹入的制程向下完全凹入隔离绝缘体104至BOX 160，使该上方晶体管的源/漏区142的部分暴露。
接着，在图58中，在通过在高压及低温下进行选择性氧化以提供例如该pFETSiGe:B的SiO2包覆的制程中，氧化该上方晶体管的源/漏区142的暴露部分，以形成隔离层氧化物140。图58中所示的制程消耗该上方晶体管的源/漏区142的部分，并因此减小该上方晶体管的源/漏区142的高度。
如图59中所示，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露下方半导体层114。此外，如图60中所示，在预清洗制程中部分凹入隔离层氧化物140的尺寸。接着，在图61中，在下方半导体层114的暴露表面上外延生长该下方晶体管的源/漏区146，以包括nFET源/漏型掺杂物(例如，Si:P)。要注意的是，在图61中所示的制程中，该下方晶体管的源/漏区146可经形成以接触BOX层160；不过，这不会导致穿过衬底102的不想要的电流流动，因为BOX层160提供足够的绝缘来防止这样的状况发生。
图62显示与图61中所示相同的结构；不过，在图62中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。接着，额外处理图61及62中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、116、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图5中所示的结构。要注意的是，在图5中，栅极延伸区156是通过用栅极导体材料150替代间隙壁层116所形成的制品。
如上所述，图63至72显示可用以制作图6中所示的结构的各种示例制程步骤的示意图。要注意的是，图6及63至72中所示的结构不使用隔离塞103；相反，在此实施例中，该衬底包括(或是附着至)埋置绝缘体层160(其可为任意类型介电质，且出于方便，在本文中被简单称为埋置氧化物层(BOX))。因此，在图6及63至72中所示的例子中，该隔离元件为BOX160，而不是隔离塞103。另外，图6及63至72中所示的结构形成纳米片堆叠，以包括额外硅层116，此额外硅层116是不连续的且薄于下方及上方半导体层114、118。此外，由于下方与上方半导体层114、118之间的双间隙壁层112，因此相对于BOX层160与下方半导体层114之间的间距，此纳米片堆叠在下方与上方半导体层114、118之间提供更多的空间(双间隙壁层112由较薄且不连接的额外硅层116隔开及结构支持)。
因此，图63显示在与图7至9及51至53中所示的制程类似的制程以后的结构，其中，利用上述制程，已完成相关鳍片形成(不过，包括BOX 160，以及该不同的纳米片堆叠)，并使衬里介电质110自对准共形保护层136的形状，且形成隔离绝缘体104并向下凹入至高于中间半导体层116的水平。此外，避免关于此类制程的多余的讨论/说明，以保持关注此实施例的突出态样。
在图64中，通过共形形成的额外量的衬里介电质110包覆上方半导体层118。随后，如图65中所示，蚀刻衬里介电质110，以将其自隔离绝缘体104的顶部移除。在图66中，利用例如氧化物非等向性凹入的制程(例如，混合湿式(BHF)/干式脉冲蚀刻-沉积(C4F6+O2/CO/Ar)等)向下完全凹入隔离绝缘体104至BOX 160，以暴露下方半导体层114。由于下方半导体层114暴露，且上方半导体层118仍被保护，如图67中所示，在下方半导体层114的暴露表面上外延生长该下方晶体管的源/漏区142，以包括pFET源/漏型掺杂物(例如，SiGe:B)。要注意的是，在图67中所示的制程中，该下方晶体管的源/漏区142可经形成以接触BOX层160；不过，这不会导致穿过衬底102的不想要的电流流动，因为BOX层160提供足够的绝缘以防止这样的状况发生。
在图68中，在通过在高压及低温下进行选择性氧化以提供例如该pFET SiGe:B的SiO2包覆的制程中，氧化该下方晶体管的源/漏区142的暴露部分，以形成隔离层氧化物140。图68中所示的制程消耗该下方晶体管的源/漏区142的部分，从而减小该下方晶体管的源/漏区142的高度。
如图69中所示，在材料移除制程(例如，在165℃的H3PO4的回蚀刻制程等)中，使衬里介电质110自对准共形保护层136的形状，以暴露上方半导体层118。此外，如图70中所示，在预清洗制程中部分凹入隔离层氧化物140的尺寸。接着，在图71中，在上方半导体层118的暴露表面上外延生长该上方晶体管的源/漏区146，以包括nFET源/漏型掺杂物(例如，Si:P)。
图72显示与图71中所示相同的结构；不过，在图72中，向附图添加示例材料识别，以显示可用于该结构的不同组件的一些化学组分的一个例子(且本领域的普通技术人员将理解，此例中所示的材料可由其它材料替代，而不背离后面所提出的权利要求所识别的结构)。接着，额外处理图71及72中所示的结构，以移除位于半导体层114、118之上及周围的材料(上述材料112、116、120、122、130、132、134)，并用栅极导体150(上述)及各种栅极绝缘体152(例如，氧化物)以及其它导电接触154替代此类组件，从而导致图6中所示的结构。要注意的是，在图6中，栅极延伸区156是通过用栅极导体材料150替代间隙壁层116所形成的制品。
出于本文中的目的，“半导体”是一种材料或结构，其可包括注入或原位(例如，外延生长)的杂质，以基于电子及空穴载流子浓度使该材料有时是导体以及有时是绝缘体。本文中所使用的“注入制程”可采取任意合适的形式(无论现在已知还是未来开发的)且可为例如离子注入等。外延生长发生于加热(有时加压)环境中，该环境富含将要被生长的材料的气体。
出于本文中的目的，“绝缘体”是相对术语，其是指与“导体”相比允许很小的电流流动(<95％)的材料或结构。本文中所提到的介电质(绝缘体)可例如自干燥的氧环境或蒸汽生长并接着被图案化。或者，本文中的介电质可自任意多种候选高介电常数(高k)材料形成，包括但不限于氮化硅、氮氧化硅、SiO2与Si3N4的栅极介电堆叠，以及金属氧化物如氧化钽。本文中的介电质的厚度可依据所需装置性能而变化。
本文中所述的导体可由任意导电材料形成，例如多晶硅、非晶硅、非晶硅与多晶硅的组合，以及多晶硅-锗，通过存在合适的掺杂物而赋予导电性。或者，本文中的导体可为一种或多种金属，例如钨、铪、钽、钼、钛，或镍，或金属硅化物，此类金属的任意合金，且可通过物理气相沉积、化学气相沉积，或现有技术中已知的任意其它技术来沉积。
存在各种类型的晶体管，其在如何被用于电路方面稍有差别。例如，双极型晶体管具有被标记为基极、集电极及发射极的端子。在基极端子的小电流(也就是，在基极与发射极之间流动)可控制或切换集电极与发射极端子之间的较大电流。另一个例子是场效应晶体管，其具有被标记为栅极、源极及漏极的端子。栅极的电压可控制源极与漏极之间的电流。在此类晶体管内，半导体(沟道区)位于导电源区与类似导电的漏极(或导电源极/发射极区)之间，且当该半导体处于导电状态时，该半导体允许电流在源极与漏极之间或集电极与发射极之间流动。栅极为导电元件，通过“栅极氧化物”(其为绝缘体)与该半导体电性隔开；且栅极内的电流/电压变化使沟道区导电，以允许电流在源极与漏极之间流动。类似地，在基极与发射极之间流动的电流使半导体导电，以允许电流在集电极与发射极之间流动。
正型晶体管“P型晶体管”在本征半导体衬底内使用杂质例如硼、铝或镓等(以形成价电子不足)作为半导体区。类似地，“N型晶体管”是负型晶体管，其在本征半导体衬底内使用杂质例如锑、砷或磷等(以形成过剩的价电子)作为半导体区。
本文中的“衬底”可为适于给定目标的任意材料(无论现在已知还是未来开发的)，且可为例如硅基晶圆(块体材料)、陶瓷材料、有机材料、氧化物材料、氮化物材料等，无论是已掺杂还是未掺杂。当图案化本文中的任意材料时，将要被图案化的该材料可以任意已知的方式生长或沉积，并可在该材料上方形成图案化层(例如有机光阻)。可将该图案化层(阻剂)暴露于以光曝光模式设置的某些光辐射图案(例如，图案化曝光、激光曝光等)，并接着，利用化学剂显影该阻剂。此制程改变被曝光的该阻剂的部分的物理特性。接着，可洗掉该阻剂的一部分，保留该阻剂的其它部分以保护将要被图案化的材料(洗掉该阻剂的哪部分依赖于该阻剂是负型阻剂(保留受照部分)还是正型阻剂(洗掉受照部分))。接着，执行材料移除制程(例如、湿式蚀刻、非等向性蚀刻(取向依赖性蚀刻)、等离子体蚀刻(反应离子蚀刻(RIE)等))，以移除将要被图案化的位于该阻剂下方的该材料的未受保护的部分。随后移除该阻剂，以保留依据该光曝光图案(或其负型图像)图案化的该下方材料。
出于本文中的目的，“侧间隙壁”是本领域的普通技术人员已知的结构，且为形成侧间隙壁，通常沉积或生长共形绝缘层(例如任意上述绝缘体)，并接着执行定向蚀刻制程(非等向性)，以与自垂直表面移除材料的速率相比较大的速率自水平表面蚀刻材料，从而保留沿结构的垂直侧壁的绝缘材料。保留于垂直侧壁上的此材料被称为侧间隙壁。
尽管附图中仅显示一个或有限数目的晶体管，但本领域的普通技术人员将理解，可用本文中的实施例同时形成许多不同类型的晶体管，且附图意图显示同时形成多个不同类型的晶体管；不过，出于清晰目的，可简化附图以仅显示有限数目的晶体管，并使读者更容易地意识到所示的不同特征。这并非意图限制此揭示，因为如本领域的普通技术人员所理解的那样，此揭示适用于附图中所显示的包括许多各类型晶体管的结构。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制上述实施例。除非上下文中另外明确指出，否则本文中所使用的单数形式“一个”以及“该”也意图包括复数形式。而且，本文中所使用的术语“右”、“左”、“垂直”、“水平”、“顶部”、“底部”、“上方”、“下方”、“平行”、“垂直”等意图说明当它们以附图中取向并显示时的相对位置(除非另外指出)，且术语如“接触”、“直接接触”、“毗邻”、“直接相邻”、“紧邻”等意图表示至少一个元件物理接触另一个元件(没有其它元件隔开所述元件)。本文中所使用的术语“横向”说明当元件以附图中取向并显示时该些元件的相对位置，尤其表示一个元件位于另一个元件的侧边而不是另一个元件的上方或下方。例如，一个元件横向邻近另一个元件将在该另一个元件旁边，一个元件横向紧邻另一个元件将直接在该另一个元件旁边，以及一个元件横向围绕另一个元件将邻近并环绕该另一个元件的外侧壁。
本文中的实施例可用于各种电子应用，包括但不限于高级传感器、存储器/数据储存、半导体、微处理器以及其它应用。制造者可以原始晶圆形式(也就是，作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得装置及结构，例如集成电路(IC)芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为(a)中间产品例如母板的部分，或者作为(b)最终产品的部分。该最终产品可为包括集成电路芯片的任意产品，涉及范围从玩具及其它低端应用直至具有显示器、键盘或其它输入装置以及中央处理器的先进计算机产品。
尽管上面仅结合有限数目的实施例来详细说明，但很容易理解，本文中的实施例不限于这些揭示。相反，可修改本文中的元件以包含此前未说明但符合本文的精神及范围的任意数目的变化、更改、替代或等同布置。此外，尽管已说明各种实施例，但应当理解，本文中的态样可仅被某些所述实施例包括。相应地，下面的权利要求将不被视为被上述说明限制。除非特别说明，否则提及单数元件并不意图意味着“一个且仅一个”，而是“一个或多个”。本发明中所述的各种实施例的元件的所有结构及功能等同(其为本领域的普通技术人员已知的或后来逐渐知道的)通过引用明确包含于此并意图被本发明包括。因此，应当理解，在所揭示的特定实施例中可作变更，其落入如所附权利要求所概述的上述范围内。

Claims (20)

1.一种集成电路结构，包括：
隔离元件，延伸至衬底中；
第一晶体管的源/漏区，接触该隔离元件，其中，该隔离元件自该衬底延伸至该第一晶体管的该源/漏区中；
隔离层，接触该第一晶体管的该源/漏区；
第二晶体管的源/漏区，接触该隔离层，其中，该第一晶体管位于该第二晶体管与该衬底之间，以及其中，该隔离层位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间；
该第一晶体管的沟道区，接触并延伸于该第一晶体管的该源/漏区之间；
该第二晶体管的沟道区，接触并延伸于该第二晶体管的该源/漏区之间；以及
栅极导体，围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面。
2.如权利要求1所述的集成电路结构，其中，该隔离元件包括位于该衬底中的绝缘体塞或埋置氧化物区。
3.如权利要求1所述的集成电路结构，其中，该隔离层具有沿平行于该衬底的表面的方向小于或等于该第一晶体管的该源/漏区的宽度的宽度。
4.如权利要求1所述的集成电路结构，还包括衬里介电质，位于该隔离元件与该衬底之间。
5.如权利要求1所述的集成电路结构，其中，该第一晶体管的该源/漏区接触与该衬底连接的埋置氧化物层。
6.如权利要求1所述的集成电路结构，其中，该第二晶体管的该源/漏区是在该第二晶体管的该沟道区的表面上的SiGe:B外延生长。
7.如权利要求1所述的集成电路结构，其中，该第一晶体管的该源/漏区及该第二晶体管的该源/漏区包括外延生长材料。
8.一种集成电路结构，包括：
衬底；
隔离元件，延伸至该衬底的表面中；
第一晶体管的源/漏区，接触该隔离元件，其中，该隔离元件自该衬底延伸至该第一晶体管的该源/漏区中；
隔离层，接触该第一晶体管的该源/漏区；
第二晶体管的源/漏区，接触该隔离层，其中，该第一晶体管位于该第二晶体管与该衬底之间，以及其中，该隔离层位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间；
该第一晶体管的沟道区，接触并延伸于该第一晶体管的该源/漏区之间；
该第二晶体管的沟道区，接触并延伸于该第二晶体管的该源/漏区之间，其中，该第一晶体管的该沟道区与该第二晶体管的该沟道区平行于该衬底的该表面而延伸；
栅极导体，围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面；以及
衬里介电质，电性横向邻近该栅极导体，
其中，该衬里介电质不同于该隔离层及该隔离元件。
9.如权利要求8所述的集成电路结构，其中，该隔离元件包括位于该衬底中的绝缘体塞或埋置氧化物区。
10.如权利要求8所述的集成电路结构，其中，该隔离层具有沿平行于该衬底的该表面的方向小于或等于该第一晶体管的该源/漏区的宽度的宽度。
11.如权利要求8所述的集成电路结构，其中，该衬里介电质位于该隔离元件与该衬底之间。
12.如权利要求8所述的集成电路结构，其中，该第一晶体管的该源/漏区接触与该衬底连接的埋置氧化物层。
13.如权利要求8所述的集成电路结构，其中，该第二晶体管的该源/漏区是在该第二晶体管的该沟道区的表面上的SiGe:B外延生长。
14.如权利要求8所述的集成电路结构，其中，该第一晶体管的该源/漏区及该第二晶体管的该源/漏区包括外延生长材料。
15.一种方法，包括：
在衬底上形成多层结构，以包括由间隙壁层隔开的半导体层；
图案化该多层结构，以形成穿过该多层结构延伸至该衬底中从而定义鳍片的凹槽；
形成延伸至该衬底的表面中的隔离元件；
在该凹槽中形成第一晶体管的源/漏区，以接触该隔离元件，其中，该隔离元件经形成以自该衬底延伸至该第一晶体管的该源/漏区中；
在该凹槽中形成隔离层，以接触该第一晶体管的该源/漏区；
在该凹槽中形成第二晶体管的源/漏区，以接触该隔离层，其中，该第一晶体管经形成以位于该第二晶体管与该衬底之间，其中，该隔离层经形成以位于该第一晶体管的该源/漏区与该第二晶体管的该源/漏区之间，其中，该半导体层的其中一个包括接触并延伸于该第一晶体管的该源/漏区之间的该第一晶体管的沟道区，其中，该半导体层的另一个包括接触并延伸于该第二晶体管的该源/漏区之间的该第二晶体管的沟道区；
形成横向邻近该鳍片的衬里介电质，其中，该衬里介电质不同于该隔离层及该隔离元件；以及
用围绕该第一晶体管的该沟道区及该第二晶体管的该沟道区的侧面的栅极导体替代该间隙壁层的部分。
16.如权利要求15所述的方法，其中，该隔离元件经形成以包括位于该衬底中的绝缘体塞或埋置氧化物区。
17.如权利要求15所述的方法，其中，所述形成该第二晶体管的该源/漏区包括在该第二晶体管的该沟道区的表面上外延生长SiGe:B。
18.如权利要求15所述的方法，其中，该衬里介电质经形成以位于该隔离元件与该衬底之间。
19.如权利要求15所述的方法，其中，该第一晶体管的该源/漏区经形成以接触与该衬底连接的埋置氧化物层。
20.如权利要求15所述的方法，其中，该隔离层的高度经形成以小于该源/漏区的高度。
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