TW202018953A - 在閘極與源極／汲極接觸之間具有絕緣層的ｆｉｎｆｅｔ - Google Patents

在閘極與源極／汲極接觸之間具有絕緣層的ｆｉｎｆｅｔ Download PDF

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TW202018953A
TW202018953A TW108131695A TW108131695A TW202018953A TW 202018953 A TW202018953 A TW 202018953A TW 108131695 A TW108131695 A TW 108131695A TW 108131695 A TW108131695 A TW 108131695A TW 202018953 A TW202018953 A TW 202018953A
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insulator
gate structure
source
gate
drain
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TW108131695A
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TWI749363B (zh
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輝 臧
拉爾特斯 柯洛米克斯
席史 馬尼 潘迪
燦柔 朴
謝瑞龍
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美商格芯（美國）集成電路科技有限公司
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Abstract

製程形成積體電路裝置，該積體電路裝置包括平行的鰭片，其中，沿第一方向圖案化該鰭片。平行閘極結構沿垂直於該第一方向的第二方向與該鰭片相交，其中，該閘極結構具有與該鰭片相鄰的下部以及在該鰭片的遠側的上部。源極/汲極結構位於該閘極結構之間的該鰭片上。源極/汲極接觸位於該源極/汲極結構上，且多個絕緣體層位於該閘極結構與該源極/汲極接觸之間。額外的上側間隙壁位於該閘極結構的該上部與該多個絕緣體層之間。

Description

在閘極與源極/汲極接觸之間具有絕緣層的FINFET
本申請關於積體電路器件(device)，以及用於製造此類器件的製程，尤其關於通過在閘極與源極/汲極接觸之間設置額外絕緣層來避免許多傳統製程步驟並顧及接觸未對準。
積體電路器件使用電晶體執行許多不同的功能，且這些電晶體可採取許多不同的形式，從平面電晶體到使用“鰭片”模式結構的電晶體(例如，鰭式場效(FinFET)電晶體)。鰭式電晶體的鰭片是自基板延伸或者具有作為基板的部分的底部表面的薄而長的六面形狀(某種程度上為矩形)；具有長度大於寬度的側面、具有與該側面在某種程度上相似的長度(但具有更窄的寬度)的頂部及底部，以及自基板的高度與該側面的寬度大致相同但僅與該頂部及/或底部大致一樣寬的端部。在此類鰭片結構中可能發生圓化及不平坦的成形(尤其在角落及頂部)，且此類結構常常具有圓化、漸窄的形狀；不過，此類結構高度地區別於平面器件(儘管兩種類型器件都非常有用)。
在一個例子中，傳統製程在相交閘極之間的鰭片上形成源極/汲極。常使用功函數金屬作為閘極的部分(portion)且此類功函數金屬可能需要被斜 切。關於FinFET中的功函數金屬的斜切是在功函數金屬層上沉積保護填充材料，凹入該保護填充材料，蝕刻掉延伸於該保護填充材料上方的任意暴露功函數金屬材料，以及後續移除該保護填充材料的製程；不過，此類多步驟製程是時間、材料及機器密集型的；且引入額外的缺陷形成機會。另外，除了功函數金屬以外，在閘極中使用其它金屬化(例如鎢)，且常常在額外製程中凹入此類材料，其同樣可為時間、材料及機器密集型的；並可引入缺陷。採用額外的步驟將接觸(contact)與閘極及其它FinFET元件對準(在執行自對準接觸(self-aligned contact；SAC)製程時包括這些額外步驟)；不過，同樣，此類SAC製程可為時間、材料及機器密集型的。
本文中的示例方法圖案化層，以形成自該層延伸的平行的鰭片，其中，沿第一方向圖案化該鰭片。這些方法還圖案化沿垂直於該第一方向的第二方向與該鰭片相交的平行的犧牲閘極，在該犧牲閘極的側壁上形成第一側壁絕緣體，在該犧牲閘極之間的該鰭片上磊晶生長源極/汲極結構，在該第一側壁絕緣體上形成第二側壁絕緣體，以及形成與該犧牲閘極之間的該第二側壁絕緣體接觸的下絕緣體層。在一些實施中，該第一側壁絕緣體與該第二側壁絕緣體可具有不同的介電常數。
此類方法降低該犧牲閘極及該第一側壁絕緣體的高度(從自該鰭片的第一高度降低至自該鰭片的降低的高度)，在製程中保留該下絕緣體層及該第二側壁絕緣體不變並在該第一高度。此外，這些方法用第一導體替代該犧牲閘極，以形成閘極結構的下部，在製程中形成閘極結構的該下部至該第一高度並覆 蓋該降低高度的第一側壁絕緣體。此外，這些方法移除該下絕緣體層的部分以及該第二側壁絕緣體的相應水平部分(例如，非等向性蝕刻)，而該閘極結構的該下部覆蓋該第一側壁絕緣體，在製程中暴露該源極/汲極結構的其中一者(但此類製程避免自該第一側壁絕緣體或該閘極結構的該下部移除該第二側壁絕緣體)。此類方法在該閘極結構的該下部之間的該源極/汲極結構的其中暴露一者上形成犧牲源極/汲極接觸結構(至該第一高度)。此外，這些方法降低該閘極結構的該下部的高度(降低至自該鰭片的第三高度，該第三高度小於該“降低的”高度)，以形成第一凹部。
這些方法還在該第一凹部中形成上側間隙壁(upper sidewall spacer)，在製程中使該上側間隙壁接觸該犧牲源極/汲極接觸結構的側壁、該閘極結構的該下部、該第一側壁絕緣體、以及該第二側壁絕緣體。該上側間隙壁部分地填充該第一凹部，且該上側間隙壁僅延伸該第一凹部的深度。該上側間隙壁可為與該第一側壁絕緣體及該第二側壁絕緣體不同的絕緣體材料。本文中的方法移除該犧牲源極/汲極接觸結構以留下第二凹部，並在該上側間隙壁之間的該第一凹部中及在該第二凹部中形成第二導體，以同時形成該閘極結構的上部及下源極/汲極接觸結構。
本文中的各種示例積體電路裝置包括(除其它組件以外)沿第一方向圖案化的自下層延伸的平行的鰭片，以及沿垂直於該第一方向的第二方向與該鰭片相交的平行的閘極結構。該閘極結構具有包括與該鰭片相鄰的第一導體的下部、以及包括在該鰭片的遠側的第二導體的上部。該閘極結構的該下部可具有自該鰭片的不規則高度。此外，該閘極結構的下部沿該第一方向寬於該閘極結構的該上部。該第一導體與該第二導體可彼此不同，且可由許多不同的材料組 成，例如具有不同功函數的導體；不過，該閘極結構的該上部與下源極/汲極接觸可為相同材料。
此外，閘極絕緣體位於該閘極結構的該下部與該鰭片之間，且磊晶源極/汲極結構位於該閘極結構之間的該鰭片上。另外，下源極/汲極接觸位於該源極/汲極結構上。此類下源極/汲極接觸也位於該閘極結構之間。
多個絕緣體層位於該閘極結構與該下源極/汲極接觸之間，與該閘極結構的該上部及該下部相鄰。該多個絕緣體層可由具有不同介電常數的兩個不同的絕緣體層製成。額外的上側間隙壁位於該閘極結構的該上部與該多個絕緣體層之間。該上側間隙壁僅與該閘極結構的該上部相鄰，且不與該閘極結構的該下部相鄰。該上側間隙壁可為與該多個絕緣體層不同的絕緣體材料。
此外，層間介電質位於該下源極/汲極接觸及該閘極結構的該上部上。閘極接觸延伸穿過該層間介電質並接觸該閘極結構的該上部。另外，上源極/汲極接觸延伸穿過該層間介電質並接觸該下源極/汲極接觸。
100‧‧‧底層或下層
102‧‧‧通道區或通道
103‧‧‧鰭式場效電晶體(FinFET)
104‧‧‧絕緣體或隔離材料
106‧‧‧犧牲閘極
108‧‧‧第一側壁絕緣體、側壁絕緣體層或絕緣體層
109‧‧‧遮罩
110‧‧‧鰭片、鰭片層或層
112‧‧‧下絕緣體層、絕緣體或第二側壁絕緣體
116‧‧‧閘極絕緣體或閘極氧化物
118‧‧‧源極/汲極結構、源極/汲極區或源極/汲極
120‧‧‧元件、下部、閘極或閘極結構
124‧‧‧第二側壁絕緣體、側壁絕緣體層或絕緣體層
132‧‧‧犧牲材料或犧牲源極/汲極接觸結構
134‧‧‧上側間隙壁
138‧‧‧遮罩
140‧‧‧下源極/汲極接觸
142‧‧‧上部或閘極結構
144‧‧‧第一凹部
146‧‧‧第二凹部
150‧‧‧層間介電質(ILD)
152‧‧‧源極/汲極通孔接觸或上源極/汲極接觸
154‧‧‧閘極通孔接觸
160、162‧‧‧區域
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230‧‧‧項目
H1‧‧‧高度或第一高度
H2‧‧‧高度或第二高度
H3‧‧‧第三高度
X1-X1、X2-X2、Y-Y‧‧‧線
通過參照附圖自下面的詳細說明將更好地理解本文中的實施例，這些附圖並不一定按比例繪製，且其中：
第1A圖顯示依據本文中的實施例的積體電路結構的頂部(平面)概念示意圖；
第1B圖顯示依據本文中的實施例的積體電路結構沿第1A圖中的線X1-X1的剖視概念示意圖；
第1C圖顯示依據本文中的實施例的積體電路結構沿第1A圖中的線X2-X2的剖視概念示意圖；
第1D圖顯示依據本文中的實施例的積體電路結構沿第1A圖中的線Y-Y的剖視概念示意圖；
第2A圖-第2D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第3A圖-第3D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第4A圖-第4D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第5A圖-第5D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第6A圖-第6D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第7A圖-第7D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第8A圖-第8D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第9A圖-第9D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第10A圖-第10D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第11A圖-第11D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第12A圖-第12D圖顯示分別對應第1A圖-第1D圖中所示的視圖的積體電路結構的製造階段的概念示意圖；
第13圖顯示對應第12B圖中所示的視圖的積體電路結構的製造階段的概念示意圖；以及
第14圖顯示本文中的實施例的流程圖。
如上所述，斜切是多步驟製程，其可為時間、材料及機器密集型的；並可引入額外的缺陷形成機會。另外，除了功函數金屬以外，在閘極中使用其它金屬化(例如鎢)，且常常在額外製程中凹入此類材料，其同樣可為時間、材料及機器密集型的；並可引入缺陷。
採用額外的步驟將接觸與閘極及其它FinFET元件對準(在執行自對準接觸(SAC)製程時包括這些額外步驟)。例如，通常在閘極導體上形成覆蓋層(cap layer)並在此類覆蓋層上執行化學機械拋光(chemical mechanical polishing；CMP)。不過，同樣，此類SAC製程可為時間、材料及機器密集型的。
本文中所述的製程使用經策略性設置及尺寸設定的絕緣體及間隙壁來避免斜切功函數金屬及閘極金屬凹入。另外，此類側壁絕緣體及間隙壁通過在閘極接觸與源極/汲極接觸之間設置額外間距來顧及接觸未對準，從而減少SAC製程量。
存在各種類型的電晶體，其在如何被用於電路方面稍有差別。例如，雙極型電晶體具有被標記為基極、集電極及發射極的端子。在基極的端子的小電流(亦即，在基極與發射極之間流動)可控制或切換集電極與發射極的端子之間的較大電流。另一個例子是場效電晶體，其具有被標記為閘極、源極及汲極的端子。閘極的電壓可控制源極與汲極之間的電流。在此類電晶體內，半導體(通道區)位於導電源極區與類似導電汲極(或導電源極/發射極區)之間，且當該半導體處於導電狀態時，該半導體允許電流在源極與汲極之間或集電極與發射極之間流動。閘極為導電元件，通過“閘極氧化物”(其為絕緣體)與該半導體電性隔開；且閘極內的電流/電壓使通道區導電，以允許電流在源極與汲極之間流動。類似地，在基極與發射極之間流動的電流使半導體導電，以允許電流在集電極與發射極之間流動。
正型電晶體“P型電晶體”在本徵半導體基板內使用雜質例如硼、鋁或鎵等(以形成價電子不足)作為半導體區。類似地，“N型電晶體”是負型電晶體，其在本徵半導體基板內使用雜質例如銻、砷或磷等(以形成過剩的價電子)作為半導體區。
一般來說，在一個例子中，電晶體結構通過在基板中沉積或注入雜質以形成至少一個半導體通道區來形成，被位於該基板的頂部(上)表面下方的淺溝槽隔離區環繞。本文中的“基板”可為適於給定目的的任意材料(無論現在已知還是未來開發的)，且可為例如矽基晶圓(塊體材料)、陶瓷材料、有機材料、氧化物材料、氮化物材料等，無論是已摻雜還是未摻雜。隔離結構通常通過使用高絕緣材料形成(這允許該基板的不同主動區彼此電性隔離)。此外，硬遮罩可由無 論是當前已知還是未來開發的任意合適的材料形成，例如氮化物、金屬、或有機硬遮罩，其具有大於該基板及該結構的其餘部分中所使用的絕緣體材料的硬度。
出於本文中的目的，“半導體”是一種材料或結構，其可包括注入或原位(例如，磊晶生長)雜質，以基於電子(electron)及電洞(hole)載子(carrier)濃度使該材料有時是導體而有時是絕緣體。本文中所使用的“注入製程”可採取任意合適的形式(無論現在已知還是未來開發的)且可例如為離子注入等。磊晶生長發生於加熱(有時加壓)環境下，該環境富含要生長的材料的氣體。
出於本文中的目的，“絕緣體”是相對術語，其是指與“導體”相比允許很小的電流流動(<95%)的材料或結構。本文中所提到的介電質(絕緣體)可例如自乾燥的氧環境或蒸汽生長並接著被圖案化。或者，本文中的介電質可自任意多種候選低介電常數(低K(其中K對應於二氧化矽的介電常數)材料，例如氟或碳摻雜二氧化矽、多孔二氧化矽、多孔碳摻雜二氧化矽、旋塗矽或有機聚合物介電質等)，或高介電常數(高K)材料，包括但不限於氮化矽、氮氧化矽、SiO2與Si3N4的閘極介電堆疊、氧化鉿(HfO2)、氧化鋯鉿(HfZrO2)、二氧化鋯(ZrO2)、氮氧化矽鉿(HfSiON)、氧化鋁鉿化合物(HfAlOx)、其它金屬氧化物如氧化鉭等形成(生長或沉積)。本文中的介電質的厚度可依據所需器件性能而變化。
本文中所述的導體可由任意導電材料形成，例如多晶矽、非晶矽、非晶矽與多晶矽的組合、多晶矽-鍺，通過存在合適的摻雜物賦予導電性，等等。或者，本文中的導體可為一種或多種金屬，例如鎢、鉿、鉭、鉬、鈦、或鎳、或金屬矽化物，此類金屬的任意合金，且可通過使用物理氣相沉積、化學氣相沉積，或現有技術中已知的任意其它技術來沉積。另外，本文中的一些導體可部分或全 部由具有特定功函數的金屬形成。該導體的功函數可經選擇以使用特定量的能量，以自固體材料移除電子，從而增強電晶體性能。
第1A圖-第13圖使用顯示場效電晶體(FET)尤其鰭式FET(FinFET)的例子。儘管附圖中僅顯示一種類型或有限數目的電晶體類型，但本領域的普通技術人員將理解，可通過本文中的實施例同時形成許多不同類型的電晶體，且附圖意圖顯示同時形成多種不同類型的電晶體；不過，出於清晰目的，已簡化附圖，以僅顯示有限數目的電晶體，並使讀者更容易地意識到所示的不同特徵。這並非意圖限制此揭示，因為如本領域的普通技術人員所理解的那樣，此揭示適用於包括附圖中所顯示的許多各類型電晶體的結構。
第1A圖-第1D圖顯示部分形成的FinFET結構的一個例子。更具體地說，第1A圖為依據本文中的實施例的積體電路結構的頂視(平面)概念示意圖，第1B圖為沿第1A圖中的線X1-X1的同一結構的剖視概念示意圖，第1C圖為沿第1A圖中的線X2-X2的剖視概念示意圖，以及第1D圖為沿第1A圖中的線Y-Y的剖視概念示意圖。
為形成第1A圖-第1D圖中所示的結構，可使用不同的製程。在一些示例方法中，將底層100(原位形成或經後續摻雜的半導體材料)圖案化為如第1D圖中所示的鰭片110。如第1C圖中所示，這形成“第一”層或基板結構(例如，鰭片110)。要注意，儘管該第一層可為鰭片結構，但它不需要是，且在一些實施中，該第一層可簡單地為平面層。因此，鰭片110在本文中有時被簡單通稱為層或基板。如第1D圖中所見，絕緣體或隔離材料104(例如，淺溝槽隔離STI)可經形成及高度降低以顯露鰭片110。
當圖案化這裡的任意材料時，可以任意已知的方式生長或沉積要被圖案化的該材料，且可在該材料上方形成圖案化層(例如有機光阻)。可將該圖案化層(阻劑)暴露於以光曝光圖案設置的某種模式的光輻射(例如，圖案化曝光、激光曝光等)，接著使用化學劑顯影該阻劑。此製程改變暴露於光的該阻劑部分的物理特性。接著，可沖洗掉該阻劑的一部分，使該阻劑的其它部分保護要被圖案化的該材料(沖洗掉該阻劑的哪部分取決於該阻劑是負型阻劑(保留受照部分)還是正型阻劑(沖洗掉受照部分))。接著，執行材料移除製程(例如，濕式蝕刻、非等向性蝕刻(取向依賴蝕刻)、電漿蝕刻(反應離子蝕刻(reactive ion etching；RIE)等))，以移除要被圖案化的該阻劑下方的該材料的未受保護部分。隨後，移除該阻劑，使下方材料依據該光曝光圖案(或其負型圖像)被圖案化。
第2A圖-第2D圖顯示與上述第1A圖-第1D圖相同的視圖。如第2A圖-第2D圖中所示，此類製程通過使用遮罩109形成延伸於鰭片層110的通道區102(例如，見第2C圖)上方的犧牲閘極106(通常被稱為“偽”閘極)；在一個例子中，犧牲閘極106可為多晶矽。此外，在犧牲閘極106上形成第一側壁絕緣體108或第一側間隙壁(其可為例如低k材料)。此類方法在犧牲閘極106的相對側上的鰭片層110中及/或上(通過使用例如磊晶生長或注入製程)形成源極/汲極結構118。源極/汲極結構118通過第一側壁絕緣體108在磊晶生長製程中自對準。
出於本文中的目的，“側間隙壁”是結構，通常通過沉積或生長共形絕緣層(例如任意上述絕緣體)並接著執行定向蝕刻製程(非等向性)，以與自垂直表面移除材料的速率相比較大的速率自水平表面蝕刻材料，從而保留沿結構的垂直側壁的絕緣材料來形成。保留於垂直側壁上的此材料被稱為側間隙壁。
第3A圖-第3D圖顯示與上述的第1A圖-第1D圖相同的相關視圖。如第3A圖-第3D圖中所示，此類製程在第一側壁絕緣體108上形成第二側壁絕緣體124(例如，第二側間隙壁)。此類第二側壁絕緣體124可為共形絕緣體層(例如，在一個例子中，其可為接觸蝕刻停止層(contact etch stop layer；CESL)如氮化物等)，並因此第二側壁絕緣體124初始也在該源極/汲極區上及隔離材料104上形成為薄層(在下述後續製程中移除)。要注意，第一側壁絕緣體108與第二側壁絕緣體124可為不同的材料，它們可具有不同的介電常數。
在形成第二側壁絕緣體124以後，這些製程形成下絕緣體層112(例如，氧化物，如二氧化矽)。因此，下絕緣體層112可接觸第二側壁絕緣體124，並位於犧牲閘極106之間。通過使用例如CMP，可將所有元件平坦化至如第3A圖-第3D圖中所示的相同高度。
第4A圖-第4D圖顯示與上述的第1A圖-第1D圖相同的視圖。在第4A圖-第4D圖中，這些方法將犧牲閘極106及第一側壁絕緣體108的高度從自層110的頂部的第一高度(H1)降低至自層110的頂部的降低的高度(H2)，在製程中將下絕緣體層112及第二側壁絕緣體124保留於該第一高度(H1)。在一個例子中，可首先執行僅攻擊犧牲閘極106(例如，僅攻擊多晶矽)的選擇性反應離子蝕刻(RIE)製程，接著執行僅移除第一側壁絕緣體108(例如，僅攻擊二氧化矽)的RIE製程。
選擇性材料移除製程首先自可相對彼此被選擇性移除的材料形成元件，並接著後續應用移除技術，以移除一種材料，同時使其它材料基本不受影響。儘管本文中提到一些材料選擇及選擇性移除技術，但本領域的普通技術人員將理解，可使用不同的材料，只要此類材料可相對彼此被選擇性移除即可。要 注意，儘管一些選擇性材料移除製程可部分移除相鄰材料(或形成圓化)，這些可能未被完全顯示於附圖中，以簡化附圖並因此更清楚地示例本文中的概念。
第5A圖-第5D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第5A圖-第5D圖中所示，本文中的方法移除犧牲閘極106(但將第一及第二側壁絕緣體108、124及絕緣體112保留於原位)。再次，可使用僅攻擊犧牲閘極106的材料(例如，僅攻擊多晶矽)的選擇性材料移除製程，以移除犧牲閘極106。閘極絕緣體116(例如，閘極氧化物)可被沉積或生長(直接接觸)於鰭片層110的通道區102上。
沉積一種或多種導體(例如，不同功函數導體層，該所有層通過元件120被共同顯示於附圖中)，以填充犧牲閘極106先前所處的第一與第二側壁絕緣體108、124之間的空間。此外，元件120可代表不同功函數金屬，例如在p型及n型電晶體中所使用的p型及n型功函數金屬。因此，如第5A圖-第5D圖中所示，此製程用第一導體替代犧牲閘極106，以形成本文中所稱的閘極結構的下部，在製程中初始形成閘極結構的下部120(例如，高k/金屬閘極(high-k/metal gate；HKMG))至第一高度(H1)並完全覆蓋降低的高度(H2)的第一側壁絕緣體的側面及頂部。在此類製程以後可移除多餘的HKMG材料。
此外，第5C圖顯示此製程形成鰭式場效電晶體(FinFET)103，其包括通道區102、位於通道區102的側面上的源極/汲極區118、閘極氧化物(絕緣體)116、以及閘極(導體)120。如上所述，在閘極結構的下部120中的電壓改變通道102的導電性，以允許或防止電流在源極/汲極118之間流動。通過此類製程，在本文中的各鰭片110上形成多個FinFET 103。
第6A圖-第6D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第6A圖-第6D圖中所示，本文中的方法圖案化遮罩138並執行選擇性材料移除(例如，蝕刻)，以移除位於該閘極結構的下部120之間的下絕緣體層112的部分。此製程還可為定向的並移除位於水平表面上的第二側壁絕緣體124的部分(同時保留位於第一側壁絕緣體108上的第二側壁絕緣體124的大部分)，但此製程是選擇性的，以便不移除源極/汲極結構118。要注意，如第6A圖-第6D圖中所示，當蝕刻掉下絕緣體層112的部分時，可稍微降低該上部的厚度或第二側壁絕緣體112的高度。此外，當閘極結構的下部120(具有高度H1)完全覆蓋第一側壁絕緣體108的側面及頂部(具有高度H2)時，執行此選擇性材料移除製程，以防止第一側壁絕緣體108被移除，即使第二側壁絕緣體124的一部分被移除。因此，第6A圖-第6D圖中所示的製程暴露源極/汲極結構118的其中一者(如遮罩138所允許的那樣)，但基本避免移除第一或第二側壁絕緣體108、124或源極/汲極結構118。
第7A圖-第7D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第7A圖-第7D圖中所示，本文中的方法用犧牲材料132(例如光聚合層(optical polymerization layer；OPL))填充先前被該下絕緣體層所佔據的空間，可後續選擇性移除該犧牲材料。因此，如第7A圖-第7D圖中所示，本文中的方法在該閘極結構的下部120之間的源極/汲極結構118的其中暴露一者上形成本文中所稱的犧牲源極/汲極接觸結構132至該第一高度(H1)(可能在CMP或類似製程以後)。
第8A圖-第8D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第8A圖-第8D圖中所示，本文中的方法將該閘極結構的下部120的高度降低至自鰭片110的第三高度(H3)，該第三高度小於該降低的高度(H2)，以形成第一 凹部144。通過使用反應劑執行此凹入製程，該反應劑僅攻擊閘極結構的下部120(第一導體)及第二側壁絕緣體124的材料，而不攻擊第一側壁絕緣體108的材料，且不攻擊犧性源極/汲極接觸結構132的材料。
第9A圖-第9D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第9A圖-第9D圖中所示，本文中的方法還在第一凹部144中形成上側間隙壁134(例如，氮化物，如氮化矽)。上面討論側間隙壁形成，且通過此類製程，上側間隙壁134接觸犧牲源極/汲極接觸結構132的側壁、該閘極結構的下部120、第一側壁絕緣體108、以及第二側壁絕緣體124。如第9A圖-第9D圖中所示，在該側間隙壁形成製程中回蝕刻上側間隙壁134，以僅部分地填充第一凹部144，且上側間隙壁134延伸於第三高度(H3)與第二高度(H2)之間，以填充該第一凹部。上側間隙壁134可為與第一及第二側壁絕緣體108、124不同的絕緣體材料。
第10A圖-第10D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第10A圖-第10D圖中所示，本文中的方法移除犧牲源極/汲極接觸結構132，以留下第二凹部146。再次，此類選擇性材料移除製程使用僅攻擊犧性源極/汲極接觸結構132的材料的反應劑(例如，如OPL灰)。
第11A圖-第11D圖顯示與上述的第1A圖-第1D圖相同的視圖。如第11A圖-第11D圖中所示，本文中的方法沉積一個或多個共形導體層，以在第一凹部144中且同時在上側間隙壁134之間的第二凹部146中形成第二導體。可移除多餘導體(例如，CMP等)。該第二導體也可由具有不同功函數的多個導體層形成，或者，該第二導體可為單種導體材料(例如，鎢)。此製程同時形成該閘極結構的上部142以及下源極/汲極接觸140。要注意，在形成該閘極結構的上 部142之前，此製程不需要斜切該閘極結構的下部120，從而避免會減慢當前製程的傳統斜切步驟。
在第12A圖-第12D圖中，沉積或生長層間介電質(interlayer dielectric；ILD)150，並通過ILD 150圖案化通孔開口(via opening)。隨後，用導體填充此類通孔開口，以形成通孔接觸，包括源極/汲極通孔接觸152(第11A圖及第11B圖)以及閘極通孔接觸154(第11A圖及第11C圖)。要注意，此製程避免傳統的金屬凹入、閘極覆蓋沉積、以及閘極覆蓋CMP製程，通過不執行這些步驟，此製程比傳統製程更有效且更不容易出錯。
第13圖是與沿第12A圖中的剖面X2-X2的第12C圖中所示的視圖類似的視圖。第13圖顯示前述製程仍允許形成經適當尺寸設定的閘極，即使該閘極的下部120的高度(自鰭片110)不一致，此時，較長的上部142顧及任意高度變化，如第13圖的區域162中所示。換句話說，即使第一凹部144因該閘極結構的下部120的不一致高度而具有不規則的深度/尺寸，該閘極結構的上部142的共形形成也顧及所有此類不規則。此外，第13圖中的區域160顯示即使在下源極/汲極接觸140與上源極/汲極接觸152之間存在一些未對準，由於上側間隙壁134與第一及第二側壁絕緣體108、124所提供的額外空間及絕緣，也不會在上源極/汲極接觸152與閘極結構120、142之間形成短路(不良電性連接)。
因此，第12A圖-第13圖顯示此類製程產生包括(除其它組件以外)沿第一方向圖案化的自下層100延伸的平行的鰭片110以及沿垂直於該第一方向的第二方向與鰭片110相交的平行的閘極結構120、142的示例結構。這裡，該第一方向與第二方向都平行於鰭片110的頂部表面(例如，見第1A圖)。該閘 極結構具有包括與鰭片110相鄰的第一導體的下部120，以及包括在鰭片110的遠側的第二導體的上部142(接觸下部120)。
該閘極結構的下部120可具有自該鰭片的不規則高度，如第13圖中所示。此外，閘極結構的下部120沿該第一方向寬於該閘極結構的上部142，因為該上側間隙壁134使第一凹部144變窄(例如，見第10C圖)，從而使該閘極結構的上部142較窄。閘極結構的下部120(第一導體)與該閘極結構的上部142(第二導體)可彼此不同，且分別可由許多不同的材料層組成，例如具有不同功函數的多個導體層。在一些實施中，該閘極結構的下部120包括功函數金屬(work function metal；WFM)，而該閘極結構的上部142為單個導體(例如，鎢等)。
此外，閘極絕緣體116位於(接觸)該閘極結構的下部120與鰭片110之間，且磊晶源極/汲極結構118位於(接觸)閘極結構120、142之間的鰭片110上。另外，下源極/汲極接觸140位於(接觸)源極/汲極結構118上。此類下源極/汲極接觸140也位於閘極結構120、142之間。
多個側壁絕緣體層108、124位於閘極結構120、142與下源極/汲極接觸140之間，與該閘極結構的上部142及下部120相鄰。多個絕緣體層108、124彼此接觸且可由具有不同介電常數的不同絕緣體層製成。設置額外的上側間隙壁134以接觸並位於該閘極結構的上部142與多個絕緣體層108、124之間。上側間隙壁134僅與該閘極結構的上部142相鄰且不與該閘極結構的下部120相鄰。上側間隙壁134可為與多個絕緣體層108、124不同的絕緣體材料。
此外，在下源極/汲極接觸140及閘極結構120、142的上部142上設置(接觸)層間介電質。閘極接觸154延伸穿過該層間介電質並接觸該閘極結 構的上部142。另外，上源極/汲極接觸152延伸穿過該層間介電質並接觸下源極/汲極接觸140。閘極結構的上部142與下源極/汲極接觸140可為相同的材料。
如第14圖中的流程圖所示，本文中的示例方法圖案化層，以形成自該層延伸的平行的鰭片，其中，在項目202中，沿第一方向/取向圖案化該鰭片。另外，在項目204中，此類方法圖案化沿垂直於該第一方向的第二方向與該鰭片相交的平行的犧牲閘極。在項目206中，這些方法在該犧牲閘極的側壁上形成第一側壁絕緣體。在項目208中，本文中的方法在該犧牲閘極之間的該鰭片上磊晶生長源極/汲極結構。在項目210中，這些方法在該第一側壁絕緣體上形成第二側壁絕緣體，並在該犧牲閘極之間的該第二側壁絕緣體上形成下絕緣體層。
如項目212中所示，此類方法將該犧牲閘極及該第一側壁絕緣體的高度從自該鰭片的第一高度降低至自該鰭片的降低的高度，在製程中將該下絕緣體層及該第二側壁絕緣體保留於該第一高度。此外，如項目214中所示，這些方法用第一導體替代該犧牲閘極，以形成閘極結構的下部，在製程中形成閘極結構的該下部至該第一高度並覆蓋該第一側壁絕緣體的側面及頂部。
此外，如項目216中所示，這些方法移除該下絕緣體層的部分以及該第二側壁絕緣體的相應水平部分，而閘極結構的該下部覆蓋該第一側壁絕緣體。在項目216中，此製程暴露該源極/汲極結構的其中一者，但避免自該第一側壁絕緣體或該閘極結構的該下部移除該第二側壁絕緣體。在項目218中，此類方法在該閘極結構的該下部之間的該源極/汲極結構的其中暴露一者上形成犧牲源極/汲極接觸結構至該第一高度。在項目220中，這些方法將該閘極結構的該下部的高度降低至小於該降低的高度(至自該鰭片的第三高度)，以形成第一凹部。
在項目222中，這些方法還在該犧牲源極/汲極接觸結構的側壁、該閘極結構的該下部、該第一側壁絕緣體、以及該第二側壁絕緣體上的該第一凹部中形成上側間隙壁。該上側間隙壁部分地填充該第一凹部，且該上側間隙壁延伸該第一凹部的深度。
在項目224中，本文中的方法移除該犧牲源極/汲極接觸結構，以留下第二凹部(但避免該閘極結構的該下部的任意斜切，如上所述)。在項目226中，此類方法在該上側間隙壁之間的該第一凹部中以及在該第二凹部中形成第二導體，以形成該閘極的上部及源極/汲極接觸結構(同時避免SAC覆蓋形成及CMP，如上所述)。該上側間隙壁可為與該第一側壁絕緣體及該第二側壁絕緣體不同的絕緣體材料，且該第一側壁絕緣體與該第二側壁絕緣體具有不同的介電常數。
此外，如項目228中所示，層間介電質被設置於(接觸)下源極/汲極接觸、該閘極結構的該上部、以及該下絕緣體上(接觸)上。在項目230中，通過該ILD形成接觸，其中，閘極接觸延伸穿過該層間介電質並接觸該閘極結構的該上部。另外，在項目230中，形成上源極/汲極接觸，以延伸穿過該層間介電質並接觸該下源極/汲極接觸。另外，該閘極結構的該上部與該下源極/汲極接觸可為相同材料。
本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制上述實施例。除非上下文中另外明確指出，否則本文中所使用的單數形式“一”、“一個”以及“該”也意圖包括複數形式。而且，本文中所使用的術語如“右”、“左”、“垂直”、“水平”、“頂部”、“底部”、“上”、“下”、“上方”、“下方”、“平行”、“直立”等意圖說明當它們以附圖中取向並顯示時的相對位置(除非另外指出)，且 術語如“接觸”、“直接接觸”、“毗鄰”、“直接相鄰”、“緊鄰”等意圖表示至少一個元件物理接觸另一個元件(沒有其它元件隔開所述元件)。本文中所使用的術語“橫向”說明當元件以附圖中取向並顯示時這些元件的相對位置，尤其表示一個元件位於另一個元件的側邊而不是另一個元件的上方或下方。例如，一個元件橫向鄰近另一個元件將在該另一個元件旁邊，一個元件橫向緊鄰另一個元件將直接在該另一個元件旁邊，以及一個元件橫向圍繞另一個元件將鄰近並環繞該另一個元件的外側壁。
本文中的實施例可用於各種電子應用，包括但不限於高級感測器、記憶體/資料儲存器、半導體、微處理器以及其它應用。製造者可以原始晶圓形式(亦即，作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得器件及結構，例如積體電路(IC)晶片。在後一種情況中，該晶片設於單晶片封裝件中(例如塑料承載件，其具有附著至主機板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，接著將該晶片與其它晶片、分立電路元件和/或其它信號處理器件整合，作為(a)中間產品例如主機板的部分，或者作為(b)最終產品的部分。該最終產品可為包括積體電路晶片的任意產品，涉及範圍從玩具及其它低端應用直至具有顯示器、鍵盤或其它輸入器件以及中央處理器的先進電腦產品。
對本實施例所作的說明是出於示例及說明目的，而非意圖詳盡無遺或限於所揭示形式的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離本文中的實施例的範圍及精神。該實施例經選擇及說明以最佳解釋此類實施例的原理，及實際應用，以及使本領域的其他普通技術人員能夠理解具有適於所考慮的特定應用的各種變更的各種實施例。
儘管上面僅結合有限數目的實施例來詳細說明，但很容易理解，本文中的實施例不限於這些揭示。相反，可修改本文中的元件以包含此前未說明但符合本文的精神及範圍的任意數目的變化、更改、替代或等同佈置。此外，儘管已說明各種實施例，但應當理解，本文中的實施例可僅被某些所述實施例包括。相應地，所附的申請專利範圍將不被視為被上述說明限制。除非特別說明，否則提及單數元件並不意圖意味著“一個且僅一個”，而是“一個或多個”。本申請中所述的各種實施例的元件的所有結構及功能等同(其為本領域的普通技術人員已知的或後來逐漸知道的)通過引用明確包含於此並意圖被本申請包括。因此，應當理解，在所揭示的特定實施例中可作變更，其落入如所附申請專利範圍所概述的上述範圍內。
102‧‧‧通道區或通道
108‧‧‧第一側壁絕緣體、側壁絕緣體層或絕緣體層
110‧‧‧鰭片、鰭片層或層
112‧‧‧下絕緣體層、絕緣體或第二側壁絕緣體
116‧‧‧閘極絕緣體或閘極氧化物
118‧‧‧源極/汲極結構、源極/汲極區或源極/汲極
120‧‧‧元件、下部、閘極或閘極結構
124‧‧‧第二側壁絕緣體、側壁絕緣體層或絕緣體層
134‧‧‧上側間隙壁
140‧‧‧下源極/汲極接觸
142‧‧‧上部或閘極結構
150‧‧‧層間介電質(ILD)
154‧‧‧閘極通孔接觸
160、162‧‧‧區域
X2-X2‧‧‧線

Claims (20)

  1. 一種積體電路裝置，包括：
    平行的鰭片，自層延伸，其中，沿第一方向圖案化該鰭片；
    平行的閘極結構，沿垂直於該第一方向的第二方向與該鰭片相交，其中，該閘極結構具有與該鰭片相鄰的下部以及在該鰭片的遠側的上部；
    源極/汲極結構，位於該閘極結構之間的該鰭片上；
    源極/汲極接觸，位於該源極/汲極結構上；
    多個絕緣體層，位於該閘極結構與該源極/汲極接觸之間；以及
    上側間隙壁，位於該閘極結構的該上部與該多個絕緣體層之間。
  2. 如申請專利範圍第1項所述的積體電路裝置，其中，該上側間隙壁僅與該閘極結構的該上部相鄰，且不與該閘極結構的該下部相鄰。
  3. 如申請專利範圍第1項所述的積體電路裝置，其中，該多個絕緣體層與該閘極結構的該上部及該下部相鄰。
  4. 如申請專利範圍第1項所述的積體電路裝置，其中，該閘極結構的下部沿該第一方向寬於該閘極結構的該上部。
  5. 如申請專利範圍第1項所述的積體電路裝置，其中，該上側間隙壁是與該多個絕緣體層不同的絕緣體材料。
  6. 如申請專利範圍第1項所述的積體電路裝置，其中，該多個絕緣體層包括具有不同介電常數的兩個不同絕緣體層。
  7. 如申請專利範圍第1項所述的積體電路裝置，其中，該源極/汲極接觸與該閘極結構的該上部為相同材料。
  8. 一種積體電路裝置，包括：
    平行的鰭片，自層延伸，其中，沿第一方向圖案化該鰭片；
    平行的閘極結構，沿垂直於該第一方向的第二方向與該鰭片相交，其中，該閘極結構具有包括與該鰭片相鄰的第一導體的下部以及包括在該鰭片的遠側的第二導體的上部，以及其中，該第一導體與該第二導體為不同材料；
    閘極絕緣體，位於該閘極結構的該下部與該鰭片之間；
    磊晶源極/汲極結構，位於該閘極結構之間的該鰭片上；
    下源極/汲極接觸，位於該源極/汲極結構上；
    多個絕緣體層，位於該閘極結構與該下源極/汲極接觸之間；
    上側間隙壁，位於該閘極結構的該上部與該多個絕緣體層之間；
    層間介電質，位於該下源極/汲極接觸及該閘極結構的該上部上；
    閘極接觸，延伸穿過該層間介電質並接觸該閘極結構的該上部；以及
    上源極/汲極接觸，延伸穿過該層間介電質並接觸該下源極/汲極接觸。
  9. 如申請專利範圍第8項所述的積體電路裝置，其中，該上側間隙壁僅與該閘極結構的該上部相鄰，且不與該閘極結構的該下部相鄰。
  10. 如申請專利範圍第8項所述的積體電路裝置，其中，該多個絕緣體層與該閘極結構的該上部及該下部相鄰。
  11. 如申請專利範圍第8項所述的積體電路裝置，其中，該閘極結構的下部沿該第一方向寬於該閘極結構的該上部。
  12. 如申請專利範圍第8所述的積體電路裝置，其中，該上側間隙壁是與該多個絕緣體層不同的絕緣體材料。
  13. 如申請專利範圍第8項所述的積體電路裝置，其中，該多個絕緣體層包括具有不同介電常數的兩個不同絕緣體層。
  14. 如申請專利範圍第8項所述的積體電路裝置，其中，該閘極結構自該鰭片具有不規則的高度。
  15. 一種方法，包括：
    在犧牲閘極的側壁上形成第一側壁絕緣體；
    在該犧牲閘極之間的鰭片上磊晶生長源極/汲極結構；
    在該第一側壁絕緣體上形成第二側壁絕緣體；
    在該犧牲閘極之間的該第二側壁絕緣體上形成下絕緣體層；
    將該犧牲閘極及該第一側壁絕緣體的高度從第一高度降低至降低的高度，在製程中將該下絕緣體層及該第二側壁絕緣體保留於該第一高度；
    用第一導體替代該犧牲閘極，以形成閘極結構的下部，在製程中形成該閘極結構的下部至該第一高度並覆蓋該第一側壁絕緣體；
    移除該下絕緣體層的部分，而該閘極結構的下部覆蓋該第一側壁絕緣體，在製程中暴露該源極/汲極結構的其中一者；
    在該閘極結構的該下部之間的該源極/汲極結構的其中暴露一者上形成犧牲源極/汲極接觸結構至該第一高度；
    將該閘極結構的該下部的高度降低至小於該降低的高度的第三高度，以形成第一凹部；
    在該犧牲源極/汲極接觸結構的側壁、該閘極結構的該下部、該第一側壁絕緣體及該第二側壁絕緣體上的該第一凹部中形成上側間隙壁；
    移除該犧牲源極/汲極接觸結構，以留下第二凹部；以及
    在該上側間隙壁之間的該第一凹部中及在該第二凹部中形成第二導體，以形成該閘極結構的上部，並在該犧牲源極/汲極接觸結構所處的位置形成源極/汲極接觸結構。
  16. 如申請專利範圍第15項所述的方法，其中，該上側間隙壁部分地填充該第一凹部。
  17. 如申請專利範圍第15項所述的方法，其中，該上側間隙壁延伸該第一凹部的深度。
  18. 如申請專利範圍第15項所述的方法，其中，所述移除該下絕緣體層的部分避免自該第一側壁絕緣體移除該第二側壁絕緣體。
  19. 如申請專利範圍第15項所述的方法，其中，該上側間隙壁是與該第一側壁絕緣體及該第二側壁絕緣體不同的絕緣體材料。
  20. 如申請專利範圍第15項所述的方法，其中，該第一側壁絕緣體與該第二側壁絕緣體具有不同的介電常數。
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