CN110993602A - 在栅极与源极/漏极接触之间具有绝缘层的finfet - Google Patents

在栅极与源极/漏极接触之间具有绝缘层的finfet Download PDF

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CN110993602A
CN110993602A CN201910839433.9A CN201910839433A CN110993602A CN 110993602 A CN110993602 A CN 110993602A CN 201910839433 A CN201910839433 A CN 201910839433A CN 110993602 A CN110993602 A CN 110993602A
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gate structure
insulator
source
gate
fin
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臧辉
拉尔特斯·柯洛米克斯
席史·马尼·潘迪
朴灿柔
谢瑞龙
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明涉及在栅极与源极/漏极接触之间具有绝缘层的FINFET，其中，制程形成集成电路装置，该集成电路装置包括平行的鳍片，其中，沿第一方向图案化该鳍片。平行栅极结构沿垂直于该第一方向的第二方向与该鳍片相交，其中，该栅极结构具有与该鳍片相邻的下部以及在该鳍片的远侧的上部。源极/漏极结构位于该栅极结构之间的该鳍片上。源极/漏极接触位于该源极/漏极结构上，且多个绝缘体层位于该栅极结构与该源极/漏极接触之间。额外的上侧间隙壁位于该栅极结构的该上部与该多个绝缘体层之间。

Description

在栅极与源极/漏极接触之间具有绝缘层的FINFET
技术领域
本申请涉及集成电路器件(device)，以及用于制造此类器件的制程，尤其涉及通过在栅极与源极/漏极接触之间设置额外绝缘层来避免许多传统制程步骤并顾及接触未对准。
背景技术
集成电路器件使用晶体管执行许多不同的功能，且这些晶体管可采取许多不同的形式，从平面晶体管到使用“鳍片”模式结构的晶体管(例如，鳍式场效应(FinFET)晶体管)。鳍式晶体管的鳍片是自衬底延伸或者具有作为衬底的部分的底部表面的薄而长的六面形状(某种程度上为矩形)；具有长度大于宽度的侧面、具有与该侧面在某种程度上相似的长度(但具有更窄的宽度)的顶部及底部，以及自衬底的高度与该侧面的宽度大致相同但仅与该顶部及/或底部大致一样宽的端部。在此类鳍片结构中可能发生圆化及不平坦的成形(尤其在角落及顶部)，且此类结构常常具有圆化、渐窄的形状；不过，此类结构高度地区别于平面器件(尽管两种类型器件都非常有用)。
在一个例子中，传统制程在相交栅极之间的鳍片上形成源极/漏极。常使用功函数金属作为栅极的部分(portion)且此类功函数金属可能需要被斜切。关于FinFET中的功函数金属的斜切是在功函数金属层上沉积保护填充材料，凹入该保护填充材料，蚀刻掉延伸于该保护填充材料上方的任意暴露功函数金属材料，以及后续移除该保护填充材料的制程；不过，此类多步骤制程是时间、材料及机器密集型的；且引入额外的缺陷形成机会。另外，除了功函数金属以外，在栅极中使用其它金属化(例如钨)，且常常在额外制程中凹入此类材料，其同样可为时间、材料及机器密集型的；并可引入缺陷。采用额外的步骤将接触(contact)与栅极及其它FinFET元件对准(在执行自对准接触(self-aligned contact；SAC)制程时包括这些额外步骤)；不过，同样，此类SAC制程可为时间、材料及机器密集型的。
发明内容
本文中的示例方法图案化层，以形成自该层延伸的平行的鳍片，其中，沿第一方向图案化该鳍片。这些方法还图案化沿垂直于该第一方向的第二方向与该鳍片相交的平行的牺牲栅极，在该牺牲栅极的侧壁上形成第一侧壁绝缘体，在该牺牲栅极之间的该鳍片上外延生长源极/漏极结构，在该第一侧壁绝缘体上形成第二侧壁绝缘体，以及形成与该牺牲栅极之间的该第二侧壁绝缘体接触的下绝缘体层。在一些实施中，该第一侧壁绝缘体与该第二侧壁绝缘体可具有不同的介电常数。
此类方法降低该牺牲栅极及该第一侧壁绝缘体的高度(从自该鳍片的第一高度降低至自该鳍片的降低的高度)，在制程中保留该下绝缘体层及该第二侧壁绝缘体不变并在该第一高度。此外，这些方法用第一导体替代该牺牲栅极，以形成栅极结构的下部，在制程中形成栅极结构的该下部至该第一高度并覆盖该降低高度的第一侧壁绝缘体。此外，这些方法移除该下绝缘体层的部分以及该第二侧壁绝缘体的相应水平部分(例如，非等向性蚀刻)，而该栅极结构的该下部覆盖该第一侧壁绝缘体，在制程中暴露该源极/漏极结构的其中一者(但此类制程避免自该第一侧壁绝缘体或该栅极结构的该下部移除该第二侧壁绝缘体)。此类方法在该栅极结构的该下部之间的该源极/漏极结构的其中暴露一者上形成牺牲源极/漏极接触结构(至该第一高度)。此外，这些方法降低该栅极结构的该下部的高度(降低至自该鳍片的第三高度，该第三高度小于该“降低的”高度)，以形成第一凹部。
这些方法还在该第一凹部中形成上侧间隙壁(upper sidewall spacer)，在制程中使该上侧间隙壁接触该牺牲源极/漏极接触结构的侧壁、该栅极结构的该下部、该第一侧壁绝缘体、以及该第二侧壁绝缘体。该上侧间隙壁部分地填充该第一凹部，且该上侧间隙壁仅延伸该第一凹部的深度。该上侧间隙壁可为与该第一侧壁绝缘体及该第二侧壁绝缘体不同的绝缘体材料。本文中的方法移除该牺牲源极/漏极接触结构以留下第二凹部，并在该上侧间隙壁之间的该第一凹部中及在该第二凹部中形成第二导体，以同时形成该栅极结构的上部及下源极/漏极接触结构。
本文中的各种示例集成电路装置包括(除其它组件以外)沿第一方向图案化的自下层延伸的平行的鳍片，以及沿垂直于该第一方向的第二方向与该鳍片相交的平行的栅极结构。该栅极结构具有包括与该鳍片相邻的第一导体的下部、以及包括在该鳍片的远侧的第二导体的上部。该栅极结构的该下部可具有自该鳍片的不规则高度。此外，该栅极结构的下部沿该第一方向宽于该栅极结构的该上部。该第一导体与该第二导体可彼此不同，且可由许多不同的材料组成，例如具有不同功函数的导体；不过，该栅极结构的该上部与下源极/漏极接触可为相同材料。
此外，栅极绝缘体位于该栅极结构的该下部与该鳍片之间，且外延源极/漏极结构位于该栅极结构之间的该鳍片上。另外，下源极/漏极接触位于该源极/漏极结构上。此类下源极/漏极接触也位于该栅极结构之间。
多个绝缘体层位于该栅极结构与该下源极/漏极接触之间，与该栅极结构的该上部及该下部相邻。该多个绝缘体层可由具有不同介电常数的两个不同的绝缘体层制成。额外的上侧间隙壁位于该栅极结构的该上部与该多个绝缘体层之间。该上侧间隙壁仅与该栅极结构的该上部相邻，且不与该栅极结构的该下部相邻。该上侧间隙壁可为与该多个绝缘体层不同的绝缘体材料。
此外，层间介电质位于该下源极/漏极接触及该栅极结构的该上部上。栅极接触延伸穿过该层间介电质并接触该栅极结构的该上部。另外，上源极/漏极接触延伸穿过该层间介电质并接触该下源极/漏极接触。
附图说明
通过参照附图自下面的详细说明将更好地理解本文中的实施例，这些附图并不一定按比例绘制，且其中：
图1A显示依据本文中的实施例的集成电路结构的顶部(平面)概念示意图；
图1B显示依据本文中的实施例的集成电路结构沿图1A中的线X1-X1的剖视概念示意图；
图1C显示依据本文中的实施例的集成电路结构沿图1A中的线X2-X2的剖视概念示意图；
图1D显示依据本文中的实施例的集成电路结构沿图1A中的线Y-Y的剖视概念示意图；
图2A-图2D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图3A-图3D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图4A-图4D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图5A-图5D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图6A-图6D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图7A-图7D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图8A-图8D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图9A-图9D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图10A-图10D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图11A-图11D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图12A-图12D显示分别对应图1A-图1D中所示的视图的集成电路结构的制造阶段的概念示意图；
图13显示对应图12B中所示的视图的集成电路结构的制造阶段的概念示意图；以及
图14显示本文中的实施例的流程图。
具体实施方式
如上所述，斜切是多步骤制程，其可为时间、材料及机器密集型的；并可引入额外的缺陷形成机会。另外，除了功函数金属以外，在栅极中使用其它金属化(例如钨)，且常常在额外制程中凹入此类材料，其同样可为时间、材料及机器密集型的；并可引入缺陷。
采用额外的步骤将接触与栅极及其它FinFET元件对准(在执行自对准接触(SAC)制程时包括这些额外步骤)。例如，通常在栅极导体上形成覆盖层(cap layer)并在此类覆盖层上执行化学机械抛光(chemical mechanical polishing；CMP)。不过，同样，此类SAC制程可为时间、材料及机器密集型的。
本文中所述的制程使用经策略性设置及尺寸设定的绝缘体及间隙壁来避免斜切功函数金属及栅极金属凹入。另外，此类侧壁绝缘体及间隙壁通过在栅极接触与源极/漏极接触之间设置额外间距来顾及接触未对准，从而减少SAC制程量。
存在各种类型的晶体管，其在如何被用于电路方面稍有差别。例如，双极型晶体管具有被标记为基极、集电极及发射极的端子。在基极的端子的小电流(也就是，在基极与发射极之间流动)可控制或切换集电极与发射极的端子之间的较大电流。另一个例子是场效应晶体管，其具有被标记为栅极、源极及漏极的端子。栅极的电压可控制源极与漏极之间的电流。在此类晶体管内，半导体(沟道区)位于导电源极区与类似导电漏极(或导电源极/发射极区)之间，且当该半导体处于导电状态时，该半导体允许电流在源极与漏极之间或集电极与发射极之间流动。栅极为导电元件，通过“栅极氧化物”(其为绝缘体)与该半导体电性隔开；且栅极内的电流/电压使沟道区导电，以允许电流在源极与漏极之间流动。类似地，在基极与发射极之间流动的电流使半导体导电，以允许电流在集电极与发射极之间流动。
正型晶体管“P型晶体管”在本征半导体衬底内使用杂质例如硼、铝或镓等(以形成价电子不足)作为半导体区。类似地，“N型晶体管”是负型晶体管，其在本征半导体衬底内使用杂质例如锑、砷或磷等(以形成过剩的价电子)作为半导体区。
一般来说，在一个例子中，晶体管结构通过在衬底中沉积或注入杂质以形成至少一个半导体沟道区来形成，被位于该衬底的顶部(上)表面下方的浅沟槽隔离区环绕。本文中的“衬底”可为适于给定目的的任意材料(无论现在已知还是未来开发的)，且可为例如硅基晶圆(块体材料)、陶瓷材料、有机材料、氧化物材料、氮化物材料等，无论是已掺杂还是未掺杂。隔离结构通常通过使用高绝缘材料形成(这允许该衬底的不同主动区彼此电性隔离)。此外，硬掩膜可由无论是当前已知还是未来开发的任意合适的材料形成，例如氮化物、金属、或有机硬掩膜，其具有大于该衬底及该结构的其余部分中所使用的绝缘体材料的硬度。
出于本文中的目的，“半导体””是一种材料或结构，其可包括注入或原位(例如，外延生长)杂质，以基于电子(electron)及空穴(hole)载流子(carrier)浓度使该材料有时是导体而有时是绝缘体。本文中所使用的“注入制程”可采取任意合适的形式(无论现在已知还是未来开发的)且可例如为离子注入等。外延生长发生于加热(有时加压)环境下，该环境富含要生长的材料的气体。
出于本文中的目的，“绝缘体”是相对术语，其是指与“导体”相比允许很小的电流流动(<95％)的材料或结构。本文中所提到的介电质(绝缘体)可例如自干燥的氧环境或蒸汽生长并接着被图案化。或者，本文中的介电质可自任意多种候选低介电常数(低K(其中K对应于二氧化硅的介电常数)材料，例如氟或碳掺杂二氧化硅、多孔二氧化硅、多孔碳掺杂二氧化硅、旋涂硅或有机聚合物介电质等)，或高介电常数(高K)材料，包括但不限于氮化硅、氮氧化硅、SiO2与Si3N4的栅极介电堆叠、氧化铪(HfO2)、氧化锆铪(HfZrO2)、二氧化锆(ZrO2)、氮氧化硅铪(HfSiON)、氧化铝铪化合物(HfAlOx)、其它金属氧化物如氧化钽等形成(生长或沉积)。本文中的介电质的厚度可依据所需器件性能而变化。
本文中所述的导体可由任意导电材料形成，例如多晶硅、非晶硅、非晶硅与多晶硅的组合、多晶硅-锗，通过存在合适的掺杂物赋予导电性，等等。或者，本文中的导体可为一种或多种金属，例如钨、铪、钽、钼、钛、或镍、或金属硅化物，此类金属的任意合金，且可通过使用物理气相沉积、化学气相沉积，或现有技术中已知的任意其它技术来沉积。另外，本文中的一些导体可部分或全部由具有特定功函数的金属形成。该导体的功函数可经选择以使用特定量的能量，以自固体材料移除电子，从而增强晶体管性能。
图1A-图13使用显示场效应晶体管(FET)尤其鳍式FET(FinFET)的例子。尽管附图中仅显示一种类型或有限数目的晶体管类型，但本领域的普通技术人员将理解，可通过本文中的实施例同时形成许多不同类型的晶体管，且附图意图显示同时形成多种不同类型的晶体管；不过，出于清晰目的，已简化附图，以仅显示有限数目的晶体管，并使读者更容易地意识到所示的不同特征。这并非意图限制此揭示，因为如本领域的普通技术人员所理解的那样，此揭示适用于包括附图中所显示的许多各类型晶体管的结构。
图1A-图1D显示部分形成的FinFET结构的一个例子。更具体地说，图1A为依据本文中的实施例的集成电路结构的顶视(平面)概念示意图，图1B为沿图1A中的线X1-X1的同一结构的剖视概念示意图，图1C为沿图1A中的线X2-X2的剖视概念示意图，以及图1D为沿图1A中的线Y-Y的剖视概念示意图。
为形成图1A-图1D中所示的结构，可使用不同的制程。在一些示例方法中，将底层100(原位形成或经后续掺杂的半导体材料)图案化为如图1D中所示的鳍片110。如图1C中所示，这形成“第一”层或衬底结构(例如，鳍片110)。要注意，尽管该第一层可为鳍片结构，但它不需要是，且在一些实施中，该第一层可简单地为平面层。因此，鳍片110在本文中有时被简单通称为层或衬底。如图1D中所见，绝缘体或隔离材料104(例如，浅沟槽隔离STI)可经形成及高度降低以显露鳍片110。
当图案化这里的任意材料时，可以任意已知的方式生长或沉积要被图案化的该材料，且可在该材料上方形成图案化层(例如有机光阻)。可将该图案化层(阻剂)暴露于以光曝光图案设置的某种模式的光辐射(例如，图案化曝光、激光曝光等)，接着使用化学剂显影该阻剂。此制程改变暴露于光的该阻剂部分的物理特性。接着，可冲洗掉该阻剂的一部分，使该阻剂的其它部分保护要被图案化的该材料(冲洗掉该阻剂的哪部分取决于该阻剂是负型阻剂(保留受照部分)还是正型阻剂(冲洗掉受照部分))。接着，执行材料移除制程(例如，湿式蚀刻、非等向性蚀刻(取向依赖蚀刻)、等离子体蚀刻(反应离子蚀刻(reactive ionetching；RIE)等))，以移除要被图案化的该阻剂下方的该材料的未受保护部分。随后，移除该阻剂，使下方材料依据该光曝光图案(或其负型图像)被图案化。
图2A-图2D显示与上述图1A-图1D相同的视图。如图2A-图2D中所示，此类制程通过使用掩膜109形成延伸于鳍片层110的沟道区102(例如，见图2C)上方的牺牲栅极106(通常被称为“伪”栅极)；在一个例子中，牺牲栅极106可为多晶硅。此外，在牺牲栅极106上形成第一侧壁绝缘体108或第一侧间隙壁(其可为例如低k材料)。此类方法在牺牲栅极106的相对侧上的鳍片层110中及/或上(通过使用例如外延生长或注入制程)形成源极/漏极结构118。源极/漏极结构118通过第一侧壁绝缘体108在外延生长制程中自对准。
出于本文中的目的，“侧间隙壁”是结构，通常通过沉积或生长共形绝缘层(例如任意上述绝缘体)并接着执行定向蚀刻制程(非等向性)，以与自垂直表面移除材料的速率相比较大的速率自水平表面蚀刻材料，从而保留沿结构的垂直侧壁的绝缘材料来形成。保留于垂直侧壁上的此材料被称为侧间隙壁。
图3A-图3D显示与上述的图1A-图1D相同的相关视图。如图3A-
图3D中所示，此类制程在第一侧壁绝缘体108上形成第二侧壁绝缘体124(例如，第二侧间隙壁)。此类第二侧壁绝缘体124可为共形绝缘体层(例如，在一个例子中，其可为接触蚀刻停止层(contact etch stop layer；CESL)如氮化物等)并因此，第二侧壁绝缘体124初始也在该源极/漏极区上及隔离材料104上形成为薄层(在下述后续制程中移除)。要注意，第一侧壁绝缘体108与第二侧壁绝缘体124可为不同的材料，它们可具有不同的介电常数。
在形成第二侧壁绝缘体124以后，这些制程形成下绝缘体层112(例如，氧化物，如二氧化硅)。因此，下绝缘体层112可接触第二侧壁绝缘体124，并位于牺牲栅极106之间。通过使用例如CMP，可将所有元件平坦化至如图3A-图3D中所示的相同高度。
图4A-图4D显示与上述的图1A-图1D相同的视图。在图4A-图4D中，这些方法将牺牲栅极106及第一侧壁绝缘体108的高度从自层110的顶部的第一高度(H1)降低至自层110的顶部的降低的高度(H2)，在制程中将下绝缘体层112及第二侧壁绝缘体124保留于该第一高度(H1)。在一个例子中，可首先执行仅攻击牺牲栅极106(例如，仅攻击多晶硅)的选择性反应离子蚀刻(RIE)制程，接着执行仅移除第一侧壁绝缘体108(例如，仅攻击二氧化硅)的RIE制程。
选择性材料移除制程首先自可相对彼此被选择性移除的材料形成元件，并接着后续应用移除技术，以移除一种材料，同时使其它材料基本不受影响。尽管本文中提到一些材料选择及选择性移除技术，但本领域的普通技术人员将理解，可使用不同的材料，只要此类材料可相对彼此被选择性移除即可。要注意，尽管一些选择性材料移除制程可部分移除相邻材料(或形成圆化)，这些可能未被完全显示于附图中，以简化附图并因此更清楚地示例本文中的概念。
图5A-图5D显示与上述的图1A-图1D相同的视图。如图5A-图5D中所示，本文中的方法移除牺牲栅极106(但将第一及第二侧壁绝缘体108、124及绝缘体112保留于原位)。再次，可使用仅攻击牺牲栅极106的材料(例如，仅攻击多晶硅)的选择性材料移除制程，以移除牺牲栅极106。栅极绝缘体116(例如，栅极氧化物)可被沉积或生长(直接接触)于鳍片层110的沟道区102上。
沉积一种或多种导体(例如，不同功函数导体层，该所有层通过元件120被共同显示于附图中)，以填充牺牲栅极106先前所处的第一与第二侧壁绝缘体108、124之间的空间。此外，元件120可代表不同功函数金属，例如在p型及n型晶体管中所使用的p型及n型功函数金属。因此，如图5A-图5D中所示，此制程用第一导体替代牺牲栅极106，以形成本文中所称的栅极结构的下部，在制程中初始形成栅极结构的下部120(例如，高k/金属栅极(high-k/metal gate；HKMG))至第一高度(H1)并完全覆盖降低的高度(H2)的第一侧壁绝缘体的侧面及顶部。在此类制程以后可移除多余的HKMG材料。
此外，图5C显示此制程形成鳍式场效应晶体管(FinFET)103，其包括沟道区102、位于沟道区102的侧面上的源极/漏极区118、栅极氧化物(绝缘体)116、以及栅极(导体)120。如上所述，在栅极结构的下部120中的电压改变沟道102的导电性，以允许或防止电流在源极/漏极118之间流动。通过此类制程，在本文中的各鳍片110上形成多个FinFET 103。
图6A-图6D显示与上述的图1A-图1D相同的视图。如图6A-图6D中所示，本文中的方法图案化掩膜138并执行选择性材料移除(例如，蚀刻)，以移除位于该栅极结构的下部120之间的下绝缘体层112的部分。此制程还可为定向的并移除位于水平表面上的第二侧壁绝缘体124的部分(同时保留位于第一侧壁绝缘体108上的第二侧壁绝缘体24的大部分)，但此制程是选择性的，以便不移除源极/漏极结构118。要注意，如图6A-图6D中所示，当蚀刻掉下绝缘体层112的部分时，可稍微降低该上部的厚度或第二侧壁绝缘体112的高度。此外，当栅极结构的下部120(具有高度H1)完全覆盖第一侧壁绝缘体108的侧面及顶部(具有高度H2)时，执行此选择性材料移除制程，以防止第一侧壁绝缘体108被移除，即使第二侧壁绝缘体124的一部分被移除。因此，图6A-图6D中所示的制程暴露源极/漏极结构118的其中一者(如掩膜138所允许的那样)，但基本避免移除第一或第二侧壁绝缘体108、124或源极/漏极结构118。
图7A-图7D显示与上述的图1A-图1D相同的视图。如图7A-图7D中所示，本文中的方法用牺牲材料132(例如光聚合层(optical polymerization layer；OPL))填充先前被该下绝缘体层所占据的空间，可后续选择性移除该牺牲材料。因此，如图7A-图7D中所示，本文中的方法在该栅极结构的下部120之间的源极/漏极结构118的其中暴露一者上形成本文中所称的牺牲源极/漏极接触结构132至该第一高度(H1)(可能在CMP或类似制程以后)。
图8A-图8D显示与上述的图1A-图1D相同的视图。如图8A-图8D中所示，本文中的方法将该栅极结构的下部120的高度降低至自鳍片110的第三高度(H3)，该第三高度小于该降低的高度(H2)，以形成第一凹部144。通过使用反应剂执行此凹入制程，该反应剂仅攻击栅极结构的下部120(第一导体)及第二侧壁绝缘体124的材料，而不攻击第一侧壁绝缘体108的材料，且不攻击牺牲源极/漏极接触结构132的材料。
图9A-图9D显示与上述的图1A-图1D相同的视图。如图9A-图9D中所示，本文中的方法还在第一凹部144中形成上侧间隙壁134(例如，氮化物，如氮化硅)。上面讨论侧间隙壁形成，且通过此类制程，上侧间隙壁134接触牺牲源极/漏极接触结构132的侧壁、该栅极结构的下部120、第一侧壁绝缘体108、以及第二侧壁绝缘体124。如图9A-图9D中所示，在该侧间隙壁形成制程中回蚀刻上侧间隙壁134，以仅部分地填充第一凹部144，且上侧间隙壁134延伸于第三高度(H3)与第二高度(H2)之间，以填充该第一凹部。上侧间隙壁134可为与第一及第二侧壁绝缘体108、124不同的绝缘体材料。
图10A-图10D显示与上述的图1A-图1D相同的视图。如图10A-图10D中所示，本文中的方法移除牺牲源极/漏极接触结构132，以留下第二凹部146。再次，此类选择性材料移除制程使用仅攻击牺牲源极/漏极接触结构132的材料的反应剂(例如，如OPL灰)。
图11A-图11D显示与上述的图1A-图1D相同的视图。如图11A-图11D中所示，本文中的方法沉积一个或多个共形导体层，以在第一凹部144中且同时在上侧间隙壁134之间的第二凹部146中形成第二导体。可移除多余导体(例如，CMP等)。该第二导体也可由具有不同功函数的多个导体层形成，或者，该第二导体可为单种导体材料(例如，钨)。此制程同时形成该栅极结构的上部142以及下源极/漏极接触140。要注意，在形成该栅极结构的上部142之前，此制程不需要斜切该栅极结构的下部120，从而避免会减慢当前制程的传统斜切步骤。
在图12A-图12D中，沉积或生长层间介电质(interlayer dielectric；ILD)150，并通过ILD 150图案化过孔开口(via opening)。随后，用导体填充此类过孔开口，以形成过孔接触，包括源极/漏极过孔接触152(图11A及图11B)以及栅极过孔接触154(图11A及图11C)。要注意，此制程避免传统的金属凹入、栅极覆盖沉积、以及栅极覆盖CMP制程，通过不执行这些步骤，此制程比传统制程更有效且更不容易出错。
图13是与沿图12A中的剖面X2-X2的图12C中所示的视图类似的视图。图13显示前述制程仍允许形成经适当尺寸设定的栅极，即使该栅极的下部120的高度(自鳍片110)不一致，此时，较长的上部142顾及任意高度变化，如图13的区域162中所示。换句话说，即使第一凹部144因该栅极结构的下部120的不一致高度而具有不规则的深度/尺寸，该栅极结构的上部142的共形形成也顾及所有此类不规则。此外，图13中的区域160显示即使在下源极/漏极接触140与上源极/漏极接触152之间存在一些未对准，由于上侧间隙壁134与第一及第二侧壁绝缘体108、124所提供的额外空间及绝缘，也不会在上源极/漏极接触152与栅极结构120、142之间形成短路(不良电性连接)。
因此，图12A-图13显示此类制程产生包括(除其它组件以外)沿第一方向图案化的自下层100延伸的平行的鳍片110以及沿垂直于该第一方向的第二方向与鳍片110相交的平行的栅极结构120、142的示例结构。这里，该第一方向与第二方向都平行于鳍片110的顶部表面(例如，见图1A)。该栅极结构具有包括与鳍片110相邻的第一导体的下部120，以及包括在鳍片110的远侧的第二导体的上部142(接触下部120)。
该栅极结构的下部120可具有自该鳍片的不规则高度，如图13中所示。此外，栅极结构的下部120沿该第一方向宽于该栅极结构的上部142，因为该上侧间隙壁134使第一凹部144变窄(例如，见图10C)，从而使该栅极结构的上部142较窄。栅极结构的下部120(第一导体)与该栅极结构的上部142(第二导体)可彼此不同，且分别可由许多不同的材料层组成，例如具有不同功函数的多个导体层。在一些实施中，该栅极结构的下部120包括功函数金属(work function metal；WFM)，而该栅极结构的上部142为单个导体(例如，钨等)。
此外，栅极绝缘体116位于(接触)该栅极结构的下部120与鳍片110之间，且外延源极/漏极结构118位于(接触)栅极结构120、142之间的鳍片110上。另外，下源极/漏极接触140位于(接触)源极/漏极结构118上。此类下源极/漏极接触140也位于栅极结构120、142之间。
多个侧壁绝缘体层108、124位于栅极结构120、142与下源极/漏极接触140之间，与该栅极结构的上部142及下部120相邻。多个绝缘体层108、124彼此接触且可由具有不同介电常数的不同绝缘体层制成。设置额外的上侧间隙壁134以接触并位于该栅极结构的上部142与多个绝缘体层108、124之间。上侧间隙壁134仅与该栅极结构的上部142相邻且不与该栅极结构的下部120相邻。上侧间隙壁134可为与多个绝缘体层108、124不同的绝缘体材料。
此外，在下源极/漏极接触140及栅极结构120、142的上部142上设置(接触)层间介电质。栅极接触154延伸穿过该层间介电质并接触该栅极结构的上部142。另外，上源极/漏极接触152延伸穿过该层间介电质并接触下源极/漏极接触140。该栅极结构的上部142与下源极/漏极接触140可为相同的材料。
如图14中的流程图所示，本文中的示例方法图案化层，以形成自该层延伸的平行的鳍片，其中，在项目202中，沿第一方向/取向图案化该鳍片。另外，在项目204中，此类方法图案化沿垂直于该第一方向的第二方向与该鳍片相交的平行的牺牲栅极。在项目206中，这些方法在该牺牲栅极的侧壁上形成第一侧壁绝缘体。在项目208中，本文中的方法在该牺牲栅极之间的该鳍片上外延生长源极/漏极结构。在项目210中，这些方法在该第一侧壁绝缘体上形成第二侧壁绝缘体，并在该牺牲栅极之间的该第二侧壁绝缘体上形成下绝缘体层。
如项目212中所示，此类方法将该牺牲栅极及该第一侧壁绝缘体的高度从自该鳍片的第一高度降低至自该鳍片的降低的高度，在制程中将该下绝缘体层及该第二侧壁绝缘体保留于该第一高度。此外，如项目214中所示，这些方法用第一导体替代该牺牲栅极，以形成栅极结构的下部，在制程中形成栅极结构的该下部至该第一高度并覆盖该第一侧壁绝缘体的侧面及顶部。
此外，如项目216中所示，这些方法移除该下绝缘体层的部分以及该第二侧壁绝缘体的相应水平部分，而栅极结构的该下部覆盖该第一侧壁绝缘体。在项目216中，此制程暴露该源极/漏极结构的其中一者，但避免自该第一侧壁绝缘体或该栅极结构的该下部移除该第二侧壁绝缘体。在项目218中，此类方法在该栅极结构的该下部之间的该源极/漏极结构的其中暴露一者上形成牺牲源极/漏极接触结构至该第一高度。在项目220中，这些方法将该栅极结构的该下部的高度降低至小于该降低的高度(至自该鳍片的第三高度)，以形成第一凹部。
在项目222中，这些方法还在该牺牲源极/漏极接触结构的侧壁、该栅极结构的该下部、该第一侧壁绝缘体、以及该第二侧壁绝缘体上的该第一凹部中形成上侧间隙壁。该上侧间隙壁部分地填充该第一凹部，且该上侧间隙壁延伸该第一凹部的深度。
在项目224中，本文中的方法移除该牺牲源极/漏极接触结构，以留下第二凹部(但避免该栅极结构的该下部的任意斜切，如上所述)。在项目226中，此类方法在该上侧间隙壁之间的该第一凹部中以及在该第二凹部中形成第二导体，以形成该栅极的上部及源极/漏极接触结构(同时避免SAC覆盖形成及CMP，如上所述)。该上侧间隙壁可为与该第一侧壁绝缘体及该第二侧壁绝缘体不同的绝缘体材料，且该第一侧壁绝缘体与该第二侧壁绝缘体具有不同的介电常数。
此外，如项目228中所示，层间介电质被设置于(接触)下源极/漏极接触、该栅极结构的该上部、以及该下绝缘体上(接触)上。在项目230中，通过该ILD形成接触，其中，栅极接触延伸穿过该层间介电质并接触该栅极结构的该上部。另外，在项目230中，形成上源极/漏极接触，以延伸穿过该层间介电质并接触该下源极/漏极接触。另外，该栅极结构的该上部与该下源极/漏极接触可为相同材料。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制上述实施例。除非上下文中另外明确指出，否则本文中所使用的单数形式“一”、“一个”以及“该”也意图包括复数形式。而且，本文中所使用的术语如“右”、“左”、“垂直”、“水平”、“顶部”、“底部”、“上”、“下”、“上方”、“下方”、“平行”、“直立”等意图说明当它们以附图中取向并显示时的相对位置(除非另外指出)，且术语如“接触”、“直接接触”、“毗邻”、“直接相邻”、“紧邻”等意图表示至少一个元件物理接触另一个元件(没有其它元件隔开所述元件)。本文中所使用的术语“横向”说明当元件以附图中取向并显示时这些元件的相对位置，尤其表示一个元件位于另一个元件的侧边而不是另一个元件的上方或下方。例如，一个元件横向邻近另一个元件将在该另一个元件旁边，一个元件横向紧邻另一个元件将直接在该另一个元件旁边，以及一个元件横向围绕另一个元件将邻近并环绕该另一个元件的外侧壁。
本文中的实施例可用于各种电子应用，包括但不限于高级传感器、存储器/数据储存、半导体、微处理器以及其它应用。制造者可以原始晶圆形式(也就是，作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得器件及结构，例如集成电路(IC)芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，接着将该芯片与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品例如母板的部分，或者作为(b)最终产品的部分。该最终产品可为包括集成电路芯片的任意产品，涉及范围从玩具及其它低端应用直至具有显示器、键盘或其它输入器件以及中央处理器的先进电脑产品。
对本实施例所作的说明是出于示例及说明目的，而非意图详尽无遗或限于所揭示形式的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离本文中的实施例的范围及精神。该实施例经选择及说明以最佳解释此类实施例的原理，及实际应用，以及使本领域的其他普通技术人员能够理解具有适于所考虑的特定应用的各种变更的各种实施例。
尽管上面仅结合有限数目的实施例来详细说明，但很容易理解，本文中的实施例不限于这些揭示。相反，可修改本文中的元件以包含此前未说明但符合本文的精神及范围的任意数目的变化、更改、替代或等同布置。此外，尽管已说明各种实施例，但应当理解，本文中的实施例可仅被某些所述实施例包括。相应地，所附的权利要求将不被视为被上述说明限制。除非特别说明，否则提及单数元件并不意图意味着“一个且仅一个”，而是“一个或多个”。本申请中所述的各种实施例的元件的所有结构及功能等同(其为本领域的普通技术人员已知的或后来逐渐知道的)通过引用明确包含于此并意图被本申请包括。因此，应当理解，在所揭示的特定实施例中可作变更，其落入如所附权利要求所概述的上述范围内。

Claims (20)

1.一种集成电路装置，包括：
平行的鳍片，自层延伸，其中，沿第一方向图案化该鳍片；
平行的栅极结构，沿垂直于该第一方向的第二方向与该鳍片相交，其中，该栅极结构具有与该鳍片相邻的下部以及在该鳍片的远侧的上部；
源极/漏极结构，位于该栅极结构之间的该鳍片上；
源极/漏极接触，位于该源极/漏极结构上；
多个绝缘体层，位于该栅极结构与该源极/漏极接触之间；以及
上侧间隙壁，位于该栅极结构的该上部与该多个绝缘体层之间。
2.如权利要求1所述的集成电路装置，其中，该上侧间隙壁仅与该栅极结构的该上部相邻，且不与该栅极结构的该下部相邻。
3.如权利要求1所述的集成电路装置，其中，该多个绝缘体层与该栅极结构的该上部及该下部相邻。
4.如权利要求1所述的集成电路装置，其中，该栅极结构的下部沿该第一方向宽于该栅极结构的该上部。
5.如权利要求1所述的集成电路装置，其中，该上侧间隙壁是与该多个绝缘体层不同的绝缘体材料。
6.如权利要求1所述的集成电路装置，其中，该多个绝缘体层包括具有不同介电常数的两个不同绝缘体层。
7.如权利要求1所述的集成电路装置，其中，该源极/漏极接触与该栅极结构的该上部为相同材料。
8.一种集成电路装置，包括：
平行的鳍片，自层延伸，其中，沿第一方向图案化该鳍片；
平行的栅极结构，沿垂直于该第一方向的第二方向与该鳍片相交，其中，该栅极结构具有包括与该鳍片相邻的第一导体的下部以及包括在该鳍片的远侧的第二导体的上部，以及其中，该第一导体与该第二导体为不同材料；
栅极绝缘体，位于该栅极结构的该下部与该鳍片之间；
外延源极/漏极结构，位于该栅极结构之间的该鳍片上；
下源极/漏极接触，位于该源极/漏极结构上；
多个绝缘体层，位于该栅极结构与该下源极/漏极接触之间；
上侧间隙壁，位于该栅极结构的该上部与该多个绝缘体层之间；
层间介电质，位于该下源极/漏极接触及该栅极结构的该上部上；
栅极接触，延伸穿过该层间介电质并接触该栅极结构的该上部；以及
上源极/漏极接触，延伸穿过该层间介电质并接触该下源极/漏极接触。
9.如权利要求8所述的集成电路装置，其中，该上侧间隙壁仅与该栅极结构的该上部相邻，且不与该栅极结构的该下部相邻。
10.如权利要求8所述的集成电路装置，其中，该多个绝缘体层与该栅极结构的该上部及该下部相邻。
11.如权利要求8所述的集成电路装置，其中，该栅极结构的下部沿该第一方向宽于该栅极结构的该上部。
12.如权利要求8所述的集成电路装置，其中，该上侧间隙壁是与该多个绝缘体层不同的绝缘体材料。
13.如权利要求8所述的集成电路装置，其中，该多个绝缘体层包括具有不同介电常数的两个不同绝缘体层。
14.如权利要求8所述的集成电路装置，其中，该栅极结构自该鳍片具有不规则的高度。
15.一种方法，包括：
在牺牲栅极的侧壁上形成第一侧壁绝缘体；
在该牺牲栅极之间的鳍片上外延生长源极/漏极结构；
在该第一侧壁绝缘体上形成第二侧壁绝缘体；
在该牺牲栅极之间的该第二侧壁绝缘体上形成下绝缘体层；
将该牺牲栅极及该第一侧壁绝缘体的高度从第一高度降低至降低的高度，在制程中将该下绝缘体层及该第二侧壁绝缘体保留于该第一高度；
用第一导体替代该牺牲栅极，以形成栅极结构的下部，在制程中形成该栅极结构的下部至该第一高度并覆盖该第一侧壁绝缘体；
移除该下绝缘体层的部分，而该栅极结构的下部覆盖该第一侧壁绝缘体，在制程中暴露该源极/漏极结构的其中一者；
在该栅极结构的该下部之间的该源极/漏极结构的其中暴露一者上形成牺牲源极/漏极接触结构至该第一高度；
将该栅极结构的该下部的高度降低至小于该降低的高度的第三高度，以形成第一凹部；
在该牺牲源极/漏极接触结构的侧壁、该栅极结构的该下部、该第一侧壁绝缘体及该第二侧壁绝缘体上的该第一凹部中形成上侧间隙壁；
移除该牺牲源极/漏极接触结构，以留下第二凹部；以及
在该上侧间隙壁之间的该第一凹部中及在该第二凹部中形成第二导体，以形成该栅极结构的上部，并在该牺牲源极/漏极接触结构所处的位置形成源极/漏极接触结构。
16.如权利要求15所述的方法，其中，该上侧间隙壁部分地填充该第一凹部。
17.如权利要求15所述的方法，其中，该上侧间隙壁延伸该第一凹部的深度。
18.如权利要求15所述的方法，其中，所述移除该下绝缘体层的部分避免自该第一侧壁绝缘体移除该第二侧壁绝缘体。
19.如权利要求15所述的方法，其中，该上侧间隙壁是与该第一侧壁绝缘体及该第二侧壁绝缘体不同的绝缘体材料。
20.如权利要求15所述的方法，其中，该第一侧壁绝缘体与该第二侧壁绝缘体具有不同的介电常数。
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