CN109273428B - 集成电路的预金属化电介质或层间电介质层中的接触结构 - Google Patents

集成电路的预金属化电介质或层间电介质层中的接触结构 Download PDF

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CN109273428B
CN109273428B CN201811384759.9A CN201811384759A CN109273428B CN 109273428 B CN109273428 B CN 109273428B CN 201811384759 A CN201811384759 A CN 201811384759A CN 109273428 B CN109273428 B CN 109273428B
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CN109273428A (zh
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J·H·张
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STMicroelectronics lnc USA
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Abstract

一种集成电路包括源漏区、与该源漏区相邻的沟道区、在该沟道区之上延伸的栅极结构以及在该栅极结构的一侧上并且在该源漏区之上延伸的侧壁间隔物。提供了与该侧壁间隔物接触并且具有顶表面的电介质层。该栅极结构包括栅极电极和从该栅极电极作为突起延伸到达该顶表面的栅极接触。该栅极电极的侧表面与栅极接触的侧表面相互对准。定位在该栅极电极与该沟道区之间的用于晶体管的栅极电介质层在该栅极电极与该侧壁间隔物之间延伸并且进一步在该栅极接触与该侧壁间隔物之间延伸。

Description

集成电路的预金属化电介质或层间电介质层中的接触结构
本申请是于2015年12月30日提出的、申请号为201511021020.8、发明名称为“集成电路的预金属化电介质或层间电介质层中的接触结构”的中国发明专利申请的分案申请。
技术领域
本发明涉及集成电路，并且具体地涉及集成电路中的预金属化电介质(PMD)或层间电介质(ILD)层的金属填充接触的形成，其目的为连接晶体管的栅极区、源极区和漏极区。
背景技术
现在参照图1A和图1B，图1A和图1B示出了常规的金属氧化物半导体(MOS)场效应晶体管(FET)10器件的总配置。图1A和图1B是在沿晶体管栅极的宽度的不同位置处以垂直于栅宽的方向所截取的平行横截面。衬底12支撑晶体管。在这个实例中，该衬底是绝缘体上硅衬底12类型的，该衬底包括衬底层14、掩埋氧化物(BOX)层16和半导体层18。用于晶体管器件的有源区20由穿透层18的周向包围的浅沟槽隔离22来限定。在有源区20之内，层18被划分为已掺杂有第一导电类型掺杂物的多个沟道区30、已掺杂有第二导电类型掺杂物的多个源极区32(各自在一侧上邻近沟道区30)以及也已掺杂有第二导电类型掺杂物多个漏极区34(各自在与源极区32的相对侧邻近沟道区30)。其中，当MOSFET 10器件是p沟道类型时，第一导电类型掺杂物是p型的并且第二导电类型是n型的。相反，当MOSFET器件是n沟道类型时，第一导电类型掺杂物是n型的并且第二导电类型是p型的。在沟道区30上方提供多个栅叠层36。每个栅叠层36典型地包括栅极电介质38、(例如金属和/或多晶硅材料的)栅极电极40和由绝缘材料(例如氮化硅(SiN))制成的多个侧壁间隔物42，这些侧壁间隔物被沉积在栅极电介质38和栅极电极40的各侧上以及该栅极电极的顶部上。在该衬底和该栅叠层上方提供层间电介质(ILD)或预金属化电介质(PMD)层46。层46的顶表面48以化学机械抛光(CMP)工艺来处理以限定平坦表面。典型地由钨形成的金属接触集50从顶表面48穿过在多个金属填充接触开口中的ILD/PMD层46，以与源极区32和漏极区34(在图1A的横截面中示出)以及栅极电极40(在图1B的横截面中示出)电接触。然后在ILD/PMD层46上方提供第一金属化层M1，其中第一金属化层M1包括形成在金属填充通孔和/或沟槽开口中的多条金属线54，这些金属线与接触50接触并且被平坦化的电介质材料层56围绕。
由于在集成电路器件中的特征尺寸持续缩小，在中段制程(MOL)互连中提供源极接触、漏极接触和栅极接触将变得更复杂且具有挑战性。这种情况的原因有很多。例如，可能需要将栅极接触从有源区22(例如在如图1B中所示的周边隔离22之上)去除以便避免在栅极接触与源漏区的沟槽硅化物之间的短路。这是不利的，因为其导致芯片面积的增加。为了解决这个问题，集成电路设计者正朝着合并鳍结构和共用源漏结构迈进。然而由于减少的接触面积在源漏区增加了接触电阻，伴随这种技术具有显著的缺点(如在图1A中以参考号60总体性示出的)。栅极与栅极接触的未对准是另一个问题(参见图1B参考号62处)，并且这个问题可能导致栅极到源漏接触的短路的问题。
在本领域中相应地需要到晶体管集成电路的源极区、漏极区和栅极区的改善的MOL互连。
发明内容
上述的和其他的问题可以通过MOL互连来解决，该MOL互连使用：自底向上形成栅极接触以便避免在栅极与栅极接触之间的未对准以及自顶向下形成具有足够以减少接触电阻并且避免短路问题的尺寸的源漏接触。这些栅极接触通孔优选地由高K材料和低K材料保护以便改善对于高密度集成的可靠性。
在实施例中，一种集成电路包括：源漏区；与该源漏区邻近的沟道区；在该沟道区之上延伸的栅极结构；在该栅极结构的一侧上并且在该源漏区之上延伸的侧壁间隔物；以及与该侧壁间隔物接触并且具有顶表面的电介质层。该栅极结构包括：栅极电极；从该栅极电极延伸至该顶表面的栅极接触；以及在该栅极接触与该沟道区之间并且在该栅极电极与该侧壁间隔物之间延伸并且进一步在该栅极接触与该侧壁间隔物之间延伸的栅极电介质层。
在实施例中，一种集成电路包括：源漏区；与该源漏区邻近的沟道区；在该沟道区之上延伸的栅极结构；在该栅极结构的一侧上并且在该源漏区之上延伸的侧壁间隔物；以及与该侧壁间隔物接触并且具有顶表面的电介质层。该栅极结构包括：栅极电极；从该栅极电极延伸至该顶表面的栅极接触；其中，该栅极电极的侧表面与该栅极接触的侧表面相互对准并且平行于该侧壁间隔物的内表面延伸。
在实施例中，一种方法包括：形成在沟道区之上延伸的假栅极结构，所述假栅极结构包括假栅极电极和在该假栅极电极的每一侧上的多个侧壁间隔物，这些侧壁间隔物在与该沟道区相邻的源漏区之上延伸；去除该假栅极电极以在这些侧壁间隔物之间形成开口；在该开口之内形成替换金属栅极，所述替换金属栅极包括电介质内衬和金属部分；对该替换金属栅极的期望有栅极接触的一部分进行遮蔽掩模；使该替换金属栅极在除被遮蔽掩模的该部分处凹陷，从而在替换金属栅极凹陷之处形成栅极电极并且在该替换金属栅极被遮蔽掩模之处形成所述栅极接触；并且提供电介质层。
附图说明
为了更好地理解实施例，现在将仅以示例方式参考附图，在附图中：
图1A和图1B展示了现有技术的MOSFET器件的结构；并且
图2至图24展示了用于制造接触的多个工艺步骤。
所提供的示图不一定按比例绘制。
具体实施方式
现在参照图2至图24，这些图展示了用于制造接触的多个工艺步骤。
参照图2，衬底112包括由周向包围的浅沟槽隔离122界定的有源区120。衬底112例如可以是绝缘体上硅(SOI)类型的，该衬底包括衬底层114、掩埋氧化物(BOX)层116和半导体层118。在有源区120之内，层118被划分为已掺杂有第一导电类型掺杂物的多个沟道区130、已掺杂有第二导电类型掺杂物的多个源极区132(各自在一侧上邻近沟道区130)以及也已掺杂有第二导电类型掺杂物多个漏极区134(各自在与源极区132的相对侧邻近沟道区130)。当与形成p沟道类型晶体管相结合时，该第一导电类型掺杂物是p型的并且该第二导电类型是n型的。相反，当与形成n沟道类型晶体管相结合时，该第一导电类型掺杂物是n型的并且该第二导电类型是p型的。
在沟道区130上方提供多个假栅叠层136。每个假栅叠层136典型地包括牺牲性多晶硅栅极电极140和由例如氮化硅(SiN)的绝缘材料制成的多个侧壁间隔物142，这些侧壁间隔物被沉积在牺牲性栅极电极140的各侧上。牺牲性多晶硅栅极电极140例如可以具有5nm至30nm的长度(具有根据本应用的任何合适的宽度，例如10nm至100nm)并且侧壁间隔物142例如可以具有4nm至20nm的厚度。这些假栅叠层136的间距可以包括40nm至50nm。在衬底上方在假栅叠层136的每一侧上提供绝缘层146。层146的顶表面148用化学机械抛光(CMP)工艺进行加工以限定平坦表面，该表面暴露牺牲性多晶硅栅极电极140的顶表面147。这在现有技术中被称为多晶开口化学机械抛光(POC)。牺牲性多晶硅栅极电极140的高度h(并且因此还有层146和侧壁间隔物142的高度)被选择为使得基本上等于集成电路的层间电介质(ILD)或预金属化电介质(PMD)区的所期望的高度。高度h例如可以是120nm至140nm。
在FinFET实施例中，对半导体层118图案化以形成多个平行的鳍，其中每个鳍都包括源极区、沟道区和漏极区。每个鳍都可以具有10nm至30nm的高度以及6nm至10nm的宽度，其中这些平行的鳍中的每一个鳍之间的间距为25nm至40nm。在这种配置中，该多个假栅叠层136垂直于这些鳍的长度以本领域已知的在三侧上跨坐在每个鳍之上的配置延伸。图2的横截面因此展示了沿该多个鳍中的仅一个鳍的长度截取的横截面，其他鳍中的每个鳍都具有类似的横截面配置。
然后执行蚀刻工艺(例如干法凹陷蚀刻30nm(20s)+DHF(45s)+SC1(300s)+65℃的热NH4OH)以选择性地去除牺牲性多晶硅栅极电极140并在侧壁间隔物142之间留下开口146。结果在图3中示出。
然后在开口146之内进行高K电介质材料的保形沉积以形成电介质内衬150。高K电介质材料例如可以包括使用原子层沉积工艺来沉积的具有2nm至10nm厚度的氧化铪(HfO2)。内衬150被沉积在开口146与栅极区130接触的底部处以限定晶体管的栅极电介质。然后在开口146之内进行金属材料的保形沉积以形成金属内衬152。该金属材料例如可以包括使用原子层沉积工艺来沉积的具有2nm至8nm厚度的TiN/TiC。这个金属内衬152例如可以作为势垒层。然后在开口146之内进行功函数材料的保形沉积以形成功函数层154。功函数材料例如可以包括使用原子层沉积工艺来沉积的具有总厚度为5nm至10nm的多层TiN、TiC和TiN(例如1nm TiN、3nm TiC和1nm TiN))。提供功函数材料以控制晶体管的工作阈值。然后用金属填充材料来填充每个开口146的剩余空部分。该金属填充物例如可以包括使用热化学气相淀积工艺来沉积的钨。金属填充物形成晶体管的栅极电极。使用化学机械抛光(CMP)工艺来去除内衬150和152、层154以及填充物156的多余部分。上述工艺类似于本领域已知的替换金属栅极工艺，并且因此内衬150和152、层154以及填充物156被共同地称为替换栅极结构158。结果在图4中示出。
然后在替换栅极结构158的期望栅极接触的一部分之上形成遮蔽掩模160。结果在图5中示出(该图是图4和图6的正交横截面，其中，图6是与图4平行的横截面)。可以使用本领域已知的任何合适的沉积和光刻图案化工艺以形成遮蔽掩模160。遮蔽掩模的尺寸例如可以是：长5nm至10nm并且宽10nm至30nm。
然后执行选择性反应离子蚀刻(RIE)以使替换栅极结构158没有被遮蔽掩模160保护的内衬150和152、层154以及填充物156凹陷。这种蚀刻不材料性地攻击侧壁间隔物142或层146。结果在图7至图9中示出以在侧壁间隔物142之间产生多个开口166并且留下替换栅极结构158位于遮蔽掩模160下方的一部分，以用替换栅极结构158的形成替换金属栅极172的凹陷部分来提供栅极电极接触170。
具体参照图9，将注意到的是，替换栅极结构158的栅极电极接触170部分的侧壁与替换栅极结构158的替换金属栅极172部分的侧壁在所有高度h内相互对准并且由侧壁间隔物142的内表面限定(即，替换栅极结构158的外表面和侧壁间隔物142的内表面相邻且平行)。因此，至少在图9的横截面中，栅极电极接触170部分与替换金属栅极172部分自对准。这种结果是因为栅极电极接触170是如以上所描述的通过对每个开口146进行填充而自底向上来制造的。将进一步注意到的是，高K电介质层150(也是在替换金属栅极172与沟道区之间的栅极电介质)被提供为在替换金属栅极172的金属部分与侧壁间隔物142之间延伸并且进一步在栅极电极接触170的金属部分与侧壁间隔物142之间延伸。
然后对绝缘填充材料进行沉积以填充开口166并且形成帽盖176和覆盖层178。该绝缘填充材料例如可以包括氮化硅(SiN)或低K电介质材料(例如SiOCN或SiBCN)。使用化学机械抛光(CMP)工艺以去除绝缘填充材料的多余部分，其中在遮蔽掩模160的顶部处停止抛光。结果在图10至图11中示出。由于使用低K电介质材料，将注意到的是，在高K电介质之外提供低K电介质，从而使得栅极电极接触170由多种电介质材料包围(参见图9和图11)。
执行非选择性反应离子蚀刻(RIE)以使未被掩模160保护的层146和侧壁间隔物142凹陷。该凹陷被制成深度为d，该深度没有到达替换栅极结构158的形成替换金属栅极172的凹陷部分的顶部。然后使用气体团簇离子束(GCIB)工艺来确保凹陷深度的一致性。结果在图12至图14中示出。该深度例如可以是60nm至80nm。将注意到的是，如在图14的横截面中所示，在栅极电极接触170的每一侧上留下了侧壁间隔物142的薄部分142’(其厚度例如为3nm至10nm)。
然后使电介质材料进行沉积以覆盖之前形成的结构。这种沉积例如可以通过使用化学气相淀积工艺来进行。电介质材料可以包括例如HDP氧化物。使用化学机械抛光(CMP)工艺以去除电介质材料沉积的多余部分，其中在遮蔽掩模160的顶部处停止抛光。结果在图15至图17中示出以形成层间电介质(ILD)或预金属化电介质(PMD)层146’。
使用公知的光刻图案化技术，在ILD/PMD层146’的顶表面182上形成蚀刻掩模180，该蚀刻掩模在用于源极接触和漏极接触的位置处具有掩模开口。结果在图18中示出。
然后穿过这些掩模开口来执行反应离子蚀刻(RIE)以形成穿过IDL/PMD层146’延伸至到达源极区和漏极区132和134的上表面的多个自对准的接触开口184。结果在图19中示出。然后可以去除蚀刻掩模180。
然后在每个开口184中形成金属接触190。金属接触190可以通过首先使用原子层沉积工艺对由例如TiN制成的薄(3nm至8nm)金属内衬进行沉积来制成。然后使用热化学气相沉积工艺来沉积金属填充材料。该金属填充材料例如可以包括钨。使用化学机械抛光(CMP)工艺以去除金属内衬和金属填充物的多余部分，其中在遮蔽掩模160已经被去除之后停止抛光(例如在厚度约等于高度h处)。结果在图20至图22中示出。
虽未特别示出，将理解的是，可以在每个接触开口184的底部处形成金属硅化物以提高在进行到源极区和漏极区的电连接中的接触电阻。
然后可以在ILD/PMD层146’的顶表面上形成常规的例如金属化层的后段制程(BEOL)结构，以便电连接至源极接触、漏极接触和栅极接触。例如参见图23至图24。
所披露的工艺和结构可以与平坦MOSFET器件的制造联合使用。如以上所讨论的，在本文中所描述的用于接触的技术和结构进一步适用于FinFET器件，并且还可以与其他集成电路器件联合使用，其他集成电路器件包括但不限于双极型晶体管器件、二极管器件、具有从UTBB或ETSOI衬底形成的源极区和漏极区的平坦晶体管器件等。
本文中的优选实施例利用SOI型衬底，但是将理解的是，体衬底和其他类型的衬底可以作为构建利用本文所披露的制造技术和结构的集成电路的基础。
已经通过示例性且非限制性的示例提供了前面的描述，是对本发明示例性实施例的完整且详实的描述。然而，对于相关领域的技术人员而言，鉴于前面的描述，当结合附图和所附权利要求书来阅读本说明书时，各种修改和适配会变得明显。然而，对本发明教导的所有这样和类似的修改将仍然落入如所附权利要求书所确定的本发明的范围之内。

Claims (7)

1.一种集成电路，包括：
源漏区；
与所述源漏区相邻的沟道区；
在所述沟道区之上延伸的栅极结构；
侧壁间隔物，所述侧壁间隔物在所述栅极结构的一侧上并且在所述源漏区之上延伸；以及
电介质层，所述电介质层与所述侧壁间隔物接触并且具有顶表面；
其中，所述栅极结构由单体导电材料制成，所述单体包括：
所述单体的栅极电极区；以及
所述单体的栅极接触区，所述栅极接触区从所述栅极电极区的顶部延伸；
其中，所述集成电路还包括栅极电介质层，所述栅极电介质层位于所述栅极电极区的底部和所述沟道区之间，所述栅极电介质层沿着所述栅极电极区的侧表面、在所述栅极电极区和所述侧壁间隔物的侧表面之间延伸，所述栅极电介质层还沿着所述栅极接触区的侧表面、在所述栅极接触区和所述侧壁间隔物的侧表面之间延伸。
2.如权利要求1所述的集成电路，其中，所述栅极电极区的侧表面与所述栅极接触区的侧表面相互对准并且平行于所述侧壁间隔物的内表面延伸。
3.如权利要求1所述的集成电路，其中，所述侧壁间隔物的高度等于所述电介质层的高度。
4.如权利要求1所述的集成电路，其中，所述电介质层是层间电介质(ILD)层或预金属化电介质(PMD)层之一。
5.如权利要求1所述的集成电路，还包括从所述电介质层的所述顶表面延伸至所述源漏区的源漏接触，所述源漏接触与所述侧壁间隔物的外表面接触。
6.如权利要求1所述的集成电路，还包括在所述电介质层的所述顶表面上的金属化层，所述金属化层包括与所述栅极接触区的顶表面电接触的金属线。
7.如权利要求1所述的集成电路，其中，所述栅极电极区的侧表面与所述栅极接触区的侧表面相互自对准。
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