CN1790742A - 具有内部隔片结构的金属镶嵌栅极场效应晶体管 - Google Patents

具有内部隔片结构的金属镶嵌栅极场效应晶体管 Download PDF

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Publication number
CN1790742A
CN1790742A CNA2005101193341A CN200510119334A CN1790742A CN 1790742 A CN1790742 A CN 1790742A CN A2005101193341 A CNA2005101193341 A CN A2005101193341A CN 200510119334 A CN200510119334 A CN 200510119334A CN 1790742 A CN1790742 A CN 1790742A
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grid
dielectric layer
spacer structure
effect transistor
field effect
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萨普莱蒂克·格哈
赫塞恩·I·哈纳菲
拉雅拉奥·杰米
保罗·M·索洛蒙
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International Business Machines Corp
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International Business Machines Corp
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

公开了一种MOSFET，其包括：位于源极扩展区和漏极扩展区之间的沟道，位于所述沟道之上的介质层，在所述介质层的周边部分上形成的栅极隔片结构，和布置在所述介质层的周边部分上的栅极；所述栅极至少下部被所述栅极隔片结构的内表面围绕，并与之接触，并且所述栅极在底部基本上与所述沟道对准。一种形成所述MOSFET的方法，其包括：形成所述介质层，在空腔内部形成栅极隔片结构和栅极接触，所述空腔是通过去除牺牲栅极和牺牲隔片结构形成的。

Description

具有内部隔片结构的金属镶嵌栅极场效应晶体管
技术领域
本发明涉及具有布置了内部隔片结构的金属镶嵌栅极的MOSFET(金属氧化物半导体场效应晶体管)器件以及所述器件的形成工艺。
技术领域
为了扩展CMOS的缩放比例，研究了具有更高介电常数(Hi-K)的电介质。对于给定的栅极电容，在沟道中存在电荷，Hi-K电介质可以更厚，从而减小隧穿泄漏。为了进一步增大栅极电容，并且使薄硅实现(thin-siliconimplementation)具有适当的逸出功，希望采用金属栅极。这些材料选项经常与常规工艺过程的高温前端处理存在抵触，因此，尝试采用替换栅极方法，其中在通过去除伪栅形成的沟槽中淀积Hi-K电介质和金属。
随着场效应晶体管(FET)栅极长度的减小，Hi-K电介质覆盖了越来越多的沟槽部分。栅极本身的底部拐角倾向于变圆，因此，只有栅极的中央具有充分的沟道控制。此外，源极/漏极(S/D)扩展注入区和栅极边缘之间存在的缝隙增大了FET的开启电阻。因此，需要替代常规方法的器件形成方法，其能够在栅极和S/D扩展区之间实现更好的覆盖或对准，并且能够实现更好的栅极接触轮廓，从而改善器件性能。
发明内容
本发明涉及具有改善的器件性能的MOSFET，以及制造所述器件的方法。所述MOSFET包括源极扩展区(source extension)、布置在所述源极扩展区上的源极接触、漏极扩展区、布置在所述漏极扩展区上的漏极接触、位于所述源极扩展区和所述漏极扩展区之间的沟道、所述沟道之上的介质层、布置在所述介质层的顶面的周边部分上的栅极隔片结构，所述栅极隔片结构具有与介质层的顶面以接近直角的角度相交的内表面。至少，布置在介质层顶面的非周边部分的栅极的下部被栅极隔片结构所环绕，并与其内表面接触。而且，所述栅极在底部与所述沟道对准。
一种形成MOSFET的方法，其包括：在衬底上提供沟道层；在所述沟道层中形成源极扩展区和漏极扩展区，由此在源极扩展区和漏极扩展区之间界定沟道；在所述沟道之上形成介质层；在所述介质层的顶面的周边部分之上形成栅极隔片结构，所述栅极隔片结构的内表面的下部基本上垂直于介质层的顶面，由此界定了侧壁为所述栅极隔片结构的内表面，底部为所述介质层的空腔；通过将导电材料布置到所述空腔当中，以接触所述介质层的顶面而形成栅极接触。
附图说明
下面将通过附图和下面的实例对本发明予以更为详细的说明。图1-14示出了在制造过程的各个阶段所获得的结构。
图1示出了带有底部绝缘体、沟道层和保护层的衬底的横截面图；
图2说明了在图1所示的结构之上形成伪栅(dummy gate)；
图3说明了由图2所示的结构形成沟道、伪栅隔片和隔离隔片结构；
图4示出了在图3所示的结构上形成的第一覆层(overlayer)和第二覆层；
图5示出了对伪栅进行平面化处理之后的图4的结构；
图6示出了去除伪栅和伪栅隔片之后的结构；
图7示出了带有隔离隔片的图6的结构；
图8说明了介质层和栅极隔片的形成；
图9说明了栅极接触的形成；
图10-12说明了在栅极接触的底部形成介质层的备选工艺程序；
图13示出了图9中的器件的放大横截面图；
图14示出了备选器件结构的横截面图。
所述附图只做说明意图，因此没有按实际尺寸或按比例绘制。
具体实施方式
现在，将参照本申请的附图对本发明进行更为详细的说明。在附图当中，采用类似的附图标记表示类似的相应元件。
图1示出了初始的叠置结构，其包括具有位于其上的底部绝缘体2的衬底1，还可以将底部绝缘体2称为埋入氧化层。初始叠置结构还包括位于底部绝缘体2顶部的沟道层3和位于沟道层3顶部的氧化层4，还可以将氧化层4称为衬垫保护层。
可以采用本领域公知的常规材料和工艺步骤制造图1所示的结构。例如，衬底1可以包括任何半导体材料，包括但不限于：Si、Ge、SiGe、GaAs、InAs、InP和所有其他III/V半导体化合物，还可以是包括不同半导体材料的分层衬底，例如Si/SiGe。图1中的示例性实施例示出了绝缘体上硅(SOI)结构，其中，在埋入氧化层2上提供沟道层3。对于具有埋入氧化层2的实施例而言，衬底1还可以是任何其他材料(例如不限于半导体)，只要其为层2提供足够的支持即可。在其他实施例中，可以省略层2。衬底可以是n型或p型，这取决于所希望制造的器件。衬底可以进一步含有有源器件区、线路区、隔离区或其他类似的区域(未示出)。衬底1还可以由诸如SiO2的介电材料构成，并且可以被用作存储器件的隔离区。通常，可以省略层1或层2；或者所述的两个层可以包括任何适当的材料或具体器件应用所需要的材料组合。
沟道层3可以包括任何半导体材料，例如Si、SiGe、SiGeC、InAs、GaAs、InP和其他III/V化合物半导体。这里还可以考虑这些半导体材料的组合，包括具有应变或不具有应变的。可以采用常规淀积工艺形成沟道层3，例如，包括化学气相淀积(CVD)、等离子体辅助CVD、蒸镀或化学溶液淀积。此外，可以采用商用的SIMOX或SMARTCUT[Bruel et al.Jpn.J.Appl.Phys.，″Smart Cut：a new silicon on insulator material technology based onhydrogen implantation and wafer bonding″，36(1997)1636-1641]工艺，由SOI形成沟道层3。典型地，沟道层3具有大约10nm的厚度。它可以具有大约在20到100nm之间的初始厚度，并在之后减小到预期厚度。
衬垫保护层4可以包括诸如SiO2的氧化物，其采用常规的热工艺形成，或者通过诸如化学气相淀积(CVD)、等离子体辅助CVD、溅射、蒸镀或其他淀积工艺的常规淀积工艺形成。衬垫保护层4的厚度对于本发明来讲是无关紧要的，因此可以发生变化。不管采用哪种技术，衬垫保护层4通常具有大约2到30nm之间的厚度，优选处于大约5到10nm之间。
图2示出了构图步骤的结果，其中，在图1的叠置结构之上采用伪栅(dummy gate)硬掩模6对伪栅5或牺牲栅进行构图。这可以通过在图1所示的结构之上淀积例如包括多晶硅或非晶硅的伪栅层，之后淀积伪栅硬掩模层来实现。在采用常规光刻技术和反应离子蚀刻(RIE)对伪栅硬掩模6进行构图之后，通过RIE将所述栅极图案转移到下部的伪栅层。衬垫保护层4起着蚀刻停止层的作用，在对伪栅5进行RIE构图时保护沟道层3。
在接下来的步骤中，将掺杂剂通过衬垫保护层4掺杂到沟道层3中，从而形成源极/漏极扩展区，也称为源极/漏极(S/D)结，伪栅5起着注入掩模的作用。在离子注入之后，对S/D扩展区进行退火，以激活掺杂剂。这样在S/D扩展区之间界定了具有预定沟道长度的沟道9(参见图3)，该预定长度基本上等于伪栅5的长度。
之后，邻近伪栅5形成伪栅隔片8，其由衬垫保护层4向上延伸至伪栅硬掩模6。伪栅隔片8可以包括易于在后续工艺步骤中去除的氧化物或其他材料。在本实施例中，伪栅隔片8具有一体的构造，例如，以围绕伪栅5的环形形式存在。例如，可以首先在图2所示的结构之上淀积由适当材料构成的层(在形成S/D之后)，之后进行反应离子蚀刻，从而形成伪栅隔片8。
在伪栅隔片8的侧面形成隔离隔片结构7。在图3中示出了所得到的结构。在本实施例中，隔离隔片7具有一体的构造，例如，以围绕所述伪栅隔片8的环形的形式存在。正如这里所采用的，采用隔离隔片结构7表示(诸)隔离隔片，不管其是否具有一体的结构。在实践当中，由于相对来讲易于制造，因此优选采用一体的结构。隔离隔片结构7可以由任何绝缘材料构成，例如包括：氧化物、氮化物、氮氧化物或它们的任何组合，只要相对于伪栅隔片8的材料能够对所述绝缘材料进行有选择地蚀刻即可。可以通过淀积绝缘材料，之后进行蚀刻形成隔离隔片结构7。优选材料是氮化硅。
之后，在围绕伪栅5和伪栅隔片8的区域去除衬垫保护层4以暴露沟道层3，例如，这可以采用HF通过湿法化学蚀刻完成。
在下述步骤中，可以在源极/漏极扩展区之上构建源极/漏极接触10(参见图4)。这可以通过外延生长，以形成升高的源极/漏极接触10，之后注入如砷(As)或硼(B)的掺杂剂来实现。之后，可以使源极/漏极接触10生成硅化物。最终，源极/漏极接触10成为由下部硅层和上部金属硅化物层构成的复合层。
接下来，在整个结构之上淀积第一覆层11，例如示范性地包含氮化硅的绝缘层，之后淀积第二覆层12，例如包括氧化物。对第二覆层12进行平面化处理直至第一覆层11，例如，可以通过化学机械平面化处理(CMP)。不需要精确的时间控制，因为第一覆层11起着平面化阻挡层的作用。图4示出了所得到的结果。注意，在备选实施例中，第一覆层11可以包括氧化物，第二覆层12可以包括氮化硅。但是，在后一实施例中，第二覆层12的CMP可能需要时间控制，因为无法相对下部氧化物对氮化物进行有选择的抛光。
可以对第二覆层12、氮化物覆层11以及伪栅掩模6的残余进行蚀刻直至伪栅5，例如可以采用RIE。在所使用的材料均不具有自然的蚀刻阻挡功能时，优选对这一步骤进行时间控制，从而在预期的伪栅高度停止。由于多晶硅中的RIE蚀刻速率可能低于氮化物和氧化物中的蚀刻速率，因此，如果伪栅5是由多晶硅构成的，那么其可能比第一覆层11和伪栅隔片8的剩余部分稍高一点。图5示出了这一步骤所得到的结果。
之后，通过蚀刻去除伪栅5，例如采用氢氧化钾(KOH)。衬垫保护层4保护沟道层3和沟道9免受蚀刻剂影响。
接下来，例如，采用稀释的HF去除伪栅隔片8，其还去除了衬垫保护层4，所得到的结构如图6所示。第一覆层11和隔离隔片结构7可以包括抗HF的氮化硅。通常，隔离隔片结构7起着防止源极/漏极接触10受到蚀刻剂侵蚀的作用，所述蚀刻剂用于去除伪栅隔片8。但是，如果S/D接触10的材料能够抵抗用来去除伪栅隔片8的蚀刻剂的作用，那么隔片7就不是必需的。
如图6所示，沟道层3和隔离隔片7一起界定了空腔13。在没有可选的隔离隔片结构7的情况下，可以由沟道层3界定空腔13的底部，由S/D接触10和覆层11的侧表面界定空腔13的侧壁。可以看到，沟道9的长度短于氮化物隔片7之间的距离。在这一过程中，伪栅5用作牺牲功能部件，有助于界定沟道长度，而伪栅隔片8则允许界定的空腔13具有大于所述沟道长度的底部横向尺寸。空腔13通常，但未必一定是高纵横比的孔径。这里，采用术语“高纵横比的孔径”表示空腔13的高宽比(H/W)为2或更大。
在这一阶段，可以在沟道层3和位于空腔13内的沟道9上生长可选的牺牲氧化层，以生成用于下一步骤的更为清洁的表面。牺牲氧化层还起着使沟道9更薄的作用，因为这一生长不仅在沟道9和沟道层3的顶部添加材料，还会延伸到沟道9和沟道层3内部。之后，通过选择蚀刻去除牺牲氧化层，在空腔13的底部保留更加洁净的，变薄了的沟道9和沟道层3。这生成了沟道层3的“凹陷”部分，它比位于空腔13之外的其余沟道层更薄。
之后，可以在空腔13的底部形成可选的栅极隔离层14，如图7所示。栅极隔离层14在沟道9和将要在其上淀积的绝缘材料之间起着缓冲层的作用。栅极隔离层14的优选材料为氧化硅，其可以热生长获得，如果必要的话对其进行减薄。但是，还有其他合适的材料。例如，这一栅极隔离层用于防止硅沟道中的迁移率下降，这种迁移率下降可能是由介质层中的散射机制引起的。
之后，淀积优选包括高K介电材料的介质层15。如图8所示，介质层15覆盖氮化物覆层11、隔离隔片7的侧壁和栅极隔离层14。高K材料是指介电常数大约超过10或更高的材料。此类材料的例子包括但不限于氧化铪、硅酸铪、氧化铝或氧化锆。
如果在所述工艺过程的这一阶段形成栅极，那么和常规方法中的做法一样，存在两个弊端：首先，栅极和沟道层3中的源极/漏极扩展区之间的寄生电容将过高。其次，在介质层从位于栅极隔离层14之上的平面过渡到邻近隔离隔片结构7的平面的区域内，在淀积工艺特性的影响下，介质层展示出圆形边缘。这些圆形边缘将导致介质层15在源极/漏极扩展区和栅极边缘之间增厚，引起对沟道9的栅极控制减弱，FET的开启电阻将由此增大，亚阈值摆动(sub-threshold swing)也将劣化。由于只有栅极的中央具有对沟道的充分控制，因此器件性能将劣化。
因此，根据本发明，在空腔13的内部形成“内部”栅极隔片16，或更一般地来讲，形成栅极隔片结构，如图8所示。例如，可以通过在空腔13中淀积诸如氧化物或其他适当材料的隔片材料获得所述栅极隔片结构，并对淀积材料进行各向异性蚀刻，例如通过RIE，使得沟道9上的部分介质层15露出，并将栅极隔片结构16留在空腔13的侧壁上。栅极隔片结构16的这一布置使沟道9上的空腔13变窄。栅极隔片结构16具有下部基本上垂直于介质层15的内表面16S(即，面向空腔13的内部、远离空腔侧壁的表面)。换句话说，内表面16S在空腔13的底部大约以直角接触介质层15或与之相遇，但是与直角还存在一定偏差的角度，例如更大或更小的角度都是可能的。但是，优选采用大的凹角(re-entrant)轮廓。栅极隔片结构16的蚀刻过程相对于介质层15是具有选择性的。可以看到，所示的栅极隔片结构16具有一体的结构，例如，以嵌入到空腔13以内的环形造型存在。原则上，栅极隔片结构16还可以由两个单独的隔片形成，尽管其可能包括更为复杂的制造过程。
之后，采用导电材料填充空腔13，以形成栅极17。这可以向空腔13内和介质层15上淀积材料来实现。例如，可以通过诸如钨或氮化钛的气相淀积，或者通过淀积非晶硅，并将其与诸如镍的金属反应以生成硅化物来形成所述导电材料，之后，将其减薄至介质层15，并通过例如CMP尽可能地去除位于空腔13之外的导电材料和介质层15。还可以采用多晶硅，例如原位(in-situ)掺杂的或采用常规的离子注入和退火技术进行掺杂的，只要退火温度和条件与介质层15和第二覆层11兼容即可。图9示出了所得到的结构。沟道9不仅小于隔离隔片7之间的距离，而且基本上与栅极17的底部横向对准，而且，栅极17的下部轮廓在与介质层15的界面处也得到了改善。具体而言，在栅极隔片16、介质层15和栅极17的底部相遇的区域内不再具有圆形拐角。相反，栅极17的下部和介质层15相遇在由内部隔片结构16界定的一个相对锐利的“边缘”，二者之间基本上相互垂直。这提供了从栅极17到沟道9的更好的控制。
通常，可以采用很多不同的导电材料形成栅极17，例如包括：诸如钨、铼、钽、铪、钼、铝、镧的元素金属，诸如氮化钛、氮化钽、氮化钨、氮化钽硅的金属氮化物，各种硅化物栅极(具有或不具有用于阈值电压控制的掺杂剂)；以及导电金属氧化物，只要它们与预期的工艺兼容即可。
图10-12示出了可以用来形成具有内部栅极隔片的栅极的备选工艺程序。在本实施例中，对图7中的结构采取淀积步骤，其中，只在位于空腔13的底部的栅极隔离层14上形成介质层15。例如，这可以通过对诸如铪、锆、铝、以及其他材料进行热蒸镀的方向性淀积工艺，以及此后向诸如金属氧化物、硅酸盐或其他适当的高K材料的化学转化来获取所述介质层15，所述化学转化的目的在于进一步降低侧壁电容。如图10所示，介质层15只覆盖了空腔13的底部。但是，仍然存在问题，即介质层15与隔离隔片结构7相交的边缘可能未得到良好的界定，其或者向上呈圆弧状，或者向下呈圆弧状(例如，类似新月(cusp))，这将导致：在第一种情况下，降低在所要形成的栅极和沟道9之间的控制；在第二种情况下，存在在所要形成的栅极和沟道9之间产生短路的危险。
因此，如图11所示，在空腔13内部形成内部栅极隔片结构16，具体过程与参照图8进行的前述说明相同。这里，栅极隔片结构16既与介质层15接触又与隔离隔片结构7接触。相反，在没有隔离隔片结构7的其他实施例中，栅极隔片结构16将与覆层11接触。
如前所述，之后采用导电材料填充空腔13，以形成栅极17，具体过程如前所述。图12示出了所得到的结构。位于栅极17的底部和介质层15之间的界面再一次通过栅极隔片结构16得到了更好界定，并且通过其提供了对沟道9的更好控制。如上所述，隔离隔片结构7和栅极隔离层14是可选的，在备选实施例中可以省略其中的一个或全部省略。
图13示出了图9中的器件的放大图，其采用了不同的附图标记来表示源极侧元件和漏极侧元件。沟道层3布置在衬底1之上，其包括沟道9、源极扩展区3a和漏极扩展区3b。沟道9的特点在于具有横向沟道长度(1)。分别提供源极接触10a和漏极接触10b与源极扩展区3a和漏极扩展区3b接触。
在沟道层3上布置栅极隔离层14，在栅极隔离层14上布置介质层15。在其他实施例中，可以省略栅极隔离层14。在图13的实施例中，介质层15具有U型截面，其具有基本上垂直的侧壁部分和具有顶面15T的水平部分。如16a和16b所示的内部栅极隔片结构布置在介质层15的顶面15T的周边区域上。注意，内部隔片结构16a和16b覆盖了位于介质层15的水平部分和侧壁部分之间的圆形边缘或轮廓，其(远离介质层15的)内表面16S的下部基本上垂直于介质层15的顶面15T。在这种情况下，内部隔片结构16a和16b还与U型介质层15的垂直侧壁部分接触。在这一实施例中，内表面16S为曲面，例如具有朝向顶部弯曲的区域。其他变化也是可能的，取决于所采用的具体工艺步骤。例如，内部隔片16a和16b还可以具有矩形截面，例如，通过打磨或切除上部弯曲区域，形成内表面的水平部分。
采用适当的栅极材料填充隔片结构16a和16b之间的空间以及介质层15的相对侧壁之间的空间，从而形成下部被栅极隔片结构16a和16b环绕，上部被介质层15环绕的栅极17。在栅极17的底部，其具有至少等于沟道长度的水平尺寸，并且基本上与沟道9对准(即，基本上与S/D扩展区的边缘横向对准)。在这一器件当中，隔片结构16a和16b有效地界定了栅极的底部和下部，从而与介质层15的“非周边”部分接触，进而在位于栅极17的底部和介质层15的顶面15T之间获取得到界定更好的边缘，例如更加陡峭的边缘。这一栅极接触的底部轮廓为所述器件实现了改善的沟道控制。
如图13所示，通过隔离隔片结构(如源极侧上的7a和漏极侧上的7b所示)使源极接触10a和漏极接触10b与介质层15绝缘。如上所述，是否采用隔离隔片结构7是可选的，取决于源极接触10a和漏极接触10b所采用的材料和具体的工艺条件，可以省略所述隔离隔片结构7。
在形成这一结构之后，可以实施惯常采用的中端和末端流水线工艺，包括形成背栅接触。
图14示出了备选器件结构，其中，只在空腔13的底部形成介质层15(参见借助附图10-12的描述)，并且省略了栅极隔离层14和隔离隔片7。在这一实施例中，栅极隔片结构16a、16b还邻近源极接触、漏极接触和覆层11，并与之接触。
尽管本发明只示出了一个FET结构的形成，但是也可以考虑在单个衬底上形成多个这样的FET结构。
尽管已经参照本发明的优选实施例对本发明进行了特别地展示和说明，但是所述领域技术人员应该理解的是，在不背离述权利要求定义的本发明的精神和范围的情况下，在其外形和细节上可做出前述和其他改变。因此，本发明不仅限于说明书和附图中具体的外形和细节，而是由权利要求界定范围。
所公开的任何实施例均可以与得到图示和/或说明的一个或几个其他实施例进行结合。对于实施例的一个或多个功能部件也可以进行这种结合。
本领于技术人员应当理解的是，在不背离权利要求界定的本发明的精神的情况下，可以在很多方面对所公开的构造做出改变。

Claims (18)

1.一种金属氧化物半导体场效应晶体管，其包括：
源极扩展区；
布置在所述源极扩展区上的源极接触；
漏极扩展区；
布置在所述漏极扩展区上的漏极接触；
位于所述源极扩展区和所述漏极扩展区之间的沟道；
位于所述沟道之上的介质层；
布置在所述介质层的顶面的周边部分上的栅极隔片结构，其具有与所述顶面以直角相交的内表面；
布置在所述介质层的所述顶面的非周边部分上的栅极，其至少下部被所述栅极隔片结构的内表面围绕，并与之接触；并且，所述栅极在底部基本上与所述沟道对准。
2.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述栅极隔片结构与所述源极接触和所述漏极接触相邻。
3.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述介质层包括介电常数大于约10的材料。
4.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述介质层具有U型截面，所述U型截面的垂直部分邻接所述介质层的所述顶面的周边部分。
5.如权利要求4所述的金属氧化物半导体场效应晶体管，其中，所述U型介质层的垂直部分围绕所述栅极的上部。
6.如权利要求1所述的金属氧化物半导体场效应晶体管，进一步包括将所述介质层与所述源极接触和所述漏极接触隔开的隔离隔片结构。
7.如权利要求6所述的金属氧化物半导体场效应晶体管，其中，所述隔离隔片结构具有一体的构造。
8.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述栅极进一步具有被布置在所述介质层和所述源极接触、漏极接触之间的隔离隔片结构围绕的上部。
9.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述栅极进一步具有被布置在所述源极接触和漏极接触上的绝缘层围绕的上部。
10.如权利要求9所述的金属氧化物半导体场效应晶体管，其中，所述栅极隔片结构与所述源极接触、漏极接触和所述绝缘层接触。
11.如权利要求1所述的金属氧化物半导体场效应晶体管，进一步包括位于所述沟道和所述介质层之间的栅极隔离层。
12.如权利要求1所述的金属氧化物半导体场效应晶体管，其中，所述栅极隔片结构具有一体的构造。
13.一种形成金属氧化物半导体场效应晶体管的方法，包括的步骤有：
a)在衬底上提供沟道层；
b)在所述沟道层中形成源极扩展区和漏极扩展区，由此在所述源极扩展区和所述漏极扩展区之间界定沟道；
c)在所述沟道之上形成介质层；
d)在所述介质层的顶面的周边部分之上形成栅极隔片结构，所述栅极隔片结构的内表面的下部基本上垂直于所述介质层的所述顶面，由此界定了第一空腔，所述空腔在其侧壁由所述栅极隔片结构的所述内表面界定，在其底部由所述介质层界定；
e)通过将导电材料布置到所述第一空腔当中，以接触所述介质层的所述顶面而形成栅极接触。
14.如权利要求13所述的方法，其中，所述步骤(a)进一步包括：
(a1)在所述沟道层上形成牺牲栅极；
(a2)将掺杂剂注入所述沟道层，所述牺牲栅极起着注入掩模的作用；
(a3)退火以激活所述掺杂剂，由此形成所述源极扩展区和漏极扩展区。
15.如权利要求14所述的方法，其在步骤(c)和(d)之前进一步包括：
f)邻近所述牺牲栅极形成牺牲栅极隔片结构；
g)在所述源极扩展区处形成源极接触，在所述漏极扩展区处形成漏极接触；
h)在所述源极接触和漏极接触的顶部形成绝缘层；以及
i)去除所述牺牲栅极和所述牺牲栅极隔片结构，以形成第二空腔，所述第二空腔的侧壁部分由所述绝缘层和所述源极接触和漏极接触界定，所述第二空腔的底部由所述沟道层界定；其中，所述栅极隔片和所述介质层形成于所述第二空腔之内。
16.如权利要求15所述的方法，其进一步包括：
j)在所述源极/漏极扩展区上形成隔离隔片结构，所述隔离隔片结构邻接所述源极接触和所述漏极接触。
17.如权利要求15所述的方法，其在所述步骤(c)之前进一步包括：
k)在所述第二空腔的底部生长牺牲氧化物层；以及
l)去除所述牺牲氧化物层。
18.如权利要求13所述的方法，其进一步包括形成所述栅极隔片结构，所述栅极隔片结构是通过将隔片材料填充到所述第一空腔内，并对其进行各向异性蚀刻以暴露所述介质层形成的。
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