WO2012016361A1 - 应变半导体沟道形成方法和半导体器件 - Google Patents

应变半导体沟道形成方法和半导体器件 Download PDF

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WO2012016361A1
WO2012016361A1 PCT/CN2010/001436 CN2010001436W WO2012016361A1 WO 2012016361 A1 WO2012016361 A1 WO 2012016361A1 CN 2010001436 W CN2010001436 W CN 2010001436W WO 2012016361 A1 WO2012016361 A1 WO 2012016361A1
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layer
semiconductor
sige
dielectric layer
epitaxial
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PCT/CN2010/001436
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English (en)
French (fr)
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尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Priority to US13/059,285 priority Critical patent/US8575654B2/en
Priority to GB1121729.6A priority patent/GB2487113B/en
Priority to CN201090000828.2U priority patent/CN202758852U/zh
Publication of WO2012016361A1 publication Critical patent/WO2012016361A1/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66651Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to semiconductor devices and methods of fabricating the same, and more particularly to a method of forming a strained semiconductor channel and a semiconductor device fabricated by the method. Background technique
  • a tensile strained Si layer structure provided on the SiGe relaxation layer is widely used.
  • the composition of the SiGe relaxed layer is expressed in the form of Si 1-x Ge, xe [0, 1].
  • Fig. 1A shows an atomic lattice diagram of a tensile strained Si layer structure disposed on a SiGe relaxed layer
  • Fig. 1B shows an energy level structure of a tensile strained Si layer structure disposed on a SiGe relaxed layer.
  • the conduction band in the tensile strained Si layer is lower than that in the SiGe relaxation layer due to the large biaxial tensile stress in the tensile strained Si layer.
  • a very high electronic in-plane mobility will be obtained in the tensile strained Si layer.
  • Figure 2A shows the longitudinal Ge atomic percent distribution of the SiGe relaxed layer.
  • the percentage of Ge atoms gradually increases from 0% to 100% from bottom to top, that is, X in the composition Si ⁇ Ge x gradually changes from 0 to 1.
  • a SiGe relaxed layer or a Ge layer is obtained by growing an ultrathick (several micrometers) SiGe layer on a Si substrate. Further, the compressive strain in the SiGe relaxed layer is released by defect generation (Fig. 2B), thereby obtaining a SiGe relaxed layer or a Ge layer.
  • FIG. 3A, 3B and 3C respectively show three conventional strained Si channel formation methods
  • Fig. 3A shows a strained Si/body SiGe MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure
  • Fig. 3B shows SG0I ( SiGe-On-Insulator) MOSFET structure
  • Figure 3C shows the SSDOI (Strained Si Directly On Insulator) MOSFET structure.
  • strain Si must be formed on the SiGe layer (or buried oxide) before the device fabrication process (for example, shallow trench isolation (STI), gate formation, etc.) Cladding.
  • the strained Si coating may be damaged during the device fabrication process, for example, pad oxidation treatment in the STI process, sacrificial oxidation before the gate formation process Treatment, various wet chemical cleaning treatments, etc., may cause loss of the strained Si coating;
  • the strained Si coating may relax during the high temperature step (stress is released), for example, to activate the source/ Annealing of the drain dopant may cause stress in the strained Si cladding to be released. Summary of the invention
  • the present invention proposes a strained semiconductor channel formation method in which a strained semiconductor channel (a material may be selected from Si, Ge or SiGe) after removing the replacement gate, thereby avoiding strained semiconductor trenches
  • a strained semiconductor channel (a material may be selected from Si, Ge or SiGe) after removing the replacement gate, thereby avoiding strained semiconductor trenches
  • the channel is exposed to high temperature source/drain annealing, and semiconductor layer losses are avoided due to the processing steps experienced to reduce the strained semiconductor channel.
  • the present invention also proposes a semiconductor device manufactured by the method.
  • a method of forming a strained semiconductor channel comprising the steps of: forming a SiGe relaxed layer on a semiconductor substrate; forming a dielectric layer on the SiGe relaxed layer, the dielectric Forming a replacement gate on the layer, the dielectric layer and the replacement gate forming an alternative gate stack structure; depositing an interlayer dielectric layer, planarizing the interlayer dielectric layer to expose the replacement gate Etching the replacement gate and the dielectric layer to form an opening; performing selective semiconductor epitaxial growth in the opening to form a semiconductor epitaxial layer; depositing a high- ⁇ dielectric layer and a metal layer; and depositing The metal layer and the high- ⁇ dielectric layer perform a planarization process to remove the high- ⁇ dielectric layer and the metal layer overlying the interlayer dielectric layer to form a metal gate.
  • the semiconductor epitaxial layer is a Si epitaxial layer, a Ge epitaxial layer, or a SiGe epitaxial layer.
  • the strained semiconductor channel forming method further comprises the steps of: etching the S iGe relaxation layer in the opening To etch out a space for semiconductor epitaxial growth.
  • the thickness of the semiconductor epitaxial layer is in the range of 5 to 10 nm.
  • the percentage of Ge atoms in the SiGe relaxed layer gradually changes from 20% adjacent to the semiconductor substrate to 100% away from the semiconductor substrate.
  • an etch stop layer is formed in the step of forming the SiGe relaxed layer. More preferably, the etch stop layer has a different percentage of Ge atoms than the SiGe relaxed layer.
  • a semiconductor device comprising: a semiconductor substrate; a SiGe relaxation layer formed on the semiconductor substrate; a semiconductor epitaxial layer formed on the SiGe relaxation layer, located On the SiGe relaxation layer, or embedded in the SiGe relaxation layer; a high-K dielectric layer deposited on the entire surface of the semiconductor epitaxial layer to form a hollow column having a bottom surface; and a metal gate, Filled inside the hollow cylindrical shape formed by the high-k dielectric layer.
  • the semiconductor epitaxial layer is a Si epitaxial layer, a Ge epitaxial layer, or a SiGe epitaxial layer.
  • the thickness of the semiconductor epitaxial layer is in the range of 5 to 10 nm.
  • the semiconductor device further includes: a sidewall spacer deposited on the SiGe relaxation layer, surrounding an outer circumference of the semiconductor epitaxial layer and the high-k dielectric layer, or surrounding the high-k dielectric layer a peripheral layer; and an interlayer dielectric layer deposited on the SiGe relaxation layer surrounding the periphery of the sidewall spacer.
  • the percentage of Ge atoms in the SiGe relaxed layer gradually changes from 20% adjacent to the semiconductor substrate to 100% away from the semiconductor substrate.
  • the SiGe relaxation layer is formed with an etch stop layer. More preferably, the etch stop layer has a different percentage of Ge atoms than the SiGe relaxed layer.
  • the strained semiconductor layer is formed after removing the replacement gate, thereby avoiding The strained semiconductor channel is exposed to a high temperature source/drain anneal, and the loss of the strained semiconductor layer is avoided by reducing the processing steps experienced by the strained semiconductor channel.
  • FIG. 1A shows an atomic lattice diagram of a tensile strained Si layer structure disposed on a SiGe relaxed layer
  • FIG. 1B shows an energy level structure of a tensile strained Si layer structure disposed on a SiGe relaxed layer
  • FIGS. 2A and 2B are schematic views for explaining a preparation method of a relaxation layer and properties thereof;
  • 3A, 3B and 3C show three conventional strained Si channel formation methods, respectively;
  • FIG. 14 shows a fabrication of a semiconductor device manufacturing method according to a first embodiment of the present invention.
  • FIG. 4 to 9 and 15 to 18 are schematic views showing respective steps of a method of fabricating a semiconductor device according to a second embodiment of the present invention, wherein FIG. 18 shows a semiconductor device fabrication according to a second embodiment of the present invention. The method of fabricating a completed semiconductor device.
  • FIG. Figure 14 is a schematic view showing a semiconductor device in which a semiconductor device manufacturing method is completed according to a first embodiment of the present invention.
  • the semiconductor device manufactured according to the process of the first embodiment of the present invention mainly comprises: a substrate 300 (Si wafer, SOI, etc.), a SiGe relaxation layer 200 (Ge atom% is as shown in FIG. The lower to upper direction, from 20% to 100%), the semiconductor epitaxial layer 260 (shown as the Si epitaxial layer 260, which may also be a Ge ⁇ epitaxial layer or a SiGe epitaxial layer) (thickness: 5 to 10 nm), high K a dielectric layer 320 (having a thickness of 1 to 3 nm), a metal gate 330, a Si spacer 240 (having a width of 10 to 40 nm), and an interlayer dielectric layer 250 (having a thickness of 15 to 50 nm), wherein the SiGe relaxation layer 200 is formed in On the substrate 300; a gate structure composed of a Si 3 N 4 spacer 240, a Si epitaxial layer 260, a high-k dielectric layer
  • the Si epitaxial layer 260 is formed, thereby avoiding the source/drain annealing treatment in which the strained Si channel is exposed to a high temperature, and the processing steps to be experienced by reducing the strained Si channel, The loss of the Si epitaxial layer 260 is avoided.
  • a SiGe relaxation layer 200 is formed on a substrate 300 (Si wafer, SOI, etc.).
  • the percentage of Ge atoms that is, the number of Ge atoms, is a percentage of the total number of atoms, as shown in FIG. 4 from the bottom to the top direction (from the adjacent substrate 300 to the direction away from the substrate 300), For example, the gradual change from 20% to 100%, that is, the X in the composition 5 ⁇ 6 is gradually changed from 0.2 to 1.
  • the group of SiGe relaxation layers 200 The specific numerical values are used for the purpose of example only, and those skilled in the art can select an appropriate other composition (BP, re-selecting the variation range of X) according to actual needs, and the gradual change of X may be linear change, hyperbolic change, Various changes such as index changes.
  • an etch stop layer eg, a change in Ge atomic % may be formed in the SiGe relaxed layer 200 so that the depth of the etch to be performed in the step shown in FIG. 10 can be controlled.
  • the control of the etching depth can be achieved by forming a lamination structure of the relaxation layer/etch stop layer/relaxation layer in the SiGe relaxation layer 200 as needed.
  • a replacement gate structure is formed on the SiGe relaxation layer 200 (dielectric layer 220, replacement gate 230 (shown as polysilicon gate 230, other materials known in the art may also be used), surrounding and covering the dielectric Layer 220 and Si of polysilicon gate 230 have sidewalls 240 and Si have a cap layer).
  • the dielectric layer 220 has a thickness of 1 to 3 nm
  • the polysilicon gate 230 has a thickness of 20 to 70 nm
  • the Si 3 N 4 spacer 240 has a width in the horizontal direction of 10 to 40 nm, Si 3 N 4 .
  • the thickness of the cap layer is 15 to 40 nm.
  • This step is also part of the conventional process where polysilicon gate 230 is formed as an alternative to the metal gate.
  • a source/drain region (not shown) is formed by a conventional method (for example, by performing ion and high temperature annealing).
  • an interlayer dielectric layer is deposited on the SiGe relaxed layer 200 on which the replacement gate structure has been formed.
  • Inter Layer Dielectric layer 250 For example, undoped silicon oxide (SiO 2 ), various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 ) can be used as interlayer dielectric layers. 250 constituent materials.
  • SiO 2 undoped silicon oxide
  • various doped silicon oxides such as borosilicate glass, borophosphosilicate glass, etc.
  • silicon nitride Si 3 N 4
  • the interlayer dielectric layer 250 is subjected to a chemical mechanical planarization (CMP) treatment, thereby exposing the Si cap layer of the replacement gate structure.
  • CMP chemical mechanical planarization
  • an additional CMP process or a reactive ion etching (RIE) process for Si 3 N 4 is performed to remove the Si 3 N 4 cap layer, exposing the polysilicon gate 230 in place of the gate structure.
  • RIE reactive ion etching
  • the polysilicon gate 230 is removed by wet etching or dry etching.
  • the SiGe relaxation layer 200 is etched by wet etching or dry etching to etch a space for Si epitaxial growth (etching depth is 5 to 10 nm).
  • etching depth is 5 to 10 nm.
  • an etch stop layer e.g., changing Ge atom%: may be formed in the SiGe relaxation layer 200, so that the etching depth can be controlled.
  • a high-k dielectric layer 320 is deposited on the surface of the structure shown in FIG. 11, and the deposition thickness is in the range of 1 to 3 nm.
  • the metal layer for constituting the metal gate 330 is deposited on the surface of the high-k dielectric layer 320.
  • the metal layer may include a plurality of conductive layers, for example, a TiN layer is first deposited. A TiAl layer is then deposited.
  • a planarization process (eg, CMP process, etc.) is performed on the formed metal layer and the high-k dielectric layer 320 to remove the high coverage of the top of the interlayer dielectric layer 250 and the Si spacer 240.
  • the K dielectric layer 320 and the metal layer form a metal gate 330.
  • the polysilicon gate 230 as a replacement gate has been completely replaced by the metal gate 330.
  • the semiconductor fabrication process can be performed in a conventional manner, such as forming a source region silicide/drain region silicide, and/or forming a CMOS device or the like.
  • the Si epitaxial layer 260 is formed, thereby avoiding the source/drain annealing treatment in which the strained Si channel is exposed to a high temperature, and the processing steps to be experienced by reducing the strained Si channel, The loss of the Si epitaxial layer 260 is avoided.
  • Figure 18 is a schematic view showing a semiconductor device in which a semiconductor device manufacturing method is completed according to a second embodiment of the present invention.
  • the semiconductor device manufactured according to the process of the second embodiment of the present invention mainly comprises: a substrate 300 (Si wafer, SOI, etc.), a SiGe relaxation layer 200 (Ge atom ° / according to FIG. 18
  • the semiconductor epitaxial layer 260 (shown as the Si epitaxial layer 260, which may also be a Ge epitaxial layer or a SiGe epitaxial layer) (thickness is 5 to 10 nm), high in the direction from bottom to top, from 20% to 100%) K dielectric layer 320 (thickness l ⁇ 3nm), metal gate 330, Si 3 N 4 spacer 240 (width 10 ⁇ 40nm), dielectric layer 250 (thickness 15 ⁇ 50nm), wherein SiGe relaxation layer 200 is formed on the substrate 300; a gate structure composed of the Si spacer 240, the Si epitaxial layer 260, the high K dielectric layer 320, and the metal gate 330 is formed on the SiGe relaxation layer 200; the interlayer dielectric layer
  • the Si epitaxial layer 260 is formed, thereby avoiding the source/drain annealing treatment in which the strained Si channel is exposed to a high temperature, and the processing steps to be experienced by reducing the strained Si channel, The loss of the Si epitaxial layer 260 is avoided.
  • the polysilicon gate 230 has been removed by wet etching or dry etching.
  • Si epitaxial growth is performed directly on the SiGe relaxation layer 200 in the opening surrounded by the Si 3 N 4 spacer 240 to form a top surface of the SiGe relaxation layer 200.
  • the Si epitaxial layer 260 and the Si epitaxial layer 260 have a thickness of 5 to 10 nm.
  • a high-k dielectric layer 320 is deposited on the surface of the structure shown in Fig. 15, and the deposition thickness is in the range of 1 to 3 nm.
  • the metal layer for constituting the metal gate 330 is deposited on the surface of the high-k dielectric layer 320.
  • the metal layer may include a plurality of conductive layers, for example, a TiN layer is first deposited, A TiAl layer is then deposited.
  • a planarization process (eg, CMP process, etc.) is performed on the formed metal layer and the high-k dielectric layer 320, and the interlayer dielectric layer 250 and the Si 3 N 4 sidewall 240 are removed.
  • a top high dielectric layer 320 and a metal layer form a metal gate 330.
  • the polysilicon gate 230 as a replacement gate has been completely replaced by the metal gate 330.
  • the semiconductor fabrication process can be performed in a conventional manner, such as forming a source region silicide/drain region silicide, and/or forming a CMOS device or the like.
  • the Si epitaxial layer 260 is formed, thereby avoiding the source of the strained Si channel being exposed to high temperature.
  • the pole/drain annealing process, and the loss of the Si epitaxial layer 260, is avoided due to the reduced processing steps experienced by the strained Si channel. .

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Description

应变半导体沟道形成方法和半导体器件
技术领域
本发明涉及半导体领域, 尤其涉及半导体器件及其制造方法, 更具体地, 涉及 一种应变半导体沟道形成方法以及利用所述方法制造出的半导体器件。 背景技术
在 SiGe半导体器件中, 大量采用了设置在 SiGe弛豫层上的拉应变 Si层结构。 通常, SiGe弛豫层的组成以 Si1-xGe,的形式表示, xe [0, 1]。
图 1A示出了设置在 SiGe弛豫层上的拉应变 Si层结构的原子晶格示意图,图 1B 示出了设置在 SiGe弛豫层上的拉应变 Si层结构的能级结构。 如图 1B所示, 由于拉 应变 Si层中较大的双轴拉应力, 拉应变 Si层中的导带低于 SiGe弛豫层中的导带。 根据这种结构, 在拉应变 Si层中将获得非常高的电子面内迁移率。
Currie等在 Appl ied Physics Letters (第 72卷, 第 14期, 第 1718-20页, 1998年)中描述了驰豫层的制备方法及其性能(如图 2A〜2D所示)。图 2A示出了 SiGe 弛豫层的纵向 Ge原子百分比分布。 如图 2A所示, Ge原子百分比 (Ge%) 从下至上逐 渐从 0%增加至 100%, 即组成 Si^Gex中的 X从 0逐渐变化为 1。 通过在 Si衬底上生长 超厚(几微米) 的 SiGe层来获得 SiGe弛豫层或 Ge层。 此外, 通过缺陷产生(图 2B) 来释放 SiGe弛豫层中的压应变, 从而获得 SiGe弛豫层或 Ge层。
图 3A、 3B和 3C分别示出了三种传统的应变 Si沟道形成方法, 图 3A示出了应 变 Si/体 SiGe M0SFET (金属氧化物半导体场效应晶体管) 结构, 图 3B示出了 SG0I (SiGe- On - Insulator) M0SFET结构, 图 3C示出了 SSDOI (Strained Si Directly On Insulator) M0SFET结构。
但是,在传统的 Si沟道形成方法中,在器件制造工艺(例如,浅沟槽隔离(STI )、 栅极形成等) 之前, 必须先在 SiGe层 (或埋层氧化物) 上形成应变 Si覆层。 这也导 致了传统的 Si沟道形成方法存在以下问题: (1 ) 在器件制造工艺期间, 应变 Si覆层 可能受到损耗, 例如, STI 工艺中的垫氧化处理、 栅极形成工艺前的牺牲氧化处理、 多种湿法化学清洗处理等, 都可能导致应变 Si覆层发生损耗; (2)应变 Si覆层在高 温步骤中可能发生弛豫 (应力被释放), 例如, 用于激活源极 /漏极掺杂剂的退火处理 可能会导致应变 Si覆层中的应力被释放。 发明内容
考虑到传统工艺的上述缺陷, 本发明提出了一种应变半导体沟道形成方法, 其 中在去除替代栅之后, 形成应变半导体沟道(材料可以选用 Si、 Ge或 SiGe ), 从而避 免了应变半导体沟道暴露于高温的源极 /漏极退火处理, 而且由于减少了应变半导体 沟道所要经历的处理步骤, 避免了半导体层损耗。 此外, 本发明还提出了一种利用所 述方法制造出的半导体器件。
根据本发明的第一方案, 提出了一种应变半导体沟道形成方法, 包括以下步骤: 在半导体衬底上形成 SiGe弛豫层; 在所述 SiGe弛豫层上形成电介质层, 在所述电介 质层上形成替代栅, 所述电介质层和所述替代栅构成了替代栅叠层结构; 沉积层间介 电层, 对所述层间介电层进行平坦化处理, 以暴露出所述替代栅; 刻蚀去除所述替代 栅和所述电介质层, 以形成开口; 在所述开口中执行选择性半导体外延生长, 形成半 导体外延层; 沉积高 κ介电层和金属层; 以及对所沉积的金属层和高 κ介电层执行平 坦化处理, 去除覆盖在所述层间介电层上的高 κ介电层和金属层, 形成金属栅。
优选地, 所述半导体外延层是 Si外延层、 Ge外延层、 或者 SiGe外延层。
优选地, 在去除所述电介质层之后, 外延生长所述半导体外延层之前, 所述应 变半导体沟道形成方法还包括以下步骤: 在所述开口中, 对所述 S iGe 弛豫层进行刻 蚀, 以刻蚀出用于半导体外延生长的空间。
优选地, 所述半导体外延层的厚度在 5〜10nm的范围内。
优选地,所述 SiGe弛豫层中 Ge原子百分比从邻近所述半导体衬底的 20%逐渐变 化为远离所述半导体衬底的 100%。
优选地, 在形成所述 SiGe弛豫层的步骤中, 形成刻蚀停止层。 更优选地, 所述 刻蚀停止层具有与所述 SiGe弛豫层不同的 Ge原子百分比。
根据本发明的第二方案, 提出了一种半导体器件, 包括: 半导体衬底; SiGe弛 豫层, 形成在所述半导体衬底上; 半导体外延层, 形成在所述 SiGe 弛豫层上, 位于 所述 SiGe弛豫层上, 或者嵌入在所述 SiGe弛豫层中; 高 K介电层, 沉积在所述半导 体外延层的整个表面上, 形成为有底面的空心柱形; 和金属栅, 填充在由所述高 K介 电层形成的空心柱形的内部。 .
优选地, 所述半导体外延层是 Si外延层、 Ge外延层、 或者 SiGe外延层。
优选地, 所述半导体外延层的厚度在 5〜10nm的范围内。 优选地, 所述半导体器件还包括: 侧墙, 沉积在所述 SiGe弛豫层上, 围绕所述 半导体外延层和所述高 K介电层的外周, 或者围绕所述高 K介电层的外周; 和层间介 电层, 沉积在所述 SiGe弛豫层上, 围绕所述侧墙的外周。
优选地,所述 SiGe弛豫层中 Ge原子百分比从邻近所述半导体衬底的 20%逐渐变 化为远离所述半导体衬底的 100%。
优选地, 所述 SiGe弛豫层形成有刻蚀停止层。 更优选地, 所述刻蚀停止层具有 与所述 SiGe弛豫层不同的 Ge原子百分比。
根据本发明, 不必在器件制造工艺之前, 先在 SiGe层 (或埋层氧化物) 上形成 应变 Si 覆层, 而是利用替代栅工艺, 在去除替代栅之后, 才形成应变半导体层, 从 而避免了应变半导体沟道暴露于高温的源极 /漏极退火处理, 而且由于减少了应变半 导体沟道所要经历的处理步骤, 避免了应变半导体层的损耗。 附图说明
通过下面结合附图说明本发明的优选实施例, 将使本发明的上述及其它目的、 特征和优点更加清楚, 其中:
图 1A示出了设置在 SiGe弛豫层上的拉应变 Si层结构的原子晶格示意图; 图 1B示出了设置在 SiGe弛豫层上的拉应变 Si层结构的能级结构;
图 2A和 2B是用于说明驰豫层的制备方法及其性能的示意图;
图 3A、 3B和 3C分别示出了三种传统的应变 Si沟道形成方法;
图 4〜14是示出了本发明第一实施例所提出的半导体器件制造方法的各个步骤 的示意图, 其中图 14 示出了根据本发明第一实施例所提出的半导体器件制造方法制 造完成的半导体器件;
图 4〜9和 15〜18是示出了本发明第二实施例所提出的半导体器件制造方法的 各个步骤的示意图, 其中图 18 示出了根据本发明第二实施例所提出的半导体器件制 造方法制造完成的半导体器件。
应当注意的是, 本说明书附图并非按照比例绘制, 而仅为示意性的目的, 因此, 不应被理解为对本发明范围的任何限制和约束。 在附图中, 相似的组成部分以相似的 附图标号标识。 具体实施方式 下面参照附图对本发明的优选实施例进行详细说明, 在描述过程中省略了对于 本发明来说是不必要的细节和功能, 以防止对本发明的理解造成混淆。
【第一实施例】
首先, 参考图 14, 对根据本发明第一实施例所提出的工艺制造的半导体器件进 行详细描述。 图 14是示出了根据本发明第一实施例所提出的半导体器件制造方法制 造完成的半导体器件的示意图。
如图 14所示,根据本发明第一实施例所提出的工艺制造的半导体器件主要包括: 衬底 300 (Si晶片、 S0I等)、 SiGe弛豫层 200 (Ge原子%按照图 14所示从下到上的 方向, 从 20%变化至 100%)、 半导体外延层 260 (图示为 Si外延层 260, 也可以是 Ge^ 外延层或 SiGe外延层) (厚度为 5〜10nm)、 高 K介电层 320 (厚度为 l〜3nm)、 金属 栅 330、 Si 侧墙 240 (宽度为 10〜40nm)、 层间介电层 250 (厚度为 15〜50nm), 其 中 SiGe弛豫层 200形成在衬底 300上; 由 Si3N4侧墙 240、 Si外延层 260、 高 K介电 层 320和金属栅 330构成的栅极结构形成在 SiGe弛豫层 200上; 层间介电层 250沉 积在 SiGe弛豫层 200上, 围绕所述栅极结构的 Si 侧墙 240的外周; Si外延层 260 形成在 SiGe弛豫层 200上, 嵌入在 SiGe弛豫层 200中; 高 K介电层 320沉积在 Si 外延层 260的整个表面上, 且形成为有底面的空心柱形; 金属栅 330填充在由高 K介 电层 320形成的空心柱形的内部; Si3N4侧墙 240形成在 SiGe弛豫层 200上, 围绕高 K 介电层 320的外周。
根据本发明第一实施例, 不必在器件制造工艺之前, 尤其是在形成源区 /漏区之 前, 先在 SiGe弛豫层 200上形成应变 Si覆层, 而是利用替代栅工艺, 在去除替代栅、 形成源区 /漏区之后, 才形成 Si外延层 260, 从而避免了应变 Si沟道暴露于高温的源 极 /漏极退火处理, 而且由于减少了应变 Si沟道所要经历的处理步骤, 避免了 Si外 延层 260的损耗。
接下来, 将结合图 4〜14, 对根据本发明第一实施例的半导体器件制造方法的各 个步骤进行详细描述。
首先, 如图 4所示, 在衬底 300 (Si晶片、 S0I等) 上形成 SiGe弛豫层 200。 在 SiGe弛豫层 200中, Ge原子%, 即 Ge原子的数目占总原子数的百分比, 按照图 4 所示从下到上的方向 (从邻近衬底 300到远离衬底 300的方向), 例如, 从 20%逐渐变 化至 100%, 即组成 5^ 6,中的 X从 0. 2逐渐变化为 1。 在此, SiGe弛豫层 200的组 成的具体数值仅用作示例的目的, 本领域普通技术人员可以根据实际需要选用适当的 其他组成(BP ,重新选定 X的变化范围), X的逐渐变化可以是线性变化、双曲线变化、 指数变化等多种变化形式。 可选地, 结合图 10, 可以在 SiGe弛豫层 200中形成刻蚀 停止层 (例如, 改变 Ge原子%), 从而可以控制在图 10所示的步骤中将要执行的刻蚀 的深度。 具体地讲, 可以根据需要在 SiGe弛豫层 200中形成驰豫层 /刻蚀停止层 /驰 豫层的叠层结构来实现对刻蚀深度的控制。
然后, 如图 5所示, 在 SiGe弛豫层 200上形成替代栅结构 (电介质层 220、 替 代栅 230 (图示为多晶硅栅 230, 也可以选用本领域公知的其他材料)、 围绕和覆盖电 介质层 220和多晶硅栅 230的 Si具侧墙 240和 Si具盖层)。作为本发明的示例, 电介 质层 220的厚度为 l〜3nm, 多晶硅栅 230的厚度为 20〜70nm, Si3N4侧墙 240在图示 水平方向上的宽度为 10〜40nm, Si3N4盖层的厚度为 15〜40nm。 这一步骤同样是传统 工艺的一部分, 这里形成了多晶硅栅 230以作为替代金属栅的替代栅。 可选地, 在上 述形成有替代栅结构的半导体中间结构中, 采用常规方法(例如, 通过进行离子和高 温退火), 来形成源区 /漏区 (图中未示出)。
之后, 如图 6所示, 在已形成替代栅结构的 SiGe弛豫层 200上沉积层间介电层
( Inter Layer Dielectric layer) 250。 例如, 未掺杂的氧化硅 (Si02)、 各种掺杂的 氧化硅 (如硼硅玻璃、 硼磷硅玻璃等) 和氮化硅 (Si3N4) 等可以作为层间介电层 250 的构成材料。
接下来, 如图 7所示, 对层间介电层 250进行化学机械平坦化 (CMP) 处理, 从 而暴露出替代栅结构的 Si具盖层。
然后, 如图 8所示, 执行另外的 CMP处理或针对 Si3N4的反应离子刻蚀 (RIE) 处理, 去除 Si3N4盖层, 暴露出替代栅结构的多晶硅栅 230。
之后, 如图 9所示, 采用湿法刻蚀或干法刻蚀, 去除多晶硅栅 230。
接下来, 如图 10所示, 采用湿法刻蚀或干法刻蚀, 对 SiGe弛豫层 200进行刻 蚀, 以刻蚀出用于 Si外延生长的空间 (刻蚀深度为 5〜10nm)。 可选地, 如之前参考 图 4所述, 可以在 SiGe弛豫层 200中形成刻蚀停止层 (例如, 改变 Ge原子%:), 从而 可以控制刻蚀深度。
然后, 如图 11所示, 在刻蚀形成的开口中, 执行选择性 Si外延生长, 形成嵌 入在 SiGe弛豫层 200中的 Si外延层 260, Si外延层 260的顶面可以与 SiGe弛豫层 200的顶面在同一平面上 (如图 11所示), 也可以不在同一平面上 (未示出)。 之后, 如图 12所示, 在图 11所示的结构的表面上沉积高 K介电层 320, 沉积厚 度在 l〜3nm的范围内。
接下来, 如图 13所示, 在高 K介电层 320的表面上沉积用于构成金属栅 330的 金属层, 根据本发明, 金属层可以包括多层导电层, 例如, 首先沉积 TiN层, 然后再 沉积 TiAl层。
最后, 如图 14所示, 对所形成的金属层和高 K介电层 320执行平坦化处理 (例 如, CMP处理等),去除覆盖在层间介电层 250和 Si 侧墙 240顶部的高 K介电层 320 和金属层, 形成金属栅 330。 在完成这一步骤之后, 作为替代栅的多晶硅栅 230已经 完全被金属栅 330所取代。
此后, 可以按照传统的方法执行半导体制造工艺, 例如形成源区硅化物 /漏区硅 化物, 和 /或形成 CMOS器件等。
根据本发明第一实施例, 不必在器件制造工艺之前, 尤其是在形成源区 /漏区之 前, 先在 SiGe弛豫层 200上形成应变 Si覆层, 而是利用替代栅工艺, 在去除替代栅、 形成源区 /漏区之后, 才形成 Si外延层 260, 从而避免了应变 Si沟道暴露于高温的源 极 /漏极退火处理, 而且由于减少了应变 Si沟道所要经历的处理步骤, 避免了 Si外 延层 260的损耗。
【第二实施例】
首先, 参考图 18, 对根据本发明第二实施例所提出的工艺制造的半导体器件进 行详细描述。 图 18 是示出了根据本发明第二实施例所提出的半导体器件制造方法制 造完成的半导体器件的示意图。
如图 18所示,根据本发明第二实施例所提出的工艺制造的半导体器件主要包括: 衬底 300 (Si晶片、 S0I等)、 SiGe弛豫层 200 (Ge原子 °/。按照图 18所示从下到上的 方向, 从 20%变化至 100%)、 半导体外延层 260 (图示为 Si外延层 260, 也可以是 Ge 外延层或 SiGe外延层) (厚度为 5〜10nm)、 高 K介电层 320 (厚度为 l〜3nm)、 金属 栅 330、 Si3N4侧墙 240 (宽度为 10〜40nm)、 间介电层 250 (厚度为 15〜50nm), 其 中 SiGe弛豫层 200形成在衬底 300上; 由 Si 侧墙 240、 Si外延层 260、 高 K介电 层 320和金属栅 330构成的栅极结构形成在 SiGe弛豫层 200上; 层间介电层 250沉 积在 SiGe弛豫层 200上, 围绕所述栅极结构的 Si3N4侧墙 240的外周; Si外延层 260 位于 SiGe弛豫层 200的顶面上;高 K介电层 320沉积在 Si外延层 260的整个表面上, 且形成为有底面的空心柱形; 金属栅 330填充在由高 K介电层 320形成的空心柱形的 内部; Si3N4侧墙 240形成在 SiGe弛豫层 200上,围绕 Si外延层 260和高 K介电层 320 的外周。
根据本发明第二实施例, 不必在器件制造工艺之前, 尤其是在形成源区 /漏区之 前, 先在 SiGe弛豫层 200上形成应变 Si覆层, 而是利用替代栅工艺, 在去除替代栅、 形成源区 /漏区之后, 才形成 Si外延层 260, 从而避免了应变 Si沟道暴露于高温的源 极 /漏极退火处理, 而且由于减少了应变 Si沟道所要经历的处理步骤, 避免了 Si外 延层 260的损耗。
接下来, 将结合图 4〜9和 15〜18, 对根据本发明第二实施例的半导体器件制造 方法的各个步骤进行详细描述。
图 4〜9的步骤与本发明上述第一实施例相同, 为了行文简洁起见, 这里省略了 对图 4〜9的详细描述, 具体内容可参考第一实施例中的详细描述。
如图 9所示, 多晶硅栅 230已通过湿法刻蚀或干法刻蚀被去除。
接下来, 如图 15所示, 直接在 SiGe弛豫层 200上、 由 Si3N4侧墙 240所环绕的 开口中, 执行选择性 Si外延生长, 形成位于 SiGe弛豫层 200的顶面上的 Si外延层 260, Si外延层 260的厚度为 5〜10nm。
之后, 如图 16所示, 在图 15所示的结构的表面上沉积高 K介电层 320, 沉积厚 度在 l〜3nm的范围内。
接下来, 如图 17所示, 在高 K介电层 320的表面上沉积用于构成金属栅 330的 金属层, 根据本发明, 金属层可以包括多层导电层, 例如, 首先沉积 TiN层, 然后再 沉积 TiAl层。
最后, 如图 18所示, 对所形成的金属层和高 K介电层 320执行平坦化处理 (例 如, CMP处理等),去除覆盖在层间介电层 250和 Si3N4侧墙 240顶部的高 K介电层 320 和金属层, 形成金属栅 330。 在完成这一步骤之后, 作为替代栅的多晶硅栅 230已经 完全被金属栅 330所取代。
此后, 可以按照传统的方法执行半导体制造工艺, 例如形成源区硅化物 /漏区硅 化物, 和 /或形成 CMOS器件等。
根据本发明第二实施例, 不必在器件制造工艺之前, 尤其是在形成源区 /漏区之 前, 先在 SiGe弛豫层 200上形成应变 Si覆层, 而是利用替代栅工艺, 在去除替代栅、 形成源区 /漏区之后, 才形成 Si外延层 260, 从而避免了应变 Si沟道暴露于高温的源 极 /漏极退火处理, 而且由于减少了应变 Si沟道所要经历的处理步骤, 避免了 Si外 延层 260的损耗。 .
至此已经结合优选实施例对本发明进行了描述。 应该理解, 本领域技术人员在 不脱离本发明的精神和范围的情况下, 可以进行各种其它的改变、替换和添加。 因此, 本发明的范围不局限于上述特定实施例, 而应由所附权利要求所限定。

Claims

权 利 要 求
1. 一种应变半导体沟道形成方法, 包括以下步骤: - 在半导体衬底上形成 SiGe弛豫层;
在所述 SiGe弛豫层上形成电介质层, 在所述电介质层上形成替代栅, 所述电介 质层和所述替代栅构成了替代栅叠层结构;
沉积层间介电层, 对所述层间介电层进行平坦化处理, 以暴露出所述替代栅; 刻蚀去除所述替代栅和所述电介质层, 以形成开口;
在所述开口中执行选择性半导体外延生长, 形成半导体外延层;
沉积高 κ介电层和金属层; 以及
对所沉积的金属层和高 κ介电层执行平坦化处理, 去除覆盖在所述层间介电层 上的高 κ介电层和金属层, 形成金属栅。
2. 根据权利要求 1所述的应变半导体沟道形成方法, 其中
所述半导体外延层是 Si外延层、 Ge外延层、 或者 SiGe外延层。
3. 根据权利要求 1或 2所述的应变半导体沟道形成方法,在去除所述电介质 层之后, 外延生长所述半导体外延层之前, 还包括以下步骤:
在所述开口中, 对所述 SiGe弛豫层进行刻蚀, 以刻蚀出用于半导体外延生长的 空间。
4. 根据权利要求 1〜3之一所述的应变半导体沟道形成方法, 其中 所述半导体外延层的厚度在 5〜10nm的范围内。
5. 根据权利要求 1〜4之一所述的应变半导体沟道形成方法, 其中 所述 SiGe弛豫层中 Ge原子百分比从邻近所述半导体衬底的 20%逐渐变化为远离 所述半导体衬底的 100%。
6. 根据权利要求 1〜5之一所述的应变半导体沟道形成方法, 其中 在形成所述 SiGe弛豫层的步骤中, 形成刻蚀停止层。
7. 根据权利要求 6所述的应变半导体沟道形成方法, 其中
所述刻蚀停止层具有与所述 SiGe弛豫层不同的 Ge原子百分比。
8. 一种半导体器件, 包括:
半导体衬底;
SiGe弛豫层, 形成在所述半导体衬底上; 半导体外延层, 形成在所述 SiGe弛豫层上, 位于所述 SiGe弛豫层上, 或者嵌 入在所述 SiGe弛豫层中;
高 K介电层, 沉积在所述半导体外延层的整个表面上, 形成为有底面的空心柱 形; 和
金属栅, 填充在由所述高 K介电层形成的空心柱形的内部。
9. 根据权利要求 8所述的半导体器件, 其中
所述半导体外延层是 Si外延层、 Ge外延层、 或者 SiGe外延层。
10. 根据权利要求 8或 9所述的半导体器件, 其中
所述半导体外延层的厚度在 5〜10nm的范围内。
11. 根据权利要求 8〜10之一所述的半导体器件, 还包括:
侧墙, 沉积在所述 SiGe弛豫层上, 围绕所述半导体外延层和所述高 K介电层的 外周, 或者围绕所述高 K介电层的外周; 和
层间介电层, 沉积在所述 SiGe弛豫层上, 围绕所述侧墙的外周。
12. 根据权利要求 8〜11之一所述的半导体器件, 其中
所述 SiGe弛豫层中 Ge原子百分比从邻近所述半导体衬底的 20%逐渐变化为远离 所述半导体衬底的 100%。
13. 根据权利要求 8〜12之一所述的半导体器件, 其中
所述 SiGe弛豫层形成有刻蚀停止层。
14. 根据权利要求 13所述的半导体器件, 其中
所述刻蚀停止层具有与所述 SiGe弛豫层不同的 Ge原子百分比。
PCT/CN2010/001436 2010-08-04 2010-09-19 应变半导体沟道形成方法和半导体器件 WO2012016361A1 (zh)

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