WO2014071665A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014071665A1
WO2014071665A1 PCT/CN2012/085817 CN2012085817W WO2014071665A1 WO 2014071665 A1 WO2014071665 A1 WO 2014071665A1 CN 2012085817 W CN2012085817 W CN 2012085817W WO 2014071665 A1 WO2014071665 A1 WO 2014071665A1
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Prior art keywords
semiconductor layer
substrate
layer
fin
dielectric material
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PCT/CN2012/085817
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English (en)
French (fr)
Inventor
朱慧珑
许淼
梁擎擎
尹海洲
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中国科学院微电子研究所
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Priority to US14/434,437 priority Critical patent/US9349867B2/en
Publication of WO2014071665A1 publication Critical patent/WO2014071665A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • a relatively high threshold voltage region may be formed in the substrate under the fin to reduce source leakage leakage.
  • such relatively high threshold voltage regions can include relatively highly doped regions, or punch-through stoppers.
  • Such a punch-through barrier may be formed by ion implantation into a substrate below the fin after forming the fin. For example, for an n-type device, p-injection can be performed; for a p-type device, n-injection can be performed.
  • a protective layer 1006 may be formed on the second semiconductor layer 1004.
  • the protective layer 1006 may, for example, comprise an oxide (e.g., silicon oxide) having a thickness of about 10-50 nm. This protective layer 1006 protects the ends of the fins in subsequent processing.
  • the etching step of forming the fins enters into the substrate 1000; then, by the operation in FIG. 3, the contact area between the p-type well and the n-type well can be made (ie, The area of the formed pn junction is small.
  • the present disclosure is not limited thereto.
  • the etching of the first semiconductor layer 1002 in FIG. 2 may stop at the substrate 1000, and then not It is also feasible to etch the substrate 1000; the operation shown in Figure 3 may not be necessary.
  • the shape of the groove (between the fins) formed by etching is not necessarily the regular rectangular shape shown in Fig. 2, and may be, for example, a frustum shape which gradually becomes smaller from top to bottom.
  • the position and number of fins formed are not limited to the example shown in FIG. 2.
  • an isolation layer is first formed on the substrate.
  • Such an isolation layer can be formed, for example, by depositing a dielectric material on the substrate and then performing etch back. During the etch back process, the etch back depth is controlled such that the etched back spacer layer exposes a portion of the first semiconductor layer (the top surface of the spacer layer is between the top surface and the bottom surface of the first semiconductor layer).
  • the isolation layer can include a high density plasma (HDP) oxide (e.g., silicon oxide).
  • HDP high density plasma
  • a sacrificial gate stack across the fins can be formed over the isolation layer 1014.
  • this can be done as follows. Specifically, as shown in Fig. 9 (Fig. 9(b) shows a cross-sectional view taken along line BB' in Fig. 9(a)), a sacrificial gate dielectric layer 1016 is formed, for example, by deposition.
  • the sacrificial gate dielectric layer 1016 can include an oxide having a thickness of about 0.8-1.5 nm. In the example shown in Fig. 7, only the " ⁇ " shaped sacrificial gate dielectric layer 1016 is shown.
  • the sacrificial gate dielectric layer 1016 may also include portions that extend over the top surface of the isolation layer 1014. Then, the sacrificial gate conductor layer 1018 is formed, for example, by deposition.
  • the sacrificial gate conductor layer 1018 can comprise polysilicon.
  • the sacrificial gate conductor layer 1018 can fill the gap between the fins and can be planarized, such as chemical mechanical polishing (CMP). Thereafter, the sacrificial gate conductor layer 1018 is patterned to form a gate stack.
  • the sacrificial gate conductor layer 1018 is patterned into a strip that intersects the fins.
  • the patterned sacrificial gate conductor layer 1018 can also be patterned to further pattern the sacrificial gate dielectric layer 1016.
  • the dielectric layer portion 1020-1 may have a surface which is substantially the same as the underlying structure because of its relatively thin thickness. However, in Fig. 9(a), the appearance of the surface of the dielectric layer portion 1020-1 is not shown for the sake of convenience.
  • the second semiconductor layer 1004 exposed due to the removal of the sacrificial gate dielectric layer 1016 can be selectively removed (e.g., RIE). Due to the presence of the sacrificial gate stack (sacrificial gate dielectric layer, sacrificial gate conductor and sidewall spacers), the second semiconductor layer 1004 can remain below the sacrificial gate stack. As a result, the first semiconductor layer 1002 is exposed.
  • RIE reactive etching
  • Fig. 12(b) shows a cross-sectional view taken along line BB' in Fig. 12(a)
  • Fig. 12(c) shows a line along CC' in Fig. 12(a)
  • the cross-sectional view may selectively etch the first semiconductor layer 1002 (eg, SiGe) with respect to the second semiconductor layer 1004 and the substrate (eg, Si) to remove the first semiconductor layer.
  • the first semiconductor layer 1002 eg, SiGe
  • the substrate eg, Si
  • a void is formed just below the second semiconductor layer 1004.
  • an opening is left in the spacer which exposes the substrate 1000 (in this example, the through barrier 1038 is exposed).
  • a dielectric may be filled in the void formed under the second semiconductor layer 1004 to form the isolation island 1032.
  • a dielectric material e.g., oxide
  • a dielectric material may be deposited and then etched back to expose the sidewalls of the fins (i.e., the second semiconductor layer 1004) (and preferably expose the surface of the substrate 1000).
  • a dielectric material is filled between the second semiconductor layer 1004 and the substrate 1000 to obtain an isolation island 1032.
  • the third semiconductor layer 1034 may include a material different from the second semiconductor layer 1004 so as to be capable of applying stress to the second semiconductor layer 1004 in which the channel forming the device is to be formed.
  • the third semiconductor layer 1034 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress.
  • the second semiconductor layer 1004 together with the third semiconductor layer 1034 on both sides thereof, constitutes the "fin" of the final device.
  • a channel may be formed in the second semiconductor layer 1004 under the gate stack, and a source/drain region may be formed in the third semiconductor layer 1034.
  • an island 1032 may be formed between the bottom of the fin and the source and drain regions. This isolated island can greatly reduce the leakage current between the source and drain via the bottom of the fin.
  • the p-type device on n-well 1000-1 can be subjected to the operations described above in connection with Figures 11-14.
  • the difference is that the third semiconductor layer 1042 may be doped in-situ as p-type, and may include SiGe (e.g., an atomic percentage of Ge is about 15-75%) to apply compressive stress.
  • a replacement gate process can be performed to replace the sacrificial gate stack to form a true gate stack of the final device. For example, this can be done as follows.
  • a final gate stack is formed by forming a gate dielectric layer 1026 and a gate conductor layer 1028 in the voids 1024.
  • the gate dielectric layer 1026 can comprise a high K gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • Gate conductor layer 1028 can include a metal gate conductor.
  • a function adjustment layer (not shown) can also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024.
  • the n-type device and the p-type device are separately processed, so that the dielectric layer portion 1020-1 shields the left p-type device region in the above operation, and The n-type device area on the right side is exposed.
  • the present disclosure is not limited thereto.
  • such masking may not be performed.
  • the p-type device region is masked first to process the n-type device region.
  • this publication is not limited to this. The order in which the n-type device region and the p-type device region are processed can be exchanged.

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Abstract

提供一种半导体器件及其制造方法。该方法包括：在衬底（1000）上依次形成第一半导体层（1002）和第二半导体层（1004）；对第二半导体层、第一半导体层进行构图，以形成鳍；在衬底上形成隔离层（1014），该隔离层露出第一半导体层的一部分；向鳍下方的衬底进行离子注入，以形成穿通阻挡部（1038），在隔离层上形成横跨鳍的栅堆叠；以栅堆叠为掩模，选择性刻蚀第二半导体层，以露出第一半导体层；选择性刻蚀第一半导体层，以在第二半导体层下方形成空隙；在衬底上形成第三半导体层（1034），用以形成源/漏区。

Description

半导体器件及其制造方法
本申请要求了 2012年 11月 9日提交的、 申请号为 201210448686.1、 发明名称为
"半导体器件及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在 本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。 背景技术
随着平面型半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提出了立 体型半导体器件如 FinFET (鰭式场效应晶体管）。 一般而言， FinFET包括在衬底上竖 直形成的鰭以及与鰭相交的栅堆叠。 另外， 衬底上形成有隔离层， 以隔离栅堆叠与衬 底。 因此， 鰭的底部被隔离层所包围， 从而栅难以有效控制鰭的底部。 结果， 易于出 现源和漏之间经由鰭底部的漏电流。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬底上依 次形成第一半导体层和第二半导体层； 对第二半导体层、 第一半导体层进行构图， 以 形成鰭； 在衬底上形成隔离层， 所述隔离层露出所述第一半导体层的一部分； 向鰭下 方的衬底进行离子注入， 以形成穿通阻挡部； 在隔离层上形成横跨鰭的栅堆叠； 以栅 堆叠为掩模， 选择性刻蚀第二半导体层， 以露出第一半导体层； 选择性刻蚀第一半导 体层， 以在第二半导体层下方形成空隙； 在衬底上形成第三半导体层， 用以形成源 / 漏区。
根据本公开的另一方面， 提供了一种半导体器件， 包括： 在衬底上形成的鰭； 在 鰭下方的衬底中形成的穿通阻挡部； 在衬底上形成的隔离层； 以及在隔离层上形成的 横跨鰭的栅堆叠， 其中， 所述鰭包括位于栅堆叠下方的第一半导体层部分以及与第一 半导体层相邻的第二半导体层部分， 该半导体器件还包括形成于第二半导体层部分中 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和 优点将更为清楚， 在附图中：
图 1-18是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是示例性 的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知结构和技术的 描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。 这些图并非是按比例绘制 的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些细节。 图中所 示出的各种区域、 层的形状以及它们之间的相对大小、 位置关系仅是示例性的， 实际 中可能由于制造公差或技术限制而有所偏差， 并且本领域技术人员根据实际所需可以 另外设计具有不同形状、 大小、 相对位置的区域 /层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该层 /元件 可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外， 如果在 一种朝向中一层 /元件位于另一层 /元件"上"， 那么当调转朝向时， 该层 /元件可以位于 该另一层 /元件 "下"。
根据本公开的实施例， 可以在鰭下方的衬底中形成相对高阈值电压区， 以减小源 漏泄漏。 例如， 这种相对高阈值电压区可以包括相对高掺杂的区域， 或者说穿通阻挡 部 （punch-through stopper )。 这种穿通阻挡部可以在形成鰭之后， 向鰭下方的衬底中 进行离子注入来形成。 例如， 对于 n型器件， 可以进行 p注入； 对于 p型器件， 可以进 行 n注入。
由于离子注入， 在鰭 （特别是靠近离子注入区域的鰭底部） 中， 可能存在相对高 的杂质浓度， 这又将导致鰭中随机掺杂波动变大， 从而使器件性能变差。 根据本公开 的实施例， 可以如此形成鰭， 使得其包括牺牲层和鰭主体层的堆叠， 其中牺牲层位于 鰭底部。 在进行用于形成穿通阻挡部的离子注入之后， 可以选择性去除潜在地被离子 注入所污染的牺牲层。 因此， 可以降低鰭中随机掺杂波动， 并进一步改善器件性能。 根据本公开的另一实施例， 为了进一步减小源漏泄漏， 还可以在如上所述去除牺 牲层之后， 在鰭底部， 在源和漏之间形成隔离岛， 以减小源、 漏之间经由鰭底部的漏 电流。 例如， 在去除牺牲层之后， 可以在鰭主体层下方填充电介质材料， 并将电介质 材料构图为隔离岛。
由于希望隔离岛位于源、 漏之间， 从而在构图隔离岛时， 可以栅堆叠为掩模。 具 体地， 在构图牺牲层和鰭主体层形成鰭之后， 可以在衬底上形成隔离层， 并在隔离层 上形成横跨鰭的 （牺牲） 栅堆叠。 在此， 隔离层露出牺牲层的一部分。 这是因为隔离 层限定了鰭的 "底部"。 然后， 可以 （牺牲）栅堆叠为掩模， 选择性刻蚀鰭主体层 （从 而鰭主体层留于栅堆叠下方）， 以露出牺牲层。 接着， 可以选择性刻蚀牺牲层， 以去 除牺牲层 （例如， 牺牲层可以全部去除）。 这样， 就在鰭主体层下方形成了空隙。 随 后， 可以淀积电介质材料， 并 （以栅堆叠为掩模） 回蚀， 使得电介质材料填充鰭主体 层下方的空隙， 从而形成隔离岛。
另一方面， 在如上所述去除牺牲层之后， 隔离层中形成了一与鰭的形状相对应的 开口， 该开口露出一部分衬底。 随后可以通过该开口， 在衬底上例如通过外延来形成 源漏区。
根据本公开的另一实施例， 形成的源 /漏区可以包括与鰭主体层不同的半导体材 料， 从而由于两者之间的晶格失配而能够在鰭主体层（其中形成沟道区）中施加应力， 以进一步提升器件性能。
根据本公开的实施例， 隔离层可以通过在衬底上淀积电介质材料然后回蚀来形 成。 可以如此形成电介质材料， 使得电介质材料基本上覆盖鰭时 （即， 在多个鰭的情 况下基本上填充鰭之间的间隙时）， 位于鰭顶部的电介质材料厚度充分小于位于衬底 上的电介质材料厚度， 例如鰭顶部的电介质材料厚度可以小于位于衬底上的电介质材 料厚度的三分之一， 优选为四分之一。 例如， 这可以通过高密度等离子体 （HDP) 淀 积来实现。 另外， 在形成多个鰭的情况下， 位于每一鰭的顶面之上的电介质材料的厚 度可以小于与其相邻的鰭之间间距的二分之一。 这样， 在随后的回蚀中， 可以减少刻 蚀深度， 从而能够增加刻蚀控制精度。
本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如但不限于 体半导体材料衬底如体 Si衬底、 绝缘体上半导体 （SOI) 衬底、 SiGe衬底等。 在以下 的描述中， 为方便说明， 以体 Si衬底为例进行描述。 在衬底 1000中， 可以形成 n型阱 1000-1和 p型阱 1000-2， 以供随后在其中分别形成 p 型器件和 n型器件。 例如， n型阱 1000-1可以通过在衬底 1000中注入 n型杂质如 P或 As来 形成， p型阱 1000-2可以通过在衬底 1000中注入 p型杂质如 B来形成。 如果需要， 在注 入之后还可以进行退火。 本领域技术人员能够想到多种方式来形成 n型阱、 p型阱， 在 此不再赘述。
这里需要指出的是， 尽管在以下描述中说明了分别在 n型阱和 p型阱中形成互补器 件的工艺， 但是本公开不限于此。 例如， 本公开同样适用于非互补工艺。 而且， 以下 涉及互补器件的一些处理， 在某些实现方式中并非是必须的。
在衬底 1000上， 例如通过外延生长， 形成第一半导体层 1002。 例如， 第一半导体 层 1002可以包括 SiGe ( Ge原子百分比例如为约 5-20%)， 厚度为约 10-50nm。 接下来， 在第一半导体层 1002， 例如通过外延生长， 形成第二半导体层 1004。 例如， 第二半导 体层 1004可以包括 Si， 厚度为约 20-100nm。
根据本公开的一示例，在第二半导体层 1004上，可以形成保护层 1006。保护层 1006 例如可以包括氧化物 （例如， 氧化硅）， 厚度为约 10-50nm。 这种保护层 1006可以在随 后的处理中保护鰭的端部。
随后，可以对如此形成的第二半导体层 1004、第一半导体层 1002和衬底进行构图， 以形成鰭。 例如， 这可以如下进行。 具体地， 在保护层 1006上按设计形成构图的光刻 胶 1008。 通常， 光刻胶 1008被构图为一系列平行的等间距线条。 然后， 如图 2所示， 以构图的光刻胶 1008为掩模， 依次选择性刻蚀例如反应离子刻蚀（RIE)保护层 1006、 第二半导体层 1004、 第一半导体层 1002和衬底 1000， 从而形成鰭。
在互补工艺的情况下， 还可以如图 3所示， 来在 n型区域和 p型区域之间形成隔离。 具体地， 可以在衬底上形成光刻胶 1010， 并对光刻胶 1010进行构图， 以露出 n型区域 和 p型区域之间界面周围的一定区域。 然后， 通过选择性刻蚀例如 RIE， 去除该区域存 在的保护层、 第二半导体层、 第一半导体层。 也可以进一步选择性刻蚀如 RIE衬底。 从而在 n型区域和 p型区域之间形成隔离地带， 该隔离地带随后可以被电介质所填充。 然后， 可以去除光刻胶 1010。
可以看到， 在图 2的操作中， 形成鰭的刻蚀步骤进入到衬底 1000中； 然后， 通过 图 3中的操作， 可以使得 p型阱和 n型阱之间的接触面积 （即， 形成的 pn结的面积） 较 小。 但是， 本公开不限于此。 例如， 在非互补工艺， 或者在单一类型 （p型或 n型） 器 件的局部区域， 图 2中对第一半导体层 1002的刻蚀可以停止于衬底 1000， 并且随后不 再对衬底 1000进行刻蚀也是可行的； 图 3所示的操作可能也并非是必须的。 通过刻蚀 所形成的 （鰭之间的） 沟槽的形状不一定是图 2中所示的规则矩形形状， 可以是例如 从上到下逐渐变小的锥台形。 另外， 所形成的鰭的位置和数目不限于图 2所示的示例。
在图 2所示的示例中， 在 n型阱 1000-1和 p型阱 1000-2之间的界面处， 也形成了鰭。 由于图 3所示的隔离形成工艺， 该鰭也被去除。 于是， 得到了图 4所示的结构。
在通过上述处理形成鰭之后， 可以形成横跨鰭的栅堆叠， 并形成最终的半导体器 件。
为了隔离栅堆叠和衬底， 在衬底上首先形成隔离层。 这种隔离层例如可以通过在 衬底上淀积电介质材料， 且然后进行回蚀来形成。 在回蚀过程中， 控制回蚀深度， 使 得回蚀后的隔离层能够使第一半导体层的一部分露出 （隔离层的顶面位于第一半导体 层的顶面和底面之间）。 例如， 隔离层可以包括高密度等离子体 （HDP) 氧化物 （例 如， 氧化硅）。
在此， 为了改善回蚀之后隔离层 （顶面的） 高度的一致性， 并因此改善最终形成 的鰭的高度的一致性， 如图 5所示， 在淀积电介质材料 1014的过程中， 使得电介质材 料 1014基本上覆盖鰭 （在多个鰭的情况下， 基本上填充鰭之间的间隙）。 根据本公开 的实施例， 可以如此淀积， 使得鰭顶部的电介质材料厚度充分小于位于衬底上的电介 质材料厚度， 并且一般来说鰭顶部的电介质材料厚度都小于位于衬底上的电介质材料 厚度的三分之一， 优选为四分之一。 例如， 每一鰭顶部的电介质材料厚度一般不大于 20nm, 而位于衬底上的电介质材料厚度可达 lOOnm左右。
根据本公开的一示例， 电介质材料 1014可以包括通过高密度等离子体 （HDP) 淀 积形成的氧化物 （例如， 氧化硅）。 由于 HDP的特性， 在淀积过程中可以使得鰭顶部 的电介质材料 （沿垂直于衬底方向的） 厚度和鰭侧面的电介质材料 （沿平行于衬底的 方向， 即横向的） 厚度要小于鰭之间衬底上的电介质材料 （沿垂直于衬底方向的） 厚 度。 因为 HDP的这种特性， 在常规技术中通常并不采用 HDP淀积来制作氧化隔离。
在此，例如可以通过控制淀积条件， 使得电介质材料 1014在基本上覆盖鰭时（S卩， 基本上填充鰭之间的空隙时）， 位于每一鰭顶部上的厚度可以小于与其相邻的鰭之间 间距的二分之一。 如果鰭之间的间距并不相同， 则可以使电介质材料 1014位于每一鰭 顶部的厚度小于与其相邻的鰭之间间距中较小间距的二分之一。
随后， 如图 6所示， 对电介质材料 1014进行回蚀。 由于电介质材料 1014的回蚀深 度相对较小， 从而对该刻蚀的控制相对容易， 并因此可以更加精确地控制从鰭的顶面 (在该示例中， 第二半导体层 1004的顶面） 到隔离层 1014的顶面的距离 （至少部分地 决定最终器件的鰭高度并因此决定最终器件的沟道宽度）， 使得该距离在衬底上基本 保持一致。
在一个示例中，保护层 1006和电介质材料 1014包括相同的材料， 如氧化物。因此， 在对电介质材料 1014回蚀的过程中， 可能同时去除了保护层 1006， 如图 6所示。
在此， 为了改善器件性能， 优选地在鰭下方的衬底中形成穿通阻挡部 1038。 具体 地， 如图 7所示， 可以利用光刻胶 1012-1覆盖 n型阱 1000-1上方， 然后进行离子注入。 注入的离子会经由隔离层 1014而扩散到被隔离层 1014所围绕的衬底中。 对于 p型阱 1000-2中要形成的 n型器件， 可以注入 p型杂质， B、 BF2或 In。 注入的峰值浓度例如 可以是约 lE18 - 2E19 cm_3。 可以进行退火， 以激活注入的杂质。 然后可以去除光刻胶 1012-1。
同样地， 如图 8所示， 可以利用光刻胶 1012-2覆盖 p型阱 1000-2上方， 然后进行（倾 斜） 离子注入。 对于 n型阱 1000-1中要形成的 p型器件， 可以注入 n型杂质， 如 As或 Sb。 注入的峰值浓度例如可以是约 lE18 - 2E19 cm_3。 可以进行退火， 以激活注入的杂质。 然后可以去除光刻胶 1012-2。
这里需要指出的是， 尽管在图 7和 8中， 将穿通阻挡部 1038示出为仅形成于衬底 1000中， 但是事实上其可能进入第一半导体层 1002中。
随后， 可以在隔离层 1014上形成横跨鰭的牺牲栅堆叠。 例如， 这可以如下进行。 具体地， 如图 9所示 （图 9 (b) 示出了沿图 9 (a) 中 BB'线的截面图）， 例如通过 淀积， 形成牺牲栅介质层 1016。 例如， 牺牲栅介质层 1016可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 7所示的示例中， 仅示出了 "Π"形的牺牲栅介质层 1016。 但是， 牺牲 栅介质层 1016也可以包括在隔离层 1014的顶面上延伸的部分。 然后， 例如通过淀积， 形成牺牲栅导体层 1018。例如，牺牲栅导体层 1018可以包括多晶硅。牺牲栅导体层 1018 可以填充鰭之间的间隙， 并可以进行平坦化处理例如化学机械抛光 （CMP)。 之后， 对牺牲栅导体层 1018进行构图， 以形成栅堆叠。 在图 9的示例中， 牺牲栅导体层 1018 被构图为与鰭相交的条形。 根据另一实施例， 还可以构图后的牺牲栅导体层 1018为掩 模， 进一步对牺牲栅介质层 1016进行构图。
接下来， 如图 10所示 （图 10 (b) 示出了沿图 10 (a) 中 BB'线的截面图）， 可以在 隔离层上形成电介质层 （例如， 厚度约为 5-30nm的氮化物）， 通过光刻胶覆盖 n型阱 1000-1上方的电介质层部分 1020-1， 并对 p型阱 1000-2上方的电介质层部分进行构图， 以形成侧墙 1020-2。 随后， 去除光刻胶。 本领域技术人员知道多种方式来形成这种侧 墙， 在此不再赘述。
这里需要指出的是， 电介质层部分 1020-1由于其厚度相对较薄， 因此其表面可能 呈现基本上与之下的结构相同的形貌。 但是， 在图 9 (a) 中， 为了方便起见， 并没有 示出电介质层部分 1020-1表面的形貌。
在鰭之间的沟槽为从上到下逐渐变小的锥台形时 （由于刻蚀的特性， 通常为这样 的情况）， 侧墙 1020-2基本上不会形成于鰭的侧壁上。
然后， 如图 11所示 （图 11 (b) 示出了沿图 11 ( a) 中 BB'线的截面图， 图 11 (c) 示出了沿图 11 (a) 中 CC'线的截面图）， 首先选择性去除 （例如， RIE) 暴露在外的牺 牲栅介质层 1016。 在牺牲栅介质层 1016和隔离层 1014均包括氧化物的情况下， 由于牺 牲栅介质层 1016较薄， 因此对牺牲栅介质层 1016的 RIE基本上不会影响隔离层 1014。 在以上形成牺牲栅堆叠的过程中， 以牺牲栅导体为掩模进一步构图牺牲栅介质层的情 况下， 不再需要该操作。
然后， 可以选择性去除 （例如， RIE) 由于牺牲栅介质层 1016的去除而露出的第 二半导体层 1004。 由于牺牲栅堆叠 （牺牲栅介质层、 牺牲栅导体和侧墙） 的存在， 第 二半导体层 1004可以留于牺牲栅堆叠下方。 结果， 露出了第一半导体层 1002。
接下来， 如图 12所示 （图 12 (b)示出了沿图 12 (a) 中 BB'线的截面图， 图 12 (c) 示出了沿图 12 (a) 中 CC'线的截面图）， 可以相对于第二半导体层 1004和衬底 （例如， Si), 选择性刻蚀第一半导体层 1002 (例如， SiGe)， 以去除第一半导体层。 这样， 就 在第二半导体层 1004下方形成了空隙。 此外， 在隔离层中留下了开口， 该开口露出衬 底 1000 (在该示例中， 露出穿通阻挡部 1038)。
为了进一步改善器件性能， 如图 13所示 （图 13 (b) 示出了沿图 13 (a) 中 BB'线 的截面图， 图 13 (c) 示出了沿图 13 (a) 中 CC'线的截面图）， 可以向在第二半导体层 1004下方形成的空隙中填充电介质， 以形成隔离岛 1032。 具体地， 可以淀积电介质材 料 （例如， 氧化物）， 然后回蚀， 以露出鰭 （即， 第二半导体层 1004) 的侧壁 （且优 选地露出衬底 1000的表面）。结果，将电介质材料填充在第二半导体层 1004与衬底 1000 之间， 得到隔离岛 1032。
之后， 如图 14所示， 例如通过外延， 在衬底上形成第三半导体层 1034。 随后可以 在该第三半导体层 1034中形成源 /漏区。 由于隔离层和侧墙的存在， 第三半导体层 1034 基本上从第二半导体层 1004的侧壁 （图 12 (a) 中上、 下两侧的侧壁） 延伸。 根据本 公开的一实施例， 可以在生长第三半导体层 1034的同时， 对其进行原位掺杂。 例如， 对于在 p型阱 1000-2上形成的 n型器件， 可以进行 n型原位掺杂。 另外， 为了进一步提升 性能， 第三半导体层 1034可以包括不同于第二半导体层 1004的材料， 以便能够向第二 半导体层 1004 (其中将形成器件的沟道） 施加应力。 例如， 在第二半导体层 1004包括 Si的情况下， 第三半导体层 1034可以包括 Si:C (C的原子百分比例如为约 0.2-2%)， 以 施加拉应力。
这样， 第二半导体层 1004连同其两侧的第三半导体层 1034—起构成了最终器件的 "鰭"。 在该鰭中， 位于栅堆叠下方的第二半导体层 1004中可以形成沟道， 而第三半 导体层 1034中可以形成源 /漏区。另外，在鰭底部、源漏区之间，可以形成有隔离岛 1032。 这种隔离岛可以大大降低源漏之间经由鰭底部的漏电流。
这里需要指出的是， 如果牺牲栅导体 1018包括多晶硅， 那么在外延时， 牺牲栅导 体 1018上可能也会生长部分第三半导体层。 这例如可以在随后的平坦化处理、 替代栅 处理等后继工艺中去除。 这里为方便起见， 没有示出该部分。 另外， 可以不形成隔离 岛， 而直接生长第三半导体层。 这样， 第二半导体层 1004在底部也通过第三半导体层 与衬底相连。
在如上所述对 p型阱 1000-2上的 n型器件进行处理之后， 同样可以对 n型阱 1000-1上 的 p型器件进行处理。
具体地， 如图 15所示， 可以淀积另一电介质层 1036 (例如， 氧化物）， 然后进行 平坦化处理如 CMP， 以露出 n型阱 1000-1上的电介质层部分 1020-1。然后， 可以对电介 质层部分 1020-1进行 RIE， 以形成侧墙 1020-1。
之后， 可以对 n型阱 1000-1上的 p型器件进行以上结合图 11-14描述的操作。 不同之 处在于： 第三半导体层 1042可以原位掺杂为 p型， 且可以包括 SiGe (例如， Ge的原子 百分比为约 15-75%)， 以施加压应力。
如图 15 (c) 所示， 对于该 p型器件， 鰭同样包括第二半导体层 1004连同其两侧的 第三半导体层 1042。在该鰭中，位于栅堆叠下方的第二半导体层 1004中可以形成沟道， 而第三半导体层 1042中可以形成源 /漏区。 另外， 在鰭底部、 源漏区之间， 可以形成有 隔离岛 1040。 这种隔离岛可以大大降低源漏之间经由鰭底部的漏电流。
在如上所述分别形成 n型器件和 p型器件的源 /漏区之后， 可以进行替代栅工艺， 以 替代牺牲栅堆叠， 形成最终器件的真正栅堆叠。 例如， 这可以如下进行。
如图 16所示 （图 16 (b) 示出了沿图 16 (a) 中 BB'线的截面图， 图 16 (c) 示出了 沿图 16 (a) 中 CC'线的截面图）， 例如通过淀积， 形成电介质层 1022。 该电介质层 1022 例如可以包括氧化物。 随后， 对该电介质层 1022进行平坦化处理例如 CMP。 该 CMP 可以停止于侧墙 1020-1、 1020-2, 从而露出牺牲栅导体 1018。
随后， 如图 17 (图 17 (b) 示出了沿图 17 (a) 中 BB'线的截面图， 图 17 (c) 示出 了沿图 17 (a) 中 CC'线的截面图） 所示， 例如通过 TMAH溶液， 选择性去除牺牲栅导 体 1018， 从而在侧墙 1020-1、 1020-2内侧形成了空隙 1024。 根据另一示例， 还可以进 一步去除牺牲栅介质层 1016。
然后， 如图 18 (图 18 (b) 示出了沿图 18 (a) 中 BB'线的截面图， 图 18 (c) 示出 了沿图 18 (a) 中 CC'线的截面图） 所示， 通过在空隙 1024中形成栅介质层 1026和栅导 体层 1028， 形成最终的栅堆叠。 栅介质层 1026可以包括高 K栅介质例如 Hf02， 厚度为 约 l-5nm。 栅导体层 1028可以包括金属栅导体。 优选地， 在栅介质层 1022和栅导体层 1024之间还可以形成功函数调节层 （未示出）。
这里需要指出的是， 在图 18中， 将栅介质层 1026示出为空隙 1024底部的一薄层。 但是， 栅介质层 1026还可以形成在空隙 1024的侧壁上， 从而包围栅导体层 1028。
如图 18所示， 根据本公开实施例的半导体器件可以包括在衬底上形成的鰭。 在鰭 下方的衬底中可以形成穿通阻挡部 1038。 该鰭可以包括位于栅堆叠下方的第二半导体 层部分 1004以及与第二半导体层相邻的第三半导体层部分 1034或 1042。 该半导体器件 还包括： 形成于第三半导体层部分中的源 /漏区， 在半导体衬底上形成的隔离层， 以及 在隔离层上形成的横跨鰭的栅堆叠。 在第二半导体层部分 1004和衬底之间可以夹有隔 离岛 1032。
这里需要指出的是， 在本示例的互补性工艺情况下， 对 n型器件和 p型器件分别进 行处理， 从而在上述操作中以电介质层部分 1020-1遮蔽左侧的 p型器件区域， 而露出右 侧的 n型器件区域。 但是， 本公开不限于此。 例如， 在非互补工艺中， 可以不进行这 样的遮蔽。
另外， 在该示例中， 先遮蔽 p型器件区域， 对 n型器件区域进行处理。 但是， 本公 开不限于此。 对 n型器件区域和 p型器件区域进行处理的次序可以交换。
此外， 在以上示例中， 针对替代栅工艺进行了描述。 但是， 本公开不限于此。 例 如， 本公开同样适用于先栅工艺。
在以上的描述中， 对于各层的构图、 刻蚀等技术细节并没有做出详细的说明。 但 是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以上描述的方法并不完全 相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例 中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。 但是， 这些实施例仅仅是为了说明的目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价物限定。 不脱 离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这些替代和修改都应落 在本公开的范围之内。

Claims

权 利 要 求
1 . 一种制造半导体器件的方法， 包括：
在衬底上依次形成第一半导体层和第二半导体层；
对第二半导体层、 第一半导体层进行构图， 以形成鰭；
在衬底上形成隔离层， 所述隔离层露出所述第一半导体层的一部分；
向鰭下方的衬底进行离子注入， 以形成穿通阻挡部；
在隔离层上形成横跨鰭的栅堆叠；
以栅堆叠为掩模， 选择性刻蚀第二半导体层， 以露出第一半导体层；
选择性刻蚀第一半导体层， 以在第二半导体层下方形成空隙；
在衬底上形成第三半导体层， 用以形成源 /漏区。
2. 根据权利要求 1所述的方法， 其中， 在选择性刻蚀第一半导体层之后， 该 方法还包括：
在所述空隙中填充电介质材料。
3. 根据权利要求 1所述的方法， 其中， 形成隔离层包括：
在衬底上淀积电介质材料， 使得电介质材料实质上覆盖鰭， 其中位于鰭顶部的电 介质材料厚度充分小于位于衬底上的电介质材料厚度； 以及
对电介质材料进行回蚀。
4. 根据权利要求 3所述的方法， 其中， 位于鰭顶部的电介质材料厚度小于位 于衬底上的电介质材料厚度的三分之一。
5. 根据权利要求 3所述的方法， 其中， 通过高密度等离子体（HDP)淀积形 成电介质材料。
6. 根据权利要求 3所述的方法， 其中， 在衬底上形成多个鰭， 且位于每一鰭 顶部的电介质材料厚度小于与其相邻的鰭之间间距的二分之一。
7. 根据权利要求 1所述的方法， 在构图鰭之前， 该方法还包括： 在第二半导体层上形成保护层。
8. 根据权利要求 3所述的方法， 其中，
在构图鰭之前， 该方法还包括： 在第二半导体层上形成保护层，
其中， 所述隔离层和所述保护层包括相同的电介质材料。
9. 根据权利要求 1所述的方法， 其中， 形成穿通阻挡部包括： 对于 p型器件， 进行 n型注入； 而对于 n型器件， 进行 p型注入。
10. 根据权利要求 1所述的方法， 其中， 在形成第三半导体层时， 对第三半导 体层进行原位掺杂。
11. 根据权利要求 1所述的方法， 其中， 对于 p型器件， 第三半导体层带压应 力； 而对于 n型器件， 第三半导体层带拉应力。
12. 根据权利要求 11所述的方法，其中，衬底包括 Si，第一半导体层包括 SiGe， 第二半导体层包括 Si， 第三半导体层包括 SiGe或 Si:C。
13. 根据权利要求 1所述的方法， 其中， 所述栅堆叠是牺牲栅堆叠， 所述方法 还包括： 进行替代栅工艺， 去除牺牲栅堆叠， 形成栅堆叠。
14. 一种半导体器件， 包括：
在衬底上形成的鰭；
在鰭下方的衬底中形成的穿通阻挡部；
在衬底上形成的隔离层； 以及
在隔离层上形成的横跨鰭的栅堆叠，
其中， 所述鰭包括位于栅堆叠下方的第一半导体层部分以及与第一半导体层相邻 的第二半导体层部分，
该半导体器件还包括形成于第二半导体层部分中的源 /漏区。
15. 根据权利要求 14所述的半导体器件， 还包括： 在第一半导体层部分和衬 底之间形成的隔离岛。
16. 根据权利要求 14所述的半导体器件， 其中， 隔离层的顶面低于第一半导 体层部分的底面。
17. 根据权利要求 14所述的半导体器件， 其中， 衬底包括 Si， 第一半导体层 部分包括 Si， 第二半导体层部分包括 SiGe或 Si:C。
18. 根据权利要求 14所述的半导体器件， 其中， 第二半导体层部分通过隔离 层中的开口形成于衬底的表面上。
PCT/CN2012/085817 2012-11-09 2012-12-04 半导体器件及其制造方法 WO2014071665A1 (zh)

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