CN103779210A - FinFET鳍状结构的制造方法 - Google Patents
FinFET鳍状结构的制造方法 Download PDFInfo
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Abstract
本发明提供一种FinFET鳍状结构的制造方法,包括:提供衬底(200);形成第一介质层(210);形成第二介质层(220),所述第二介质层(220)与第一介质层相邻部分的材料与第一介质层(210)不同;形成贯穿所述第二介质层(220)和第一介质层(210)的开口(230),所述开口(230)部分暴露所述衬底;在所述开口(230)中填充半导体材料;去除第二介质层(220),形成鳍状结构(240)。本发明通过介质层的厚度来控制FinFET中鳍状结构的高度。利用不同材料之间的刻蚀选择性,可以很好的控制刻蚀停止,相比于时间控制可以更好的实现刻蚀均匀性。
Description
技术领域
本发明涉及半导体制造技术,尤其涉及一种FinFET鳍状结构的制造方法。
背景技术
随着半导体技术的发展,为了满足晶体管更快速的需求,需要较高的驱动电流。由于晶体管的驱动电流正比于晶体管的栅极宽度,为了提高驱动电流,需要较大的栅极宽度。然而,增加栅极宽度与半导体元件缩小化的需求互相冲突,于是发展出一种新型三维结构晶体管——鳍式场效应晶体管(FinFET)。在FinFET结构中,栅极形成在垂直衬底的鳍状结构上。通过栅极的控制,可以在鳍状结构两侧形成导电沟道。FinFET的优点包括抑制短沟道效应(SCE)、提高驱动电流以及降低泄漏电流。
目前FinFET在制造方面仍然存在许多问题。传统的工艺流程如图1(a)至图1(c)所示,包括:提供衬底;去除部分衬底形成鳍状结构;形成隔离鳍状结构的绝缘介质层。通常,形成隔离介质层的步骤包括:沉积绝缘介质层;进行化学机械抛光(CMP)停止在鳍状结构顶部;刻蚀部分绝缘介质层使鳍状结构暴露出一定高度。由于不存在刻蚀阻挡层,只能通过时间来控制刻蚀停止。硅片上不同位置的刻蚀速率存在一定差异,不同硅片的刻蚀速率也会存在一定差异,从而造成暴露出隔离介质层的鳍状结构的高度存在一定差异,这就直接影响了FinFET的栅极宽度,最终导致不同硅片上以及硅片上不同位置的器件性能存在一定差异,不利于器件的大规模集成和批量生产。
发明内容
本发明的目的是提供一种FinFET鳍状结构的制造方法,通过形成多层薄膜,并利用薄膜厚度来控制鳍状结构的高度,使暴露在绝缘层外部的鳍状结构的高度基本一致。
根据本发明的一个方面,提供一种FinFET鳍状结构的制造方法,该方法包括以下步骤:
a)提供衬底;
b)形成第一介质层;
c)形成第二介质层,所述第二介质层与第一介质层相邻部分的材料与第一介质层不同;
d)形成贯穿所述第二介质层和第一介质层的开口,所述开口部分暴露所述衬底;
e)在所述开口中填充半导体材料;
f)去除第二介质层,形成鳍状结构。
本发明通过形成第一介质层和第二介质层,并利用第二介质层的厚度来控制FinFET中鳍状结构的高度。由于形成薄膜的厚度比较均匀,并且厚度可以通过测量来控制。利用不同材料之间的刻蚀选择性,可以很好的控制刻蚀停止,相比于时间控制可以更好的实现刻蚀均匀性。采用上述方法形成的鳍状结构的高度基本一致,从而保证了不同硅片上以及硅片上不同位置的器件性能的一致性。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1(a)至图1(c)为现有技术的制造FinFET鳍状结构的各个阶段的剖面示意图;
图2为根据本发明的FinFET鳍状结构制造方法的流程图;
图3(a)至图3(d)为根据本发明的一个优选实施例按照图2所示流程制造FinFET鳍状结构的各个阶段的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了各种特定的工艺和材料的例子,但是本领域技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面,将结合图3(a)至图3(d)对图2中形成FinFET鳍状结构的方法进行具体地描述。
参考图2和图3(a),在步骤S101中,提供衬底200。
在本实施例中,衬底200包括硅衬底(例如硅晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底),衬底200可以包括各种掺杂配置。其他实施例中衬底200还可以包括其他基本半导体,例如锗。或者,衬底200可以包括化合物半导体(如Ⅲ-Ⅴ族材料),例如碳化硅、砷化镓、砷化铟。典型地,衬底200可以具有但不限于约几百微米的厚度,例如可以在400um-800um的厚度范围内。
参考图2和图3(a),在步骤S 102中,在衬底200上形成第一介质层210。所述第一介质层210可以通过化学气相沉淀(CVD)、等离子体增强CVD、高密度等离子体CVD、旋涂和/或其他合适的工艺等方法形成。所述第一介质层210的材料可以包括氧化硅、氮氧化硅及其组合,和/或其他合适的隔离材料。所述第一介质层210的厚度为最后形成的器件隔离介质层的厚度,其范围例如可以是100-500nm。
参考图2和图3(a),在步骤S 103中,在第一介质层210上形成第二介质层220,所述第二介质层220与第一介质层相邻部分的材料与第一介质层210不同。所述第二介质层220可以是单层或者多层结构。当第二介质层220为多层结构时,其最靠近第一介质层的子层的材料与下方的第一介质层的材料不同。所述第二介质层220的各层薄膜可以通过化学气相沉淀(CVD)、等离子体增强CVD、高密度等离子体CVD、旋涂和/或其他合适的工艺等方法形成。例如,如果第一介质层的材料是氧化硅,则所述第二介质层220可以包括三层薄膜,从下到上依次为氮化硅层、氧化硅层和氮化硅层。其中,所述氮化硅层的厚度可以为5-10nm,最上层氮化硅层可以作为之后填充半导体材料时进行化学机械抛光的阻挡层,最下层氮化硅层保证了刻蚀第二介质层时相对于下方的第一介质层的选择性。所述氧化硅层的厚度范围例如可以是100-500nm,用于控制要形成的鳍状结构的高度。或者,所述第二介质层220可以为单层氮化硅薄膜,既可以作为化学机械抛光的阻挡层,又可以保证刻蚀第二介质层时相对于下方的第一介质层的选择性。单层氮化硅薄膜厚度范围例如可以是100-500nm,用于控制要形成的鳍状结构的高度。
参考图2和图3(b),在步骤S 104中,形成贯穿所述第二介质层220和第一介质层210的开口230,所述开口230部分暴露所述衬底200。在本实施例中,先刻蚀第二介质层220,再刻蚀第一介质层210,直至暴露衬底200,形成开口230。刻蚀之前先在第二介质层220上覆盖一层光刻胶层(未示出),并曝光显影形成光刻胶图形,以光刻胶图形为掩膜采用等离子刻蚀等干法刻蚀,各向异性地刻蚀第二介质层220和第一介质层210。干法刻蚀工艺气体包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(HI)、氯、氩、氦、甲烷(及氯代甲烷)、乙炔、乙烯等碳的氢化物及其组合,和/或其他合适的材料。开口宽度为最后形成的鳍状结构的宽度,其范围例如可以是10-50nm。
参考图2和图3(c),在步骤S105中,在所述开口230中填充半导体材料。所述半导体材料可以为掺杂或非掺杂的单晶硅。在一个实施例中,填充所述开口230的方法可以为外延生长。可以在外延生长的同时进行原位掺杂,也可以在外延生长之后通过离子注入和退火的方式进行掺杂。对于NMOS,所述半导体材料可以为P型掺杂;对于PMOS,所述半导体材料可以为N型掺杂。在另一个实施例中,若衬底为单晶硅,可以在开口230中沉积非晶硅,然后通过退火工艺使非晶硅结晶从而形成单晶硅。退火可以采用包括快速退火、尖峰退火等其他合适的方法实施。填充所述半导体材料后,可以对所述半导体材料进行化学机械抛光(CMP),并停止在化学机械抛光阻挡层上,使所述半导体材料的上表面与第二介质层220的上表面齐平(本文件内,术语“齐平”意指两者之间的高度差在工艺误差允许的范围内)。
参考图2和图3(d),在步骤S106中,去除第二介质层220,形成鳍状结构240。可以使用湿法刻蚀和/或干法刻蚀的方式去除第二介质层220。湿法刻蚀工艺包括热磷酸(H3PO4)、稀释氢氟酸(DHF)或者其他合适刻蚀的溶液;干法刻蚀工艺包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(HI)、氯、氩、氦、甲烷(及氯代甲烷)、乙炔、乙烯等碳的氢化物及其组合,和/或其他合适的材料。由于第二介质层220与第一介质层相邻部分的材料与第一介质层210不同,因此可以选择具有高刻蚀选择性的刻蚀方法和/或刻蚀气体,使得刻蚀精确地停止在第一介质层的表面处。从而可以精确控制暴露出隔离介质层的鳍状结构的高度在整个晶圆表面的均匀性。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (12)
1.一种FinFET鳍状结构的制造方法,该方法包括以下步骤:
a)提供衬底(200);
b)形成第一介质层(210);
c)形成第二介质层(220),所述第二介质层(220)与第一介质层相邻部分的材料与第一介质层(210)不同;
d)形成贯穿所述第二介质层(220)和第一介质层(210)的开口(230),所述开口(230)部分暴露所述衬底;
e)在所述开口(230)中填充半导体材料;
f)去除第二介质层(220),形成鳍状结构(240)。
2.根据权利要求1所述的方法,其中,在所述步骤b)中,所述第一介质层(210)的材料包括氧化硅。
3.根据权利要求1或2所述的方法,其中,所述第一介质层(210)的厚度为最后形成的器件隔离介质层的厚度,其范围是100-500nm。
4.根据权利要求1所述的方法,其中,在所述步骤c)中,所述第二介质层(220)的顶部包括化学机械抛光阻挡层。
5.根据权利要求1或4所述的方法,其中,所述第二介质层(220)包括三层薄膜,从下到上依次为氮化硅层、氧化硅层和氮化硅层。
6.根据权利要求5所述的方法,其中,所述氮化硅层的厚度为5-10nm。
7.根据权利要求5所述的方法,其中,所述氧化硅层的厚度为暴露出的鳍状结构的高度,其范围是100-500nm。
8.根据权利要求1所述的方法,其中,在所述步骤d)中,所述开口(230)的宽度为最后形成的鳍状结构的宽度,其范围是10-50nm。
9.根据权利要求1所述的方法,其中,在所述步骤e)中,所述半导体材料为掺杂或非掺杂的单晶硅。
10.根据权利要求1所述的方法,其中,在所述步骤e)中,填充半导体材料的方法为外延生长。
11.根据权利要求1所述的方法,其中,在所述步骤e)中,填充半导体材料的方法包括沉积非晶硅并退火形成单晶硅。
12.根据权利要求1、10或11所述的方法,其中,在所述步骤e)中,填充半导体材料之后还包括进行化学机械抛光。
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