CN103531474B - 半导体器件制造方法 - Google Patents
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Abstract
一种FinFET半导体器件制造方法,鳍状半导体柱被形成为多条平行排列,多条平行排列的栅极与之相交。全面性地沉积多晶硅层,并将其转变成单晶硅层,使该单晶硅层与鳍状半导体柱本质上成为一体,这相当于抬升了鳍状半导体柱中的源漏区域,并且扩展了鳍状半导体柱的顶部面积;之后,使位于鳍状半导体柱顶面以上的单晶硅层转化而形成金属硅化物,从而形成源漏区域接触。本发明的源漏区域接触较常规FinFET中的源漏区域接触的面积更大,使得接触电阻减小,并且有利于后续工艺中的自对准金属插塞的形成。
Description
技术领域
本发明涉及半导体器件制造方法领域,特别地,涉及一种FinFET(鳍状场效应晶体管)的制造方法。
背景技术
近30年来,半导体器件一直按照摩尔定律等比例缩小,半导体集成电路的特征尺寸不断缩小,集成度不断提高。随着技术节点进入深亚微米领域,例如100nm以内,甚至45nm以内,传统场效应晶体管(FET),也即平面FET,开始遭遇各种基本物理定律的限制,使其等比例缩小的前景受到挑战。众多新型结构的FET被开发出来,以应对现实的需求,其中,FinFET就是一种很具等比例缩小潜力的新结构器件。
FinFET,鳍状场效应晶体管,是一种多栅半导体器件。由于结构上的独有特点,FinFET成为22nm技术节点以后很具发展前景的器件。参见附图1,FinFET包括一个垂直于衬底1的Fin2,Fin被称为鳍状半导体柱,不同于常规的平面FET,FinFET的沟道区位于Fin内。栅极绝缘层3和栅极4在侧面和顶面包围Fin,形成至少两面的栅极,即位于Fin的两个侧面以及顶面的栅极,从而获得了对沟道区更好的控制,能够提供“全耗尽”型的操作;Fin2未被栅极4包围的两端为源漏区域5。通过控制Fin2的厚度,使得FinFET具有极佳的特性:更好的短沟道效应抑制能力,更好的亚阈值斜率,较低的关态电流,消除了浮体效应,更低的工作电压,更有利于按比例缩小。而为了获得更大的驱动力,多个并列的鳍状半导体柱可以通过一个栅极控制。参见附图2,多个并列的Fin2由同一个栅极4进行控制,获得的FinFET具有更大驱动能力以使电路具有更佳性能。图3为多个并列鳍状半导体柱的FinFET的显微照片。
由于鳍状半导体柱的形状,Fin的顶部表面积非常小,这样一来,FinFET源漏区域用于形成接触插塞的接触面积非常小。同时,由于接触面积小,使得对通过自对准工艺而形成源漏区域接触的难度也增加了。由于接触面积较小以及工艺偏差,自对准金属材料形成的FinFET源漏区域接触插塞具有较大的接触电阻,并会导致较大的寄生电容,这会显著降低整个电路的速度。因此,需要提供一种FinFET的制造方法,在保证FinFET本身所具有的优点的前提下,解决上述问题。
发明内容
本发明针对FinFET器件源漏区域接触情况不良的问题,提出了抬升源漏区域以便于形成接触的工艺方案。本发明提供一种FinFET制造方法,用于制造FinFET器件,其中,包括如下步骤:
提供半导体衬底,在该半导体衬底上形成多条平行排列的鳍状半导体柱;
沉积栅极绝缘层和栅极材料,定义栅极图形,形成多条平行排列的栅极,所述栅极与所述鳍状半导体柱相交,定义FinFET的沟道区域;
形成间隙壁,其位于所述栅极和所述鳍状半导体柱的侧面上;
全面性沉积多晶硅层,然后对该多晶硅层进行平坦化处理,暴露出所述栅极的顶面;
将所述多晶硅层单晶化,形成单晶硅层;
形成隔离结构,其切断所述鳍状半导体柱;
使位于所述鳍状半导体柱顶面以上的所述单晶硅层与金属反应形成金属硅化物,所形成的金属硅化物为源漏区域接触;
多条平行排列的所述栅极被按照预定区域进行切割,形成栅极隔离沟槽,从而获得所需要的FinFET。
在本发明的方法中,所述半导体衬底为SOI衬底,或者所述半导体衬底为单晶的Si、SiGe、SiC、InAs、GaN、AlGaN、InP或它们的组合的衬底,所述鳍状半导体柱为单晶的Si、SiGe、SiC、InAs、GaN、AlGaN、InP材料。在所述半导体衬底上形成多条平行排列的鳍状半导体柱具体包括:光刻出所述鳍状半导体柱的图形,对所述半导体衬底进行各向异性刻蚀,从而形成所述鳍状半导体柱。
在本发明的方法中,采用先栅工艺,所述栅极为非牺牲性的,其材料为金属或金属硅化物。
在本发明的方法中,采用后栅工艺,所述栅极为牺牲性的,其材料为多晶硅;其中,在形成所述源漏区域接触之后,进行后栅工艺,包括:
移除所述栅极和所述栅极绝缘层;
接着,形成后栅工艺中的栅极绝缘层和栅极。
在本发明的方法中,所述后栅工艺中的栅极绝缘层为高K栅极绝缘材料,所述后栅工艺中的栅极为金属或金属硅化物;所述后栅工艺中的栅极绝缘层的材料选自HfO2、ZrO2、LaAlO3,所述后栅工艺中的栅极的材料选自Al、W、Ti、Ta或它们的硅化物。
在本发明的方法中,将所述多晶硅层单晶化的步骤具体为:采用激光退火工艺,使所述多晶硅层转变为所述单晶硅层;所述激光退火工艺为高温激光退火工艺,退火温度为1000℃,时间为1秒。
在本发明的方法中,形成所述间隙壁的步骤具体包括:在所述半导体衬底上沉积间隙壁材料层,接着采用各向异性的刻蚀工艺,去除所述栅极顶部以及所述鳍状半导体柱顶部的间隙壁材料层,使间隙壁材料层仅留存在所述栅极和所述鳍状半导体柱的侧面上,从而形成所述间隙壁;所述间隙壁的材料为SiO2、Si3N4。
在本发明的方法中,形成栅极隔离沟槽的步骤具体包括:采用刻蚀工艺,在所述栅极中的预定区域进行刻蚀,使得多条所述栅极被切割,从而形成所述栅极隔离沟槽;另外,在形成所述栅极隔离沟槽时,所述间隙壁被部分或全部刻蚀;另外,在形成所述栅极隔离沟槽后,在所述栅极隔离结构中填充隔离介质。
本发明提供了一种FinFET器件的制造方法。本发明中,鳍状半导体柱被形成为多条平行排列,多条平行排列的栅极与之相交,这有利于在随后的工艺中根据需求进行分割而获得所需要FinFET。通过采用全面性地沉积多晶硅层,并将其通过激光退火转变成单晶硅层,使单晶硅层与鳍状半导体柱本质上成为一体,由于鳍状半导体柱的顶部之上形成了与其相同的单晶硅层,这相当于抬升了鳍状半导体柱中的源漏区域,并且扩展了鳍状半导体柱的顶部面积,有利于随后源漏区域接触的形成。之后,使位于鳍状半导体柱顶面以上的单晶硅层转化而形成金属硅化物,从而形成源漏区域接触。由于源漏区域接触较常规FinFET中的源漏区域接触的面积更大,使得接触电阻减小,并且有利于后续工艺中的自对准金属插塞的形成。
附图说明
图1常规FinFET器件结构;
图2常规具有多个并列鳍状半导体柱的FinFET器件结构;
图3常规具有多个并列鳍状半导体柱的FinFET器件显微照片;
图4A-12B本发明制造方法的工艺过程。
具体实施方式
以下,通过附图中示出的具体实施例来描述本发明。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
本发明提供一种FinFET制造方法,其制造流程参见附图1-9。
首先,参见图4A和4B,在半导体衬底10上形成Fin(鳍状半导体柱)12,其中图4A为平面图,图4B为图4A中沿AA’线的横截面图。提供半导体衬底10,本实施例中采用了SOI(绝缘体上硅)衬底,另外,衬底材料也可以采用单晶的Si、SiGe、SiC、InAs、GaN、AlGaN、InP或它们的组合。半导体衬底10具有绝缘层11,绝缘层11之上具有顶层半导体层(未示出,即用来形成Fin的层),绝缘层11通常为SiO2。在半导体衬底10上形成多个并列平行的Fin12,Fin12具有侧面和顶面。本实施例中,Fin12的形成方法具体包括,首先在SOI衬底的顶层半导体层上形成硬掩膜13,硬掩膜13的材料为Si3N4,并涂布光刻胶,光刻出Fin12图形,以图案化的硬掩膜13为掩模,对顶层半导体层进行各向异性的刻蚀,从而获得Fin12。Fin12(也即顶层半导体层)为单晶Si,可选地,也可以是单晶的SiGe、SiC、InAs、GaN、AlGaN、InP或它们的组合。在另外的实施例中,Fin12也可以通过外延工艺在体硅衬底上直接形成。在形成Fin12之后,去除图案化硬掩膜13。
接着,形成栅极绝缘层14和栅极15,参见图5A和5B,其中图5A为平面图,图5B为图5A中沿AA’线的横截面图。先在沉积一层栅极绝缘材料薄膜,例如是SiO2薄膜,更加优选地采用高K栅极绝缘材料,高K栅极绝缘材料具有比SiO2更大的介电常数,对晶体管器件性能更为有利。高K栅极绝缘材料包括一些金属氧化物、金属铝酸盐等,例如HfO2、ZrO2、LaAlO3等。栅极绝缘层14既要实现其栅绝缘特性,又要具有尽可能薄的厚度,其厚度优选为0.5-10nm,沉积工艺例如为热氧化或者CVD。在形成栅极绝缘层14之后,沉积栅极15的材料。本实施例中采用后栅工艺,栅极和栅极绝缘层均为牺牲层,其会在后续步骤中移除,因此在这里栅极15为多晶硅材料。在沉积栅极材料后,进行光刻胶涂布,光刻,定义出栅极图形,对栅极15以及栅极绝缘层14顺序刻蚀,从而形成栅极图形。本发明中,多条平行排列的栅极图形与多个并列平行的Fin12相交,定义出FinFET的沟道区域。在另外的实施例中,可以采用先栅工艺,直接形成非牺牲性的栅极15,可选地,采用金属硅化物、金属等作为栅极材料,例如Al、W、Ti、Ta或它们的硅化物。
接着,形成间隙壁16,参见6A-6C,其中,图6A为平面图,图6B为图6A中沿AA’线的横截面图,图6C为图6A中沿BB’线的横截面图。间隙壁16形成于栅极15和Fin12的侧面上。首先,在衬底上沉积间隙壁材料层,例如SiO2、Si3N4等等,采用保形性良好的沉积工艺,使其以期望的厚度覆盖整个衬底;接着采用各向异性的刻蚀工艺,去除栅极15顶部以及Fin12顶部的间隙壁材料层,使间隙壁材料层仅留存在栅极15和Fin12的侧面上,从而形成间隙壁16。
接着,形成多晶硅层17,参见图7A-7C,其中,图7A为平面图,图7B为图7A中沿AA’线的横截面图,图7C为图7A中沿BB’线的横截面图。全面性地沉积多晶硅层17于衬底之上,覆盖Fin12和栅极15,然后进行平坦化处理,例如CMP工艺,减薄多晶硅层,暴露出栅极15顶面。
接着,将晶硅层17单晶化,形成单晶硅层18,参见图8A-8C,其中,图8A为平面图,图8B为图8A中沿AA’线的横截面图,图8C为图8A中沿BB’线的横截面图。将晶硅层17单晶化的方法具体为,采用高温激光退火工艺,以单晶Si的Fin12为种子层,将多晶硅层17完全转变为单晶硅层18。高温激光退火温度为1000℃,时间为1秒。图8B和图8C中虚线分开了Fin12和单晶硅层18,表示它们材料以及晶体特征相同,本质上成为一体,但却在不同步骤中形成。由此,参见图8B,Fin12的顶部之上形成了与其相同的单晶硅层18,这相当于抬升了Fin12中的源漏区域,并且扩展了Fin12的顶部面积,这有利于随后源漏区域接触的形成。
接着,形成隔离结构19,参见图9A-9C,其中,图9A为平面图,图9B为图9A中沿AA’线的横截面图,图9C为图9A中沿BB’线的横截面图。隔离结构19用于使不同FinFET相互绝缘隔离。在形成隔离结构19的预定区域,进行刻蚀工艺,去除其中的单晶硅层18以及Fin12,也即切断Fin12,直至暴露出衬底的绝缘层11,形成隔离沟槽;接着,在隔离沟槽中填充绝缘材料,例如SiO2等,并进行平坦化,如采用CMP工艺,暴露出单晶硅层18和栅极15的顶面,从而获得隔离结构19。本发明中,隔离结构19位于相邻的两条栅极15之间,并与栅极15平行布置。图9B和图9C中虚线分开了绝缘层11和隔离结构19,表示它们材料可以是相同,如均为SiO2,本质上成为一体,但却在不同步骤中形成。在另外的实施例中,绝缘层11和隔离结构19的材料可以不同。
接着,形成源漏区域接触20,参见图10A-10C,其中,图10A为平面图,图10B为图10A中沿AA’线的横截面图,图10C为图10A中沿BB’线的横截面图。在该步骤中,通过沉积金属并与单晶硅层18进行反应,使位于Fin12顶面以上的单晶硅层18转化而形成金属硅化物,参见图10B和图10C。所采用的金属可以是Ni或NiPt,形成的金属硅化物为Ni硅化物或NiPt硅化物,所形成的金属硅化物用作源漏区域接触20。由于在图8A-8C的步骤中,FinFET的源漏区域已经被抬升,Fin12的顶部面积也已被扩展,该步骤中形成的源漏区域接触20与源漏区域的接触面积较常规FinFET更大,因而能够减小接触电阻,从获得更好的接触效果,并且,由于接触面积增大以及源漏区域接触20面积的扩大,使得后续工艺中的自对准金属插塞的形成更为便利。
接着,进行后栅工艺,参见图11A-11C,其中,图11A为平面图,图11B为图11A中沿AA’线的横截面图,图11C为图11A中沿BB’线的横截面图。本实施例中采用了后栅工艺,因此,在形成源漏区域接触20之后,移除先前形成的多晶硅栅极15和栅极绝缘层14,接着,形成后栅工艺中的栅极绝缘层21和栅极22。如前所述,后栅工艺中的栅极绝缘层21例如是SiO2薄膜,更加优选地采用高K栅极绝缘材料,高K栅极绝缘材料具有比SiO2更大的介电常数,包括一些金属氧化物、金属铝酸盐等,例如HfO2、ZrO2、LaAlO3等;栅极22采用金属硅化物、金属等,例如Al、W、Ti、Ta或它们的硅化物。
接着,形成器件隔离,以获得所需要的FinFET,参见图12A、12B,其中,图12A为平面图,图12B为图12A中沿AA’线的横截面图,图12A中沿BB’线的横截面图与图11C相同,此处不再重复。在此步骤中,多条连续的平行栅极被按照预定区域进行切割,从而获得所需要的FinFET。通过刻蚀工艺,在栅极线条中形成栅极隔离沟槽23,可选地,形成栅极隔离沟槽时,间隙壁16也被部分或全部刻蚀,如图12A中栅极隔离沟槽23′所示。栅极隔离沟槽23(以及23′)中可以填充隔离介质,例如SiO2等。
接着,可以进行FinFET以及集成电路的其他工序,例如介质层的形成,金属插塞的形成,等等。
这样,本发明提供了一种FinFET器件的制造方法。本发明中,鳍状半导体柱Fin12被形成为多条平行排列,多条平行排列的栅极与Fin12相交,这有利于在随后的工艺中根据需求进行分割而获得所需要FinFET。间隙壁16形成在多条Fin12和栅极15的侧面上,一方面保护了Fin12和栅极15的侧壁,另一方面提供了绝缘隔离。通过采用全面性地沉积多晶硅层,并将其通过激光退火转变成单晶硅层,使单晶硅层与Fin12本质上成为一体,由于Fin12的顶部之上形成了与其相同的单晶硅层18,这相当于抬升了Fin12中的源漏区域,并且扩展了Fin12的顶部面积,有利于随后源漏区域接触的形成。之后,使位于Fin12顶面以上的单晶硅层18转化而形成金属硅化物,从而形成源漏区域接触20。由于源漏区域接触20较常规FinFET中的源漏区域接触的面积更大,使得接触电阻减小,并且有利于后续工艺中的自对准金属插塞的形成。
以上参照本发明的实施例对本发明予以了说明。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围,本领域技术人员可以做出多种替换和修改,这些替换和修改都应落在本发明的范围之内。
Claims (15)
1.一种半导体器件制造方法,用于制造FinFET器件,其特征在于包括如下步骤:
提供半导体衬底,在该半导体衬底上形成多条平行排列的鳍状半导体柱;
沉积栅极绝缘层和栅极材料,定义栅极图形,形成多条平行排列的栅极,所述栅极与所述鳍状半导体柱相交,定义FinFET的沟道区域;
形成间隙壁,其位于所述栅极和所述鳍状半导体柱的侧面上;
全面性沉积多晶硅层,然后对该多晶硅层进行平坦化处理,暴露出所述栅极的顶面;
将所述多晶硅层单晶化,形成单晶硅层;
形成隔离结构,其切断所述鳍状半导体柱;
使位于所述鳍状半导体柱顶面以上的所述单晶硅层与金属反应形成金属硅化物,所形成的金属硅化物为源漏区域接触;
多条平行排列的所述栅极被按照预定区域进行切割,形成栅极隔离沟槽,从而获得所需要的FinFET。
2.根据权利要求1所述的方法,其特征在于,所述半导体衬底为SOI衬底,或者所述半导体衬底为单晶的Si、SiGe、SiC、InAs、GaN、AlGaN、InP或它们的组合的衬底,所述鳍状半导体柱为单晶的Si、SiGe、SiC、InAs、GaN、AlGaN、InP材料或它们的组合。
3.根据权利要求2所述的方法,其特征在于,在所述半导体衬底上形成多条平行排列的鳍状半导体柱具体包括:光刻出所述鳍状半导体柱的图形,对所述半导体衬底进行各向异性刻蚀,从而形成所述鳍状半导体柱。
4.根据权利要求1所述的方法,其特征在于,采用先栅工艺,所述栅极为非牺牲性的,其材料为金属或金属硅化物。
5.根据权利要求1所述的方法,其特征在于,采用后栅工艺,所述栅极为牺牲性的,其材料为多晶硅。
6.根据权利要求5所述的方法,其特征在于,在形成所述源漏区域接触之后,进行后栅工艺,包括:
移除所述栅极和所述栅极绝缘层;
接着,形成后栅工艺中的栅极绝缘层和栅极。
7.根据权利要求6所述的方法,其特征在于,所述后栅工艺中的栅极绝缘层为高K栅极绝缘材料,所述后栅工艺中的栅极为金属或金属硅化物。
8.根据权利要求6或7所述的方法,其特征在于,所述后栅工艺中的栅极绝缘层的材料选自HfO2、ZrO2、LaAlO3,所述后栅工艺中的栅极的材料选自Al、W、Ti、Ta或它们的硅化物。
9.根据权利要求1所述的方法,其特征在于,将所述多晶硅层单晶化的步骤具体为:采用激光退火工艺,使所述多晶硅层转变为所述单晶硅层。
10.根据权利要求9所述的方法,其特征在于,所述激光退火工艺为高温激光退火工艺,退火温度为1000℃,时间为1秒。
11.根据权利要求1所述的方法,其特征在于,形成所述间隙壁的步骤具体包括:在所述半导体衬底上沉积间隙壁材料层,接着采用各向异性的刻蚀工艺,去除所述栅极顶部以及所述鳍状半导体柱顶部的间隙壁材料层,使间隙壁材料层仅留存在所述栅极和所述鳍状半导体柱的侧面上,从而形成所述间隙壁。
12.根据权利要求11所述的方法,其特征在于,所述间隙壁的材料为SiO2或Si3N4。
13.根据权利要求1所述的方法,其特征在于,形成栅极隔离沟槽的步骤具体包括:采用刻蚀工艺,在所述栅极中的预定区域进行刻蚀,使得多条所述栅极被切割,从而形成所述栅极隔离沟槽。
14.根据权利要求13所述的方法,其特征在于,在形成所述栅极隔离沟槽时,所述间隙壁被部分或全部刻蚀。
15.根据权利要求13所述的方法,其特征在于,在形成所述栅极隔离沟槽后,在所述栅极隔离沟槽中填充隔离介质。
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Publication number | Priority date | Publication date | Assignee | Title |
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CN103779210A (zh) * | 2012-10-18 | 2014-05-07 | 中国科学院微电子研究所 | FinFET鳍状结构的制造方法 |
US10468406B2 (en) * | 2014-10-08 | 2019-11-05 | Northrop Grumman Systems Corporation | Integrated enhancement mode and depletion mode device structure and method of making the same |
CN105633157B (zh) * | 2015-03-31 | 2019-07-30 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US9773731B2 (en) * | 2016-01-28 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
CN107706113B (zh) * | 2016-08-09 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET器件及制备方法、电子装置 |
WO2018063365A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Dual fin endcap for self-aligned gate edge (sage) architectures |
US10396208B2 (en) | 2017-01-13 | 2019-08-27 | International Business Machines Corporation | Vertical transistors with improved top source/drain junctions |
US10936756B2 (en) | 2017-01-20 | 2021-03-02 | Northrop Grumman Systems Corporation | Methodology for forming a resistive element in a superconducting structure |
US9934977B1 (en) | 2017-01-27 | 2018-04-03 | International Business Machines Corporation | Salicide bottom contacts |
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US9911736B1 (en) | 2017-06-14 | 2018-03-06 | Globalfoundries Inc. | Method of forming field effect transistors with replacement metal gates and contacts and resulting structure |
US11411095B2 (en) * | 2017-11-30 | 2022-08-09 | Intel Corporation | Epitaxial source or drain structures for advanced integrated circuit structure fabrication |
US10741401B1 (en) | 2019-02-09 | 2020-08-11 | International Business Machines Corporation | Self-aligned semiconductor gate cut |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6346438B1 (en) * | 1997-06-30 | 2002-02-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
CN1525530A (zh) * | 2003-02-27 | 2004-09-01 | ̨������·����ɷ�����˾ | 半导体鳍式元件的接触窗及其制造方法 |
CN102157555A (zh) * | 2010-02-11 | 2011-08-17 | 台湾积体电路制造股份有限公司 | 鳍式场效晶体管 |
CN102299092A (zh) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | 一种半导体器件及其形成方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8026553B2 (en) * | 2007-05-10 | 2011-09-27 | Kabushiki Kaisha Toshiba | Semiconductor memory device and manufacturing method thereof |
US8492839B2 (en) * | 2010-08-24 | 2013-07-23 | International Business Machines Corporation | Same-chip multicharacteristic semiconductor structures |
CN102956457B (zh) * | 2011-08-22 | 2015-08-12 | 中国科学院微电子研究所 | 半导体器件结构及其制作方法、及半导体鳍制作方法 |
US8652932B2 (en) * | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US8816436B2 (en) * | 2012-05-16 | 2014-08-26 | International Business Machines Corporation | Method and structure for forming fin resistors |
-
2012
- 2012-07-02 CN CN201210229040.4A patent/CN103531474B/zh active Active
- 2012-07-18 WO PCT/CN2012/078837 patent/WO2014005360A1/zh active Application Filing
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6346438B1 (en) * | 1997-06-30 | 2002-02-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
CN1525530A (zh) * | 2003-02-27 | 2004-09-01 | ̨������·����ɷ�����˾ | 半导体鳍式元件的接触窗及其制造方法 |
CN102157555A (zh) * | 2010-02-11 | 2011-08-17 | 台湾积体电路制造股份有限公司 | 鳍式场效晶体管 |
CN102299092A (zh) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | 一种半导体器件及其形成方法 |
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US9425288B2 (en) | 2016-08-23 |
WO2014005360A1 (zh) | 2014-01-09 |
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