CN103811342B - 鳍结构及其制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 230000008021 deposition Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910003217 Ni3Si Inorganic materials 0.000 description 1
- 241000849798 Nita Species 0.000 description 1
- 229910019897 RuOx Inorganic materials 0.000 description 1
- 235000003976 Ruta Nutrition 0.000 description 1
- 240000005746 Ruta graveolens Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000005806 ruta Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
本申请公开了一种鳍结构及其制造方法。一示例方法可以包括:对衬底进行构图,以在衬底的选定区域上形成初始鳍;在衬底上形成电介质层,使得电介质层实质上覆盖初始鳍,其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度;以及对电介质层进行回蚀,以露出初始鳍的一部分,其中,初始鳍的露出的所述部分用作鳍。
Description
技术领域
本公开涉及半导体领域,更具体地,涉及一种鳍结构及其制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小,短沟道效应愈加明显。为此,提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言,FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅极。因此,沟道区形成于鳍中,且其宽度主要由鳍的高度决定。然而,在集成电路制造工艺中,难以控制晶片上形成的鳍的高度相同,从而导致晶片上器件性能的不一致性。
发明内容
本公开的目的至少部分地在于提供一种鳍结构及其制造方法。
根据本公开的一个方面,提供了一种制造鳍结构的方法。根据一示例,该方法可以包括:对衬底进行构图,以在衬底的选定区域上形成初始鳍;在衬底上形成电介质层,使得电介质层实质上覆盖初始鳍,其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度;以及对电介质层进行回蚀,以露出初始鳍的一部分,其中,初始鳍的露出的所述部分用作鳍。
根据本公开的另一方面,提供了一种鳍结构。根据一示例,该鳍结构可以包括:衬底;在衬底上由衬底构图而形成的多个鳍;以及在衬底上形成的、部分地填充相邻鳍之间的间隙的电介质层,其中,每一鳍的顶面大致持平,电介质层的顶面大致持平。
附图说明
通过以下参照附图对本公开实施例的描述,本公开的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1-6是示出了根据本公开实施例的制造鳍结构流程的示意图;
图7和8示出了在根据本公开实施例的鳍结构上进一步形成的半导体器件的示意图;
图9-13是示出了根据本公开另一实施例的制造鳍结构流程的示意图;以及
图14示出了在根据本公开另一实施例的鳍结构上进一步形成的半导体器件的示意图。
具体实施方式
以下,将参照附图来描述本公开的实施例。但是应该理解,这些描述只是示例性的,而并非要限制本公开的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中,当将一层/元件称作位于另一层/元件“上”时,该层/元件可以直接位于该另一层/元件上,或者它们之间可以存在居中层/元件。另外,如果在一种朝向中一层/元件位于另一层/元件“上”,那么当调转朝向时,该层/元件可以位于该另一层/元件“下”。
为控制鳍的高度,常规的思想是控制鳍构图工艺中的参数。例如,在通过刻蚀衬底形成鳍的情况下,可以通过刻蚀参数来控制刻蚀深度,并因此控制所形成的鳍的高度。与此不同,根据本公开的一些实施例,并不刻意去精确控制鳍构图工艺,而是在通过构图在衬底上形成初始鳍之后,再在衬底上形成电介质层以基本上覆盖初始鳍。然后,可以对电介质层进行回蚀,以露出初始鳍的一部分。这样,以初始鳍的露出部分作为最终器件的鳍,其高度基本上由其顶面到电介质层的顶面的距离决定。
根据本公开的一个实施例,可以如此形成电介质层,使得电介质层基本上覆盖初始鳍时(即,在多个初始鳍的情况下基本上填充初始鳍之间的间隙时),位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度,例如初始鳍顶部的电介质层厚度可以小于位于衬底上的电介质层厚度的三分之一,优选为四分之一。例如,这可以通过高密度等离子体(HDP)淀积来实现。另外,在形成多个初始鳍的情况下,位于每一初始鳍的顶面之上的电介质材料的厚度可以小于与其相邻的初始鳍之间间距的二分之一。这样,在随后的回蚀中,可以减少刻蚀深度,从而能够增加刻蚀控制精度。
本公开可以各种形式呈现,以下将描述其中一些示例。
首先,参照图1-6,描述根据本公开一实施例的制造鳍结构的流程。
如图1所示,提供衬底1000。该衬底1000可以是各种形式的衬底,例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中,为方便说明,以体Si衬底为例进行描述。
可以通过对衬底1000进行构图来形成初始鳍。本领域技术人员知道众多手段来形成初始鳍。例如,可以在衬底1000上形成光致抗蚀剂1002,按照所需形成的鳍的位置来对光致抗蚀剂1002进行构图。然后,可以如图2所示,利用构图的光致抗蚀剂1002为掩模,例如通过反应离子刻蚀(RIE)来对衬底1000进行构图,以形成初始鳍1004。之后,可以去除光致抗蚀剂1002。由于刻蚀深度D相对较大,刻蚀深度在衬底上事实上有较大变化。在图2中示出了这样的变化。
这里需要指出的是,尽管在图2中示出了形成5个初始鳍的示例,但是本公开不限于此。可以形成更多或者更少(乃至单个)初始鳍。
然后,如图3所示,可以在形成有初始鳍的衬底1000上例如通过淀积来形成电介质层1006。根据本公开的实施例,可以如此淀积,使得初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度,并且一般来说初始鳍顶部的电介质层厚度都小于位于衬底上的电介质层厚度的三分之一,优选为四分之一。例如,每一初始鳍顶部的电介质层厚度一般不大于20nm,而位于衬底上的电介质层厚度可达100nm左右。
根据本公开的一示例,电介质层1006可以包括通过高密度等离子体(HDP)淀积形成的氧化物(例如,氧化硅)。由于HDP的特性,在淀积过程中可以使得初始鳍顶部的电介质层(沿垂直于衬底方向的)厚度和初始鳍侧面的电介质层(沿平行于衬底的方向,即横向的)厚度要小于初始鳍之间衬底上的电介质层(沿垂直于衬底方向的)厚度。因为HDP的这种特性,在常规技术中通常并不采用HDP淀积来制作氧化隔离。
在此,例如可以通过控制淀积条件,使得电介质层1006在基本上覆盖初始鳍1004时(即,基本上填充初始鳍1004之间的空隙时),位于每一初始鳍1004顶部上的厚度可以小于与其相邻的初始鳍之间间距的二分之一。如果初始鳍1004之间的间距并不相同,则可以使电介质层1006位于每一初始鳍1004顶部的厚度小于与其相邻的初始鳍之间间距中较小间距的二分之一。
随后,可以对电介质层1006进行回蚀。根据本公开的示例,回蚀可以如下进行。例如,如图4所示,可以对电介质层1006进行平坦化处理,例如化学机械抛光(CMP),直至露出初始鳍1004的顶面。优选地,在露出初始鳍1004的顶面之后,还可以进一步进行平坦化处理(“过平坦化处理”),从而也去除了初始鳍1004顶端的一部分。然后,可以相对于衬底1000和初始鳍1004(例如,硅),对电介质层1006(例如,氧化硅)进行选择性刻蚀。优选地,在选择性刻蚀电介质层1006之前,还可以如图5所示,进行热氧化处理,在初始鳍1004的端部形成氧化物1008,以去除初始鳍1004顶端处的缺陷。通过选择性刻蚀,如图6所示,电介质层1006相对于初始鳍1004的顶面凹入,从而露出初始鳍1004的一部分。初始鳍1004的露出部分随后充当最终器件的鳍。
在电介质层1006为氧化物的情况下,对电介质层1006的选择性刻蚀也会去除初始鳍1004端部形成的氧化物1008。这里需要指出的是,即便氧化物1008没有被去除,也不会影响鳍在最终器件中起作用。
尽管如上所述,初始鳍1004的顶面到其底面的距离D′(由于平坦化处理等操作,D′<D)在衬底上存在较大变化,但是由于电介质层1006的刻蚀深度相对较小,从而对该刻蚀的控制相对容易,并因此可以更加精确地控制从鳍1004的顶面到电介质层1006的顶面的距离(h,至少部分地决定最终器件的鳍高度并因此决定最终器件的沟道宽度),使得h在衬底上基本保持一致。
这样,就得到了根据本公开的鳍结构示例。如图6所示,该鳍结构包括在衬底1000上形成的初始鳍1004。另外,衬底上形成有电介质层1006。电介质层1006的顶面低于初始鳍1004的顶面,从而露出初始鳍1004的一部分。初始鳍1004的露出部分用作最终器件的鳍。在这种鳍结构中,每一鳍1004的顶面大致持平,而鳍之间的间隙中填充的电介质层的顶面也大致持平,从而使得每一鳍的高度(即,h)大致相同。鳍1004例如可以具有约5-30nm的宽度。
在得到这种鳍结构之后,还可以在该鳍结构上来形成半导体器件。本领域技术人员知道多种方式来在鳍结构上形成半导体器件。以下,将参考图7和8描述一示例。
如图7和8所示(图7为沿图8中AA′线的截面图),可以在鳍结构上例如通过淀积形成高K栅介质层1010。高K栅介质层1010例如包括HfO2,厚度为约2-5nm。优选地,在形成高K栅介质层1010之前,还可以淀积一薄界面层(未示出)。界面层例如包括氧化物(例如,氧化硅),厚度为约0.3-0.7nm。在高K栅介质层1010之上,可以形成栅导体层1014。栅导体层1014例如包括多晶硅。优选地,在高K栅介质层1010和栅导体层1014可以形成功函数调节层1012。功函数调节层1012例如可以包括TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTa、NiTa、MoN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSi、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx及其组合,厚度可以约为2-10nm。
如图8所示,可以对栅导体层1014以及可选的功函数调节层1012进行构图(图8的示例中构图为条形),以形成最终的栅堆叠。在图8的示例中,还对高K栅介质层1010进行了同样的构图,从而露出了鳍1014的一部分。这里需要指出的是,高K栅介质层1010的构图并不是必须的。在栅堆叠两侧,还可以形成栅侧墙1016。栅侧墙1016例如包括氮化物(例如,氮化硅)。在如上所述形成栅堆叠之后,可以进行源漏注入,以形成源/漏区。
这里需要指出的是,在图8所示的示例中,栅堆叠形成为一连续的条形。但是本公开不限于此。例如,可以根据设计布局,使不同器件的栅堆叠彼此隔离。
以下,参照图9-13,描述根据本公开一实施例的制造鳍结构的流程。
如图9所示,提供衬底2000。该衬底2000可以是各种形式的衬底,例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中,为方便说明,以体Si衬底为例进行描述。在衬底2000上,例如通过淀积形成停止层2001。停止层2001例如可以包括氮化物(例如,氮化硅),厚度约为10-20nm。
随后,可以通过对衬底2000进行构图来形成初始鳍。例如,可以在停止层2001上形成光致抗蚀剂2002,按照所需形成的鳍的位置来对光致抗蚀剂2002进行构图。然后,可以如图10所示,利用构图的光致抗蚀剂2002为掩模,例如通过RIE来依次刻蚀停止层2001和衬底2002,以形成初始鳍2004。之后,可以去除光致抗蚀剂2002。由于刻蚀深度D相对较大,刻蚀深度在衬底上事实上有较大变化。
然后,如图11所示,可以在形成有初始鳍的衬底2000上例如通过淀积来形成电介质层2006。关于电介质层2006及其形成,可以参见以上结合图3的说明,在此不再赘述。
随后,可以对电介质层2006进行回蚀。例如,如图12所示,可以对电介质层2006进行平坦化处理,例如CMP。该平坦化处理可以停止于停止层2001。然后,如图13所示,可以相对于衬底2000、初始鳍2004(例如,硅)以及停止层2001(例如,氮化硅),对电介质层2006(例如,氧化硅)进行选择性刻蚀。通过选择性刻蚀,电介质层2006相对于初始鳍2004的顶面凹入,从而露出初始鳍2004的一部分。初始鳍2004的露出部分随后充当最终器件的鳍。
尽管如上所述,鳍2004的顶面到其底面的距离D在衬底上存在较大变化,但是由于电介质层2006的刻蚀深度相对较小,从而对该刻蚀的控制相对容易,并因此可以更加精确地控制从鳍2004的顶面到电介质层2006的顶面的距离(h,至少部分地决定最终器件的鳍高度并因此决定最终器件的沟道宽度),使得h在衬底上基本保持一致。
随后,可以如图14所示,在图13所示的鳍结构上来形成半导体器件。例如,可以在鳍结构上例如通过淀积依次形成高K栅介质层2010、功函数调节层2012和栅导体层1014,并对它们进行构图以形成栅堆叠。关于高K栅介质层2010、功函数调节层2012和栅导体层1014及其形成,可以参见以上结合图7和8的说明,在此不再赘述。
在以上的描述中,对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解,可以通过各种技术手段,来形成所需形状的层、区域等。另外,为了形成同一结构,本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外,尽管在以上分别描述了各实施例,但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围,本领域技术人员可以做出多种替代和修改,这些替代和修改都应落在本公开的范围之内。
Claims (10)
1.一种制造鳍结构的方法,包括:
对衬底进行构图,以在衬底的选定区域上形成高度不同的多个初始鳍,其中每个初始鳍具有5-30nm的宽度;
在衬底上形成电介质层,使得衬底上初始鳍之间的间隙中的电介质层的厚度超过初始鳍的高度从而填满所述间隙并实质上覆盖初始鳍,其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上初始鳍之间的间隙中的电介质层厚度;
去除电介质层的一部分和初始鳍的一部分,使得所述电介质层与初始鳍齐平;以及
对电介质层进行回蚀,以露出初始鳍的一部分,
其中,初始鳍的露出的所述部分用作鳍,
其中,衬底在相邻初始鳍之间的部分的表面高度在衬底上有变化,所述多个初始鳍各自的顶面彼此实质上齐平,且电介质层在回蚀之后具有实质上平坦的顶面。
2.根据权利要求1所述的方法,其中,通过高密度等离子体淀积,在衬底上形成电介质层。
3.根据权利要求1所述的方法,其中,位于每一初始鳍顶部的电介质层厚度小于与其相邻的初始鳍之间间距的二分之一。
4.根据权利要求1所述的方法,其中,位于初始鳍顶部的电介质层厚度小于位于衬底上的电介质层厚度的三分之一。
5.根据权利要求1所述的方法,其中,对电介质层进行回蚀的操作包括:
对电介质层进行平坦化处理,以露出初始鳍的顶面;以及
对电介质层进行选择性刻蚀。
6.根据权利要求5所述的方法,其中,在平坦化处理中,在露出初始鳍的顶面之后,进行进一步的平坦化处理。
7.根据权利要求6所述的方法,在进一步平坦化处理之后,还包括:
对由于进一步平坦化处理而露出的初始鳍的端部进行热氧化。
8.根据权利要求5所述的方法,在对衬底进行构图之前,还包括:
在衬底上形成停止层,
其中,在对电介质层进行平坦化处理时,平坦化处理停止于该停止层。
9.根据权利要求1所述的方法,其中,电介质层包括氧化物。
10.根据权利要求1所述的方法,其中,在回蚀电介质层之后,每一鳍的顶面大致持平,电介质层的顶面大致持平。
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