CN103811321A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103811321A
CN103811321A CN201210451050.2A CN201210451050A CN103811321A CN 103811321 A CN103811321 A CN 103811321A CN 201210451050 A CN201210451050 A CN 201210451050A CN 103811321 A CN103811321 A CN 103811321A
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grid
mosfet
side wall
gate
semiconductor substrate
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CN103811321B (zh
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朱慧珑
梁擎擎
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Institute of Microelectronics of CAS
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Priority to CN201210451050.2A priority Critical patent/CN103811321B/zh
Priority to PCT/CN2012/085624 priority patent/WO2014071663A1/zh
Priority to US14/144,275 priority patent/US9117926B2/en
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Abstract

公开了一种半导体器件和一种制造半导体器件的方法。该方法包括：在半导体衬底中形成具有第一栅长的第一MOSFET；以及在半导体衬底中形成具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体和栅极电介质，栅极电介质将栅极导体与半导体衬底隔开。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及用于集成具有不同栅长的金属氧化物半导体场效应晶体管(MOSFET)的半导体器件及其制造方法。
背景技术
随着半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了使用包括高K栅介质和金属栅极导体的栅堆叠。为避免栅堆叠的性能退化，包括这种栅堆叠的半导体器件通常利用替代栅工艺来制造。替代栅工艺涉及在栅侧墙之间限定的孔隙中形成高K栅介质和金属栅极导体。然而，由于器件尺寸的缩小，要在如此小的栅极开口中形成高K栅介质和金属导体越来越困难。
因此，仍然期望制造和集成小栅极尺寸的MOSFET的方法。尤其期望在一个半导体衬底集成不同栅长的MOSFET的方法。
发明内容
本公开的目的至少部分地在于提供一种集成具有不同栅长的MOSFET的方法。
根据本公开的方法，提供一种制造半导体器件的方法，包括：在半导体衬底中形成具有第一栅长的第一MOSFET；以及在半导体衬底中形成具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体和栅极电介质，栅极电介质将栅极导体与半导体衬底隔开。
根据本公开的另一方面，提供一种半导体器件，包括：半导体衬底；位于半导体衬底中的具有第一栅长的第一MOSFET；以及位于半导体衬底中的具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体和栅极电介质，栅极电介质位于栅极导体与半导体衬底之间。
本公开针对第一MOSFET和第二MOSFET形成不同结构的栅堆叠，其中第一MOSFET包括常规的栅堆叠，第二MOSFET包括侧墙形式的栅堆叠。因此，第二MOSFET的栅长可以比第一MOSFET的栅长小很多。本公开提供了在一个半导体衬底上集成不同栅长的MOSFET的方法。在本公开的优选实施例中，首先形成牺牲侧墙，然后采用栅堆叠替代牺牲侧墙，这可以减少掩模的使用以及对复杂的光刻工艺的需求，从而降低制造成本。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-11是示出了根据本公开的第一实施例的制造半导体器件流程的示意图。
图12-19是示出了根据本公开的第二实施例的制造半导体器件流程的一部分步骤的示意图。
图20-27是示出了根据本公开的第三实施例的制造半导体器件流程的一部分步骤的示意图。
具体实施方式
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在......上面”或“在......上面并与之邻接”的表述方式。
在本申请中，术语“半导体结构”指在制造半导体器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
除非在下文中特别指出，MOSFET的各个部分可以由本领域的技术人员公知的材料构成。半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。栅极导体可以由能够导电的各种材料形成，例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料，例如为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx|和所述各种导电材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3，氮化物例如包括Si3N4，硅酸盐例如包括HfSiOx，铝酸盐例如包括LaAlO3，钛酸盐例如包括SrTiO3，氧氮化物例如包括SiON。并且，栅极电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
在常规工艺中，在利用“伪”栅堆叠以及该伪栅堆叠两侧的侧墙在衬底中制造出源区和漏区之后，保留两侧的侧墙而在侧墙之间限定出孔隙，通过填充孔隙来形成真正的栅堆叠。与此不同，在本公开中，提出了一种“替代侧墙”工艺。在形成源区和漏区之后，保留位于源区和漏区之一一侧的材料层，并在该保留的材料层的侧壁上以侧墙的形式形成栅堆叠(特别是，栅极导体)。从而可以在较大的空间(具体地，大致为栅区+源区和漏区中另一个的区域)上来形成栅堆叠，相比于仅在侧墙之间的小栅极开口中形成栅堆叠的常规工艺，可以使得工艺更加容易进行。
本公开可以各种形式呈现，以下将描述其中一些示例。
参照图1-11描述根据本公开的第一实施例的制造半导体器件的流程。
如图1所示，提供衬底101。该衬底101可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在衬底101上，可以形成有浅沟槽隔离(STI)102，用以隔离单独器件的有源区。STI 102例如可以包括氧化物(例如，氧化硅)。这里需要指出的是，在以下描述的示例中，为方便说明，仅形成两个半导体器件的情况，其中STI 102在图1中的左侧和右侧限定两个半导体器件的有源区。但是本公开不局限于此，而是可以应用于形成更多个半导体器件的情况。
在半导体衬底101上已经采用常规的工艺形成第一MOSFET 100。第一MOSFET 100的第一有源区是图1中由STI 102限定的左侧区域。第一MOSFET 100包括在半导体衬底上形成的栅堆叠，该栅堆叠包括位于半导体衬底101上的栅极电介质102以及位于栅极电介质102上的栅极导体103。栅极电介质102将栅极导体103与半导体衬底101隔开。侧墙105围绕栅极导体103而形成。第一MOSFET 100还包括在半导体衬底101中形成的源/漏区(未示出)、延伸区(未示出)和可选的晕圈区(未示出)。
正如本领域的技术人员可以理解的那样，可以采用各种工艺制造第一MOSFET 100，例如采用已知的“先栅工艺”或“替代栅工艺”。
接下来，通过已知的沉积工艺，如CVD(化学气相沉积)、原子层沉积、溅射等，在半导体结构的表面上形成厚度约为100-200nm的第一掩蔽层106。第一掩蔽层106可以由氧化物(例如，氧化硅)组成。
然后，通过旋涂在第一掩蔽层106上形成光致抗蚀剂层(未示出)，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层形成图案。利用光致抗蚀剂层作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，去除第一掩蔽层106位于图1的右侧区域(即STI 102围绕的第二有源区)中的部分。通过在溶剂中溶解或灰化去除光致抗蚀剂层。
在上述图案化步骤之后，第一掩蔽层106仅覆盖第一MOSFET 100的第一有源区，如图2所示。
接下来，通过上述的已知的沉积工艺，在半导体结构的表面上形成厚度约为100-200nm的第二掩蔽层107。第二掩蔽层107可以由氮化物(例如，氮化硅)组成。优选地，第二掩蔽层107可以包括氮化物层和氧化物层，氧化物层位于氮化物层上方。采用第一掩蔽层106作为停止层，对第二掩蔽层107进行平面化处理，例如采用化学机械抛光(CMP)，获得平整的半导体结构的表面。结果，第一掩蔽层106和第二掩蔽层107邻接，并且第一掩蔽层106覆盖第一MOSFET 100的第一有源区，而第二掩蔽层107覆盖将要形成的第二MOSFET的第二有源区。
例如采用光致抗蚀剂掩模，通过上述的图案化步骤在第二掩蔽层107中形成开口，开口暴露第二有源区中半导体衬底101的一部分的表面。优选地，开口与第一掩蔽层106相邻并且暴露第一有源区和第二有源区之间的STI 102的一部分，如图3所示。开口暴露半导体衬底101中将要形成源区和漏区中的一个的部分。
接下来，穿过开口，沿着垂直于半导体衬底101的主表面的方向进行第一离子注入以形成延伸区108a。在第一离子注入中，对于p型器件，可以通过注入p型杂质如In、BF2或B；对于n型器件，可以通过注入n型杂质如As或P，来形成延伸区。
然后，仍然穿过开口，沿着与半导体衬底101的主表面倾斜的方向进行第二离子注入以形成源区和漏区中的一个108b。第二离子注入的方向相对于第一离子注入的方向顺时针地偏离某一角度(小于90°，例如为15°)，使得在第二离子注入期间，第二掩蔽层107阻挡一部分离子。结果，注入的离子仅在靠近STI 102的位置进入半导体衬底101中而形成源区和漏区中的一个。第二离子注入的深度比第一离子注入的深度大。在第二离子注入中，对于p型器件，可以采用上述的p型杂质；对于n型器件，可以采用上述的n型杂质。正如本领域的技术人员可以理解的那样，延伸区108a和源区和漏区中的一个108b彼此叠加，两者没有清晰的边界，如图4所示。
可选地，在第一离子注入之前，还可以穿过开口进行附加的离子注入以形成晕圈(未示出)。该附加的离子注入的方向相对于第一离子注入的方向逆时针偏离某一角度(小于90°，例如为15°)，使得在该附加的离子注入期间，第一掩蔽层106阻挡一部分离子。结果，注入的离子仅在远离STI 102的位置进入半导体衬底101中而形成晕圈。该附加的离子注入的深度比第一离子注入的深度和第二离子注入的深度均大。在该附加的离子注入中，对于p型器件，可以采用上述的n型杂质；对于n型器件，可以采用上述的p型杂质。
可选地，在第二离子注入之后，可以进行退火处理例如尖峰退火、激光退火、快速退火等，以激活注入的杂质。
接下来，通过上述已知的沉积工艺，在半导体结构上形成第三掩蔽层109(例如，氧化物)，第三掩蔽层109的材料填充开口。进行平面化处理，例如采用CMP，获得平整的半导体结构的表面，如图5所示。用于填充开口的第三掩蔽层109的材料可以与第一掩蔽层106相同。如果第二掩蔽层107包括氮化物层和氧化物层，则CMP步骤只需停止于氮化物层即可。
接下来，采用合适的蚀刻剂，通过上述的干法蚀刻或湿法蚀刻，相对于第一掩蔽层106、第三掩蔽层109选择性去除第二掩蔽层107，如图6所示。该蚀刻停止在半导体衬底101的表面上。优选地，可以在半导体衬底101的表面上设置附加的氧化物层(未示出)，以提供蚀刻的选择性。
接下来，通过上述已知的沉积工艺，在半导体结构的表面上沉积例如8-30纳米的氮化物层，然后通过各向异性蚀刻在第一掩蔽层106的侧壁上形成牺牲侧墙110，如图7所示。该牺牲侧墙110的形成和材料与常规的栅极侧墙相同。如下文将要描述的那样，该牺牲侧墙110最终去除并由栅极堆叠代替。
接下来，以牺牲侧墙110作为硬掩模，按照结合图4已经描述的方法，通过第三离子注入和第四离子注入在半导体衬底101中形成延伸区111a和源区和漏区中的另一个111b，如图8所示。
可选地，在第三离子注入之前，还可以进行附加的离子注入以形成晕圈(未示出)。
可选地，在第四离子注入之后，可以进行退火处理例如尖峰退火、激光退火、快速退火等，以激活注入的杂质。
接下来，采用合适的蚀刻剂，通过上述的干法蚀刻或湿法蚀刻，相对于第一掩蔽层106、第三掩蔽层109选择性去除牺牲侧墙110。
可选地，为更好地控制短沟道效应以及抑制带间泄露，可以通过第五离子注入(图中箭头所示)，形成超陡后退阱(SSRW)112，如图9所示。例如，对于p型器件，可以通过注入n型杂质如As或P或Sb；对于n型器件，可以通过注入p型杂质如In、BF2或B，来形成SSRW，从而有效改善带间泄露电流。这里需要指出的是，图9中的SSRW 112仅仅是为了图示方便而示出为规则的矩形形状。实际上，SSRW 112的形状由注入工艺决定，并且可能没有清晰的边界。
接下来，通过已知的沉积工艺，在半导体结构的表面上依次形成共形的电介质层(例如HfO2)以及栅极导体层(例如多晶硅)。对导体层进行各向异性蚀刻，以去除导体层与半导体衬底101的主表面平行延伸的部分。栅极导体层位于第三掩蔽层109的侧壁上的垂直延伸的部分保留，形成侧墙形式的栅极导体113。进一步地，采用栅极导体113作为硬掩模并采用合适的蚀刻剂，相对于栅极导体113和第三掩蔽层109选择性地去除电介质层的暴露部分，以形成栅极电介质114。栅堆叠包括栅极电介质114和栅极导体113，其中栅极电介质114将栅极导体113与半导体衬底101隔开，如图10所示。
电介质层的厚度约为2-4纳米。栅极导体层的厚度约为9-30纳米。结果，通过控制栅极导体层的厚度，所形成的栅极导体113与图7所示的牺牲侧墙110大致对准，进而使得所形成的栅极导体113与延伸区111a和源区和漏区中的另一个111b大致对准。
可选地，在栅极导体113和栅极电介质114之间还可以形成功函数调节层(未示出)。功函数调节层例如可以包括TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTa、NiTa、MoN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSi、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx及其组合，厚度可以约为2-10nm。正如本领域的技术人员已知的那样，功函数调节层是优选的层，包含功函数调节层的栅堆叠(如HfO2/TiN/多晶Si)可以有利地获得减小的栅极漏电流。
结果，在第二有源区中形成包括延伸区108a、111a，源/漏区108b、111b、SSRW 112、包括栅极导体113和栅极电介质114的第二MOSFET12。
接下来，通过上述已知的沉积工艺，在半导体结构上形成电介质层115。对电介质层115进行平面化处理，例如采用化学机械抛光(CMP)，获得平整的半导体结构的表面，如图10所示。在图中示出仅保留电介质层115覆盖第二MOSFET的部分。替代地，电介质层115可以覆盖第一MOSFET和第二MOSFET二者。第一掩蔽层106、第三掩蔽层109和电介质层115一起作为层间电介质(ILD)。
参照图12-19描述根据本公开的第二实施例的制造半导体器件的流程。在第二实施例中，与第一实施例对应的元件采用类似的附图标记表示，并且省略对其材料、结构和制造工艺的详细描述。
接着图1所示的步骤，与图2所示的步骤类似，在半导体结构的表面上形成第一掩蔽层106，并且图案化第一掩蔽层106。在图案化步骤之后，第一掩蔽层106不仅覆盖第一MOSFET 100的第一有源区，而且覆盖将要形成的第二MOSFET的第二有源区的一部分。接着，与图7所示的步骤类似，在第一掩蔽层106经由开口暴露的一个侧壁上形成牺牲侧墙110’，如图12所示。
接下来，与图8所示的步骤类似，以第一掩蔽层106和牺牲侧墙110’作为硬掩模，通过第一离子注入和第二离子注入在半导体衬底101中形成延伸区111a和源区和漏区中的一个111b，如图13所示。
接下来，在半导体结构的表面上形成第二掩蔽层107’。对第一掩蔽层106和第二掩蔽层107’进行平面化处理，使得第二掩蔽层107’与第一掩蔽层106齐平，并且暴露牺牲侧墙110’的顶部表面，如图14所示。
接下来，采用光致抗蚀剂掩模遮挡第一MOSFET 100的第一有源区，相对于第二掩蔽层107’(例如，氧化硅)以及牺牲侧墙110’(例如，多晶硅或非晶硅)，选择性刻蚀第一掩蔽层106(例如，氮化硅)的一部分，以形成暴露第二有源区中半导体衬底101的一部分的表面的开口，如图15所示。这种选择性刻蚀例如可以通过热磷酸来进行。
接下来，与图8所示的步骤类似，以第一掩蔽层106、第二掩蔽层107’和牺牲侧墙110’作为硬掩模，通过第三离子注入和第四离子注入在半导体衬底101中形成延伸区108a和源区和漏区中的另一个108b，如图16所示。
接下来，与图9所示的步骤类似，通过蚀刻，相对于第一掩蔽层106、第二掩蔽层107’选择性去除牺牲侧墙110’。可选地，通过第五离子注入，经由开口形成超陡后退阱(SSRW)112，如图17所示。
接下来，与图10所示的步骤类似，在第二掩蔽层107’经由开口暴露的一个侧壁上形成栅堆叠，该栅堆叠包括栅极导体118和位于栅极导体118和半导体衬底101之间的栅介质113，如图18所示。可选地，在栅极导体113和栅极电介质114之间还可以形成功函数调节层(未示出)。
接下来，与图5所示的步骤类似，在半导体结构上形成第三掩蔽层109’以填充开口，如图19所示。
参照图20-27描述根据本公开的第三实施例的制造半导体器件的流程。在第三实施例中，与第一实施例对应的元件采用类似的附图标记表示，并且省略对其材料、结构和制造工艺的详细描述。
接着图2所示的步骤，在形成第一掩蔽层106之后，与图3所示的步骤类似，形成覆盖将要形成的第二MOSFET的第二有源区的第二掩蔽层107”。在第二掩蔽层107”中形成开口。然而，与图3所示的步骤不同之处在于该开口暴露半导体衬底101中将要形成源区和漏区中的一个的部分，以及与该源区和漏区中的一个相邻的半导体衬底101中将要用作沟道区的部分。接着，与图9所示的步骤类似，可选地，经由该开口进行第一离子注入，在半导体衬底101中形成超陡后阱阱(RRSW)112，如图20所示。
然后，与图7所示的步骤类似，在第二掩蔽层107”经由开口暴露的一个侧壁上形成牺牲侧墙110”，如图21所示。
然后，与图4所示的步骤类似，以牺牲侧墙110”作为硬掩模，穿过开口进行第二离子注入以形成延伸区108a，接着，沿着与半导体衬底101的主表面倾斜的方向进行第三离子注入以形成源区和漏区中的一个108b，如图22所示。在第三离子注入之后，可选地，执行附加的离子注入以形成晕圈，或者进一步可选地，进行退火处理以激活注入的杂质。
然后，采用合适的蚀刻剂，通过上述的干法蚀刻或湿法蚀刻，相对于第一掩蔽层106、第二掩蔽层107”选择性去除牺牲侧墙110”。接着，与图10所示的步骤类似，在第二掩蔽层107”经由开口暴露的一个侧壁上形成栅堆叠，该栅堆叠包括栅极导体118和位于栅极导体118和半导体衬底101之间的栅介质113，如图23所示。可选地，在栅极导体113和栅极电介质114之间还可以形成功函数调节层(未示出)。
然后，与图5所示的步骤类似，在半导体结构上形成第三掩蔽层109”以填充第二掩蔽层107”中的开口，如图24所示。
然后，与图6所示的步骤类似，采用合适的蚀刻剂，通过上述的干法蚀刻或湿法蚀刻，相对于第一掩蔽层106、第三掩蔽层109”选择性去除第二掩蔽层107”，如图25所示。
然后，与图8所示的步骤类似，以牺牲侧墙110”作为硬掩模，通过第四离子注入和第五离子注入在半导体衬底101中形成延伸区111a和源区和漏区中的另一个111b，如图26所示。
然后，与图11所示的步骤类似，形成至少覆盖第二MOSFET的电介质层115”，如图27所示。
上述根据本公开的第一实施例、第二实施例和第三实施例描述了在形成常规的第一MOSFET之后进一步形成第二MOSFET的步骤。第二MOSFET的栅堆叠形成在掩蔽层的侧壁上。因此，第二MOSFET的栅长可以显著小于第一MOSFET的栅长，例如，第二MOSFET的栅长约为5-20nm。
在图11、图19和图27所示的步骤之后，可以在所得到的半导体结构上形成层间绝缘层、位于层间绝缘层中的通孔、位于层间绝缘层上表面的布线或电极，从而完成MOSFET的其他部分。
在以上的描述中，对于各层的构图、蚀刻等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (8)

1.一种制造半导体器件的方法，包括：
在半导体衬底中形成具有第一栅长的第一MOSFET；以及
在半导体衬底中形成具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，
其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体和栅极电介质，栅极电介质将栅极导体与半导体衬底隔开。
2.根据权利要求1所述的方法，其中形成第二MOSFFET包括：
以掩蔽层作为掩模形成第二MOSFET的源区和漏区之一；
以牺牲侧墙作为掩模形成第二MOSFET的源区和漏区中另一个；以及
采用栅堆叠替代牺牲侧墙。
3.根据权利要求1所述的方法，其中形成第二MOSFET包括：
以牺牲侧墙作为掩模形成第二MOSFET的源区和漏区之一；
以牺牲侧墙作为掩模形成第二MOSFET的源区和漏区中另一个；以及
采用栅堆叠替代牺牲侧墙。
4.根据权利要求1所述的方法，其中形成第二MOSFFET包括：
以牺牲侧墙作为掩模形成第二MOSFET的源区和漏区之一；
采用栅堆叠替代牺牲侧墙；以及
以掩蔽层作为掩模形成第二MOSFET的源区和漏区中另一个。
5.根据权利要求2至4中任一项所述的方法，其中采用以下步骤形成牺牲侧墙：
形成具有一个暴露的侧壁的另一个掩蔽层；以及
在该另一个掩蔽层的侧壁上形成牺牲侧墙。
6.根据权利要求5所述的方法，其中采用栅堆叠替代牺牲侧墙包括：
去除牺牲侧墙；
形成共形的电介质层，电介质层至少覆盖该另一个掩蔽层的侧壁和半导体衬底的表面；
在电介质层上形成共形的导体层；
将导体层图案化为栅极导体；以及
以栅极导体作为掩模，将电介质层图案化为栅极电介质。
7.根据权利要求6所述的方法，其中栅极导体的厚度与牺牲侧墙的厚度大致相等。
8.一种半导体器件，包括：
半导体衬底；
位于半导体衬底中的具有第一栅长的第一MOSFET；以及
位于半导体衬底中的具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，
其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体和栅极电介质，栅极电介质位于栅极导体与半导体衬底之间。
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