CN103165674B - 具有多阈值电压的FinFET - Google Patents

具有多阈值电压的FinFET Download PDF

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Publication number
CN103165674B
CN103165674B CN201210058769.XA CN201210058769A CN103165674B CN 103165674 B CN103165674 B CN 103165674B CN 201210058769 A CN201210058769 A CN 201210058769A CN 103165674 B CN103165674 B CN 103165674B
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metal layer
metal level
semiconductor fin
work content
dielectric
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CN103165674A (zh
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郭博钦
李显铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件，包括：衬底、位于衬底上的半导体鳍以及位于半导体鳍的顶面和侧壁上的栅极介电层。栅极介电层将栅电极与半导体鳍间隔开。栅电极包括位于半导体鳍上方并且与其对准的顶部，以及位于介电层的侧壁部分上的侧壁部分。栅电极的顶部具有第一功函，栅电极的侧壁部分具有与第一功函不同的第二功函。本发明还提供了一种具有多阈值电压的FinFET。

Description

具有多阈值电压的FinFET
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种具有多阈值电压的FinFET。
背景技术
随着集成电路的尺寸越来越小以及对集成电路速度的越来越苛刻的要求，晶体管需要在更小的尺寸情况下具有更高的驱动电流。由此发展出了鳍式场效应晶体管(FinFET)。与平面型器件相比，FinFET晶体管具有更好的短沟道效应(SCE)，该短沟道效应使得晶体管能够持续缩小，并且由于其沟道宽度的增大实现了更高的驱动电流。通过形成沟道来实现FinFET沟槽宽度的增大，该沟道包括位于鳍的侧壁上的部分以及位于鳍的顶面上的部分。FinFET可以是双栅极FET，该双栅极FET包括位于相应的鳍的侧壁上的沟道，但在相应的鳍的顶面上没有沟道。FinFET也可以是三栅极FET，该三栅极FET包括位于相应的鳍的侧壁和顶面上的沟道。由于晶体管的驱动电流与沟槽的宽度成比例，所以提高了FinFET的驱动电流。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，包括：衬底；半导体鳍，位于所述衬底上方；栅极介电层，位于所述半导体鳍的顶面和侧壁上；以及栅电极，通过所述栅极介电层与所述半导体鳍间隔开，其中，所述栅电极包括位于所述半导体鳍上方并且与所述半导体鳍对准的顶部以及位于所述介电层的侧壁部分上的侧壁部分，并且其中，所述栅电极的顶部具有第一功函，并且所述栅电极的侧壁部分具有与所述第一功函不同的第二功函。
在该器件中，所述第一功函高于所述第二功函。
在该器件中，所述第一功函低于所述第二功函。
在该器件中，所述栅电极包括：第一金属层，位于所述半导体鳍上方并且与所述半导体鳍对准，其中，所述第一金属层不延伸到所述半导体鳍的侧面；以及第二金属层，包括位于所述半导体鳍上方并且与所述半导体鳍对准的第一部分以及在所述半导体鳍的侧面上延伸的第二部分，其中，所述第一金属层和所述第二金属层包含不同的材料。
在该器件中，还包括：保护层，位于所述介电层上方并且位于所述第一金属层和所述第二金属层下方，其中，所述第一金属层和所述第二金属层均接触所述保护层。
在该器件中，所述保护层包含氮化钛。
在该器件中，所述第一功函和所述第二功函具有大于大约0.2eV的差值。
根据本发明的另一方面，提供了一种器件，包括：衬底；半导体鳍，位于所述衬底上方，其中，所述半导体鳍是所述鳍式场效应晶体管(FinFET)的一部分；栅极介电层，位于所述半导体鳍的顶面和侧壁上；以及栅电极，通过所述栅极介电层与所述半导体鳍间隔开，其中，所述栅电极包括：第一金属层，位于所述半导体鳍上方并且与所述半导体鳍对准，其中，所述第一金属层基本上不包括低于所述半导体鳍的顶面的部分；以及第二金属层，包括位于所述第一金属层上方并且与所述第一金属层对准的第一部分以及低于所述半导体鳍的顶面的第二部分，其中，所述第一金属层和所述第二金属层包含不同的材料，并且其中，所述第一金属层和所述第二金属层的所述第一部分形成所述FinFET的栅电极的顶部，所述第二金属层的所述第二部分形成所述FinFET的所述栅电极的侧壁部分。
在该器件中，所述第一金属层具有第一功函，所述第二金属层具有第二功函，并且其中，所述第一功函大于所述第二功函。
在该器件中，所述第一金属层具有第一功函，所述第二金属层具有第二功函，并且其中，所述第一功函小于所述第二功函。
在该器件中，还包括：保护层，位于所述介电层上方并且位于所述第一金属层和所述第二金属层下方，其中，所述第一金属层和所述第二金属层均接触所述保护层。
在该器件中，所述保护层包含氮化钛。
根据本发明的又一方面，提供了一种方法，包括：在半导体鳍上形成栅极电介质，其中，所述栅极电介质包括位于所述半导体鳍的顶面上方的顶部以及位于所述半导体鳍的侧壁上的侧壁部分；在所述栅极电介质的顶部上方形成第一金属层，其中，所述第一金属层不包括在所述栅极电介质的所述侧壁部分上延伸的部分；以及形成第二金属层，其中，所述第二金属层包括位于所述第一金属层上方的第一部分以及在所述栅极电介质的侧壁部分上延伸的第二部分，并且其中，所述第一金属层和所述第二金属层包含不同的材料。
在该器件中，使用非共形沉积方法执行形成所述第一金属层的步骤。
在该器件中，使用共形沉积方法形成所述第二金属层。
在该器件中，形成所述第一金属层的步骤包括：沉积所述第一金属层，并且执行蚀刻步骤来去除位于所述栅极电介质的侧壁部分上的所述第一金属层的部分。
在该器件中，所述第一金属层和所述第二金属层的所述第一部分形成栅电极的顶部，所述第二金属层的所述第二部分形成所述栅电极的第二部分，并且其中，所述栅电极的顶部和所述栅电极的所述第二部分具有不同的功函。
在该器件中，还包括：在形成所述栅极电介质的步骤之后并且在形成所述第一金属层的步骤之前，在所述栅极电介质上方形成保护层，其中，所述第一层和所述第二层均与所述保护层相接触。
在该器件中，还包括：在所述保护层上方形成伪栅极；以及去除所述伪栅极，其中，在去除所述伪栅极的步骤之后暴露出所述保护层，并且其中，在去除所述伪栅极的步骤之后执行形成所述第一金属层和所述第二金属层的步骤。
在该器件中，所述第一金属层和所述第二金属层具有大于大约0.1eV的功函差。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1至图6B是根据一些示例性实施例的制造鳍式场效应晶体管(FinFET)的中间阶段的截面图，其中，采用先栅极方法来形成FinFET；以及
图7至图10是根据一些示例性实施例的制造FinFET的中间阶段的截面图，其中，采用后栅极方法来形成FinFET。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所论述的具体实施例仅仅是说明性的，而不限制本发明的范围。
根据各个实施例提供了鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。论述了根据实施例的FinFET的变型和操作。在各个视图和说明性实施例中，类似的参考标号被用于表示类似的元件。
图1至图6B是根据一些示例性实施例的制造鳍式场效应晶体管(FinFET)的中间阶段的截面图。参考图1A和图1B，形成初始结构。从图1A中的剖面线1B-1B得到图1B中所示的截面图。该初始结构包括部分晶圆10，该管芯还包括衬底20。衬底20可以是半导体衬底，该半导体衬底可以进一步是硅衬底，锗衬底、或由其他半导体材料形成的衬底。衬底20可以掺杂有p型或n型杂质。隔离区域(诸如，浅沟槽隔离(STI)区域22)可以形成在衬底20中。半导体鳍24形成在STI区域22上方。在一些实施例中，半导体鳍24包括与衬底20相同的材料，并且可以由半导体衬底20形成，例如，通过对STI区域22进行开槽。
参考图2，界面层26形成在鳍24上。界面层26可以由化学氧化物、热氧化物等等形成。在一些实施例中，可以通过氧化鳍24的表层来形成界面层26。栅极介电层28形成在界面层26上。根据一些实施例，栅极介电层28包括氧化硅、氮化硅、或其多层。在可选实施例中，栅极介电层28由高k介电材料形成，并且由此在整个说明中可选地被称作高k介电层28。高k介电层28可以具有大于大约7.0的k值，并且可以包括氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb的硅化物及其组合。高k介电层28的示例性材料包括MgOx、BaTixOy、BaSrxTiyOz、PbTixOy、PbZrxTiyOz等，X、Y和Z的值在0和1之间。高k介电层28的厚度可以在大约1nm和大约10nm之间。然而，本领域普通技术人员将意识到，整个说明书中所列举的尺寸是实例并且可以变成不同的值。栅极介电层28的形成方法可以包括分子束沉积(MBD)、原子层沉积(ALD)、物理汽相沉积(PVD)等。
在栅极介电层28上方可以形成保护层(cappinglayer)30。在可选实施例中，不形成保护层30，并且随后形成的金属层34和40(图2中未示出，请参考图3A至图4)直接形成在栅极介电层28上并与其相接触。在一些实施例中，保护层30具有接近硅的导带和价带的中间水平的中间禁带功函(mid-gapworkfunction)。在一些示例性实施例中，保护层30包括氮化钛(TiN)。在可选实施例中，保护层30的示例性材料包括含钽材料和/或含钛材料，诸如，TaC、TaN、TaAlN、TaSiN、及其组合。
参考图3A，非共形金属层34形成在鳍24上方并且与其对准。在一些实施例中，使用非共形沉积方法(诸如，PVD)来形成金属层34。因此，非共形金属层34包括位于鳍24上方并且与其对准的顶部，但不包括位于保护层30的侧壁部分上的部分。在可选实施例中，如虚线所示的那样，可以在保护层30的侧壁部分上形成由金属层34所构成的薄层。根据这些实施例，金属层34的侧壁部分(如果存在的话)的厚度T2明显小于金属层34的顶部的厚度T1。比例T2/T1可以小于大约2.0，或在一些示例性实施例中小于大约0.1。当非共形金属层34包括位于保护层30的侧壁部分上的薄层时，可以执行蚀刻步骤来蚀刻和去除金属层34的侧壁部分。在该蚀刻过程中，可以不形成用于覆盖金属层34的顶部的蚀刻掩模。在可选实施例中，不执行蚀刻步骤，并且将薄金属层34保留在保护层30的侧壁部分上。在蚀刻步骤中还可以减小保护层30的顶部的厚度。由于厚度T1大于厚度T2，所以在蚀刻之后，金属层34仍然保留在鳍24上方并且与其对准，但不保留金属层34的侧壁部分。在一些实施例中，厚度T1大于大约并且可以在和大约之间，金属层34的功函由此可以影响所得到的FinFET的阈值电压。
图3B示出了根据示例性实施例的金属层34的形成。在这些实施例中，最初可以使用共形沉积方法(诸如，ALD或化学汽相沉积(CVD)方法)来形成金属层34。在形成金属层34之后，形成并且图案化掩模36来覆盖金属层34的顶部，并且掩模36没有覆盖金属层34的侧壁部分。掩模36可以包括光刻胶或硬掩模，诸如，氮化硅。然后，在蚀刻步骤中去除金属层34的暴露的侧壁部分，并且不蚀刻金属层34的顶部。在蚀刻步骤之后，去除掩模36。
参考图4，形成了金属层40。金属层40包括位于金属层34上面的部分。另外，金属层在保护层30的侧壁部分上延伸。在一些实施例中，金属层40是共形层，其中，顶厚度T3与侧壁厚度T4彼此接近。在一些示例性实施例中，厚度T3和T4之间的差值小于T3和T4两者厚度的大约百分之20，或小于大约百分之10。厚度T3和T4可以大于大约并且在一些实施例中可以在大约和大约之间。
金属层34和40包括不同的材料，并且可以具有不同的功函。金属层34的功函WF34可以大于或小于金属层40的功函WF40。在一些实施例中，功函WF34和WF40可以具有大于大约0.1eV，或在大约0.1eV和大约1.0eV之间的差值，然而，该差值可以更大或更小。在其中所得到的FinFET60(图6A)是P型FinFET的实施例中，功函WF34和WF40中的每个都可以在大约4.1eV和大约5.2eV之间。在其中所得到的FinFET60(图6A)是N型FinFET的实施例中，功函WF34和WF40中的每个都可以在大约4.1eV和大约5.2eV之间。在一些实施例中，金属层34和40的材料可以选自于TiN、TaN、TaAlC、TiAl、TaC、TaAl、Co及其组合。
参考图5A和图5B，形成了厚金属层42。在一些实施例中，厚金属层42由铝或铝合金形成。例如，厚金属层42的厚度T5可以大于大约50nm，并且可以在大约50nm和大约120nm之间。在形成厚金属层42之后，图案化金属层42、40和34、保护层30、介电层28以及界面层26，从而形成栅极堆叠件，其中，可以从图5B中看出该栅极堆叠件。从图5A中的平面剖切线5B-5B得到图5B中的截面图。如图5B所示，金属层34形成在鳍24的中间部分上。另外，金属层34位于半导体鳍24的顶面上方，并且基本上金属层34的任何部分都不延伸到半导体鳍24的顶面下方。金属层40和42、保护层30、介电层28以及界面层26也在鳍24的顶面和侧壁上延伸。
图6A和图6B示出了栅极隔离件46、源极和漏极区域48、源极/漏极硅化物区域50、接触塞52以及层间电介质(ILD)54的形成。由此完成了FinFET60的形成。参考图6A，在一些实施例中，栅极隔离件46首先形成在界面层26、介电层28、保护层30以及金属层34、40和42的侧壁上。然后，形成了源极和漏极区域48、在一些实施例中，通过深注入形成源极和漏极区域48。根据FinFET60的传导类型，可以注入n型杂质来形成n型FinFET60，或可以注入p型杂质来形成p型FinFET60。深源极/漏极区域48的掺杂浓度可以在大约1×1020/cm3和大约1×1021/cm3之间或更高。在一些实施例中，源极和漏极区域48的形成也可以包括蚀刻鳍24的未被金属层34、40和42所覆盖的部分，并且执行取向附生来生长应激物(stressor，未示出，可以是硅锗或硅碳)。然后，注入该应激物来形成源极/漏极区域48。
图6A还示出了硅化物区域50(可以是亚锗硅化物(germano-silicide)区域)。可以通过均厚沉积金属(诸如，镍、钛、钴及其组合)的薄层来形成硅化物区域50。然后加热晶圆10，这导致硅和锗与其所接触的金属相反应。在反应之后，金属硅化物的层形成在硅(或硅锗)和金属之间。通过使用蚀刻剂来选择性地去除未反应的金属，该蚀刻剂损害金属但不损害硅化物和亚锗硅化物。然后，形成ILD54来覆盖FinFET60，并且将接触塞52形成在ILD54中，从而电连接至FinFET60。
图6B示出了图6A中的FinFET60的截面图，其中，从图6A的6B-6B的平面剖切线得到该截面图。参考图6B，FInFET60的沟槽区域62包括顶部62A和侧壁部分62B。顶部沟道区域62A包括鳍24的顶面部分，而侧壁沟道部分62B包括鳍24的侧壁部分。实际上，沟道部分62A以及源极和漏极区域48形成了第一晶体管60A。第一晶体管60A的栅电极包括层30、34、40和42的位于鳍24上方并且将其覆盖的顶部。沟道部分62B以及源极和漏极区域48形成了第二和第三晶体管60B。第二晶体管60B的栅电极包括层30、40和42的位于鳍24的侧壁上的侧壁部分。可以意识到，第二晶体管60B的栅电极可以不包括金属层34，或可选地包括非常薄的金属层34。
晶体管60A的栅电极的有效功函受到金属层34的功函的影响，该金属层的功函至少部分地决定晶体管60A的阈值电压VthA。换言之，由于金属层34不在鳍24的侧壁上延伸，所以晶体管60B的栅电极的功函不受到金属层34的功函的影响。然而，金属层40对晶体管60B的栅电极的所得到的功函具有很大影响。因此，晶体管60A和60B的栅电极的有效功函彼此可以是不同。晶体管60A的栅电极的有效功函可以高于、等于或低于晶体管60B的栅电极的有效功函。在一些示例性实施例中，晶体管60A和60B的栅电极的有效功函之间的差值可以大于大约0.2eV。
无论FinFET60是n型的或是p型的，由于功函的差别，晶体管60A的阈值电压VthA和晶体管60B的阈值电压VthB可以是彼此不同的，但也可以是彼此相同的。在一些实施例中，阈值电压VthA大于阈值电压VthB。在可选实施例中，阈值电压VthA与VthB之间的差值可以大于大约0.2V，并且可以在大约0.2V和大约1.0V之间。
图1至图6B示出了用于形成FinFET60的先栅极方法。图7至图10示出了根据可选实施例形成FinFET60的中间阶段的截面图，在这些实施例中也可以使用后栅极方法来形成FinFET60。除非另行说明，这些实施例中的部件的材料和形成方法基本上与在图1至图6B中以类似的参考标号表示的类似的部件相同。由此，可以在图1至图6B所示的实施例的论述中得到图7至图10中所示的实施例的形成细节。
这些实施例的初始步骤基本上与图1和图2所示的相同。然后，如图7所示，形成了伪栅极70。在一些实施例中，伪栅极70包括多晶硅，然而也可以使用其他材料。由SiN形成的硬掩模可以形成在伪栅极70上。然后，形成源极/漏极区域48以及源极/漏极硅化物区域50(图7中未示出，请参考图6A)。由于源极/漏极区域48以及源极/漏极硅化物区域50不位于图7的平面中，所以并未示出。源极/漏极区域48以及源极/漏极硅化物区域50可以基本上与图6A中所示的相同。
然后，形成了ILD54，随后进行化学机械抛光(CMP)。在CMP中，硬掩模72被用作为CMP停止层，从而使得ILD54的顶面可以与硬掩模72的顶面齐平。然后，去除硬掩模72和伪栅极70，并且暴露出保护层30。图8中示出了所得到的结构。在后续的步骤中，如图9所示，形成了金属层34、40和42。与图3A和图3B中的实施例类似，金属层34可以位于鳍24上方并且与其对准，并且可以不包括保护层30的侧壁部分上的侧壁部分。然而，金属层40包括位于金属层34上方并且与其对准的部分，以及延伸到保护层30的侧壁的部分。然后形成金属层42来填充伪栅极70所留下的剩余空间。然后，执行CMP来去除金属层40和42的过量部分，从而使金属层40和42的顶面与ILD54的顶面相齐平。由此，金属层34、40和42以及保护层30形成了所得到的FinFET60的栅电极。图10中示出了所得到的FinFET60。在后续的步骤中，在ILD54上方形成了额外的ILD(未示出)，并且可以形成用于穿过额外的ILD和ILD54，并且用于与FinFET60的源极/漏极区域以及栅电极电连接的接触塞。
在图7至图10所示的实施例中，使用后栅极方法形成FinFET60的栅极。然而，栅极介电层28形成在替换该栅极之前。因此，该相应的方法有时被称为后栅极先电介质方法，或如果栅极介电层28由高k电介质材料形成的话，被称为后栅极先HK方法。在可选实施例中，可以使用后栅极后电介质方法(或后栅极后HK方法)。除了不在形成伪栅极70之前形成栅极介电层28以外，该工艺步骤与图7至图10所示的步骤类似。然而，栅极介电层28形成在去除伪栅极70(见图8所示步骤)之后，并且形成在如图9所示的保护层30形成之前。因此，所得到的栅极介电层28也在STI区域22的顶面上延伸，并且在ILD54的侧壁上延伸。
在通过形成顶部晶体管60A(图6B和图10)来具有与侧壁晶体管60B不同的阈值电压的实施例中，可以通过调整FinFET60的栅极电压来调整所得到的FinFET60的饱和电流。例如，假设顶部晶体管60A的阈值电压VthA大于侧壁晶体管60B的阈值电压VthB，如果栅极电压Vg小于阈值电压VthB，那么晶体管60A和60B都没有导通，并且整个FinFET60都是截止的。如果栅极电压Vg大于阈值电压VthB并且小于阈值电压VthA，那么侧壁晶体管60B导通，而顶部晶体管60A截止。FinFET60的饱和电流(下文中被称为饱和电流Isat1)接近侧壁晶体管60B的总饱和电流。然而，如果栅极电压Vg大于阈值电压VthA，那么晶体管60A和60B均导通。FinFET60的饱和电流Isat2由此接近顶部晶体管60A和侧壁晶体管60B的总饱和电流，该饱和电流Isat2大于饱和电流Isat1。
根据实施例，一种器件包括：衬底、位于衬底上的半导体鳍以及位于半导体鳍的顶面和侧壁上的栅极介电层。栅极介电层将栅电极与半导体鳍分隔开。栅电极包括位于半导体鳍上方并且与其对准的顶部，以及位于介电层的侧壁部分上的侧壁部分。栅电极的顶部具有第一功函，栅电极的侧壁部分具有与第一功函不同的第二功函。
根据其他实施例，一种器件包括：衬底，以及位于该衬底上方的半导体鳍，其中，半导体鳍是FinFET的一部分。栅极介电层设置在半导体鳍的顶面和侧壁上。栅极介电层将栅电极与半导体鳍间隔开。栅电极包括位于半导体鳍上方并且与其对准的第一金属层，其中，该第一金属层不包括低于半导体鳍的顶面的大部分。该栅电极还包括：第二金属层，该第二金属层包括位于第一金属层上方并且与其对准的第一部分，以及低于该半导体鳍的顶面的第二部分。第一金属层和第二金属层包括不同的材料。第一金属层和第二金属层的第一部分形成了FinFET的栅电极的顶部，第二金属层的第二部分形成了FinFET的栅电极的侧壁部分。
根据另外其他实施例，一种方法包括：在半导体鳍上形成栅极电介质，其中，该栅极电介质包括位于半导体鳍的顶面上方的顶部，以及位于半导体鳍的侧壁上的侧壁部分。第一金属层形成在栅极电介质的第一部分上方，其中，第一金属层不包括在栅极电介质的侧壁部分上延伸的部分。形成第二金属层，其中，第二金属层包括位于第一金属层上方的第一部分，以及在栅极介电层的侧壁部分上延伸的第二部分。该第一和第二金属层包含不同的材料。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (19)

1.一种具有多阈值电压的鳍式场效应晶体管，包括：
衬底；
半导体鳍，位于所述衬底上方；
栅极介电层，位于所述半导体鳍的顶面和侧壁上；以及
栅电极，通过所述栅极介电层与所述半导体鳍间隔开，其中，所述栅电极包括位于所述半导体鳍上方并且与所述半导体鳍对准的顶部以及位于所述介电层的侧壁部分上的侧壁部分，并且其中，所述栅电极的顶部具有第一功函，并且所述栅电极的侧壁部分具有与所述第一功函不同的第二功函，所述栅电极包括：
第一金属层，位于所述半导体鳍上方并且与所述半导体鳍对准，其中，所述第一金属层不延伸到所述半导体鳍的侧面；以及
第二金属层，包括位于所述半导体鳍上方并且与所述半导体鳍对准的第一部分以及在所述半导体鳍的侧面上延伸的第二部分，其中，所述第一金属层和所述第二金属层包含不同的材料。
2.根据权利要求1所述的具有多阈值电压的鳍式场效应晶体管，其中，所述第一功函高于所述第二功函。
3.根据权利要求1所述的具有多阈值电压的鳍式场效应晶体管，其中，所述第一功函低于所述第二功函。
4.根据权利要求1所述的具有多阈值电压的鳍式场效应晶体管，还包括：保护层，位于所述介电层上方并且位于所述第一金属层和所述第二金属层下方，其中，所述第一金属层和所述第二金属层均接触所述保护层。
5.根据权利要求4所述的具有多阈值电压的鳍式场效应晶体管，其中，所述保护层包含氮化钛。
6.根据权利要求1所述的具有多阈值电压的鳍式场效应晶体管，其中，所述第一功函和所述第二功函具有大于0.2eV的差值。
7.一种具有多阈值电压的鳍式场效应晶体管，包括：
衬底；
半导体鳍，位于所述衬底上方，其中，所述半导体鳍是所述鳍式场效应晶体管的一部分；
栅极介电层，位于所述半导体鳍的顶面和侧壁上；以及
栅电极，通过所述栅极介电层与所述半导体鳍间隔开，其中，所述栅电极包括：
第一金属层，位于所述半导体鳍上方并且与所述半导体鳍对准，其中，所述第一金属层基本上不包括低于所述半导体鳍的顶面的部分；以及
第二金属层，包括位于所述第一金属层上方并且与所述第一金属层对准的第一部分以及低于所述半导体鳍的顶面的第二部分，其中，所述第一金属层和所述第二金属层包含不同的材料，并且其中，所述第一金属层和所述第二金属层的所述第一部分形成所述鳍式场效应晶体管的栅电极的顶部，所述第二金属层的所述第二部分形成所述鳍式场效应晶体管的所述栅电极的侧壁部分。
8.根据权利要求7所述的具有多阈值电压的鳍式场效应晶体管，其中，所述第一金属层具有第一功函，所述第二金属层具有第二功函，并且其中，所述第一功函大于所述第二功函。
9.根据权利要求7所述的具有多阈值电压的鳍式场效应晶体管，其中，所述第一金属层具有第一功函，所述第二金属层具有第二功函，并且其中，所述第一功函小于所述第二功函。
10.根据权利要求7所述的具有多阈值电压的鳍式场效应晶体管，还包括：保护层，位于所述介电层上方并且位于所述第一金属层和所述第二金属层下方，其中，所述第一金属层和所述第二金属层均接触所述保护层。
11.根据权利要求10所述的具有多阈值电压的鳍式场效应晶体管，其中，所述保护层包含氮化钛。
12.一种制造具有多阈值电压的鳍式场效应晶体管的方法，包括：
在半导体鳍上形成栅极电介质，其中，所述栅极电介质包括位于所述半导体鳍的顶面上方的顶部以及位于所述半导体鳍的侧壁上的侧壁部分；
在所述栅极电介质的顶部上方形成第一金属层，其中，所述第一金属层不包括在所述栅极电介质的所述侧壁部分上延伸的部分；以及
形成第二金属层，其中，所述第二金属层包括位于所述第一金属层上方的第一部分以及在所述栅极电介质的侧壁部分上延伸的第二部分，并且其中，所述第一金属层和所述第二金属层包含不同的材料。
13.根据权利要求12所述的方法，其中，使用非共形沉积方法执行形成所述第一金属层的步骤。
14.根据权利要求13所述的方法，其中，使用共形沉积方法形成所述第二金属层。
15.根据权利要求12所述的方法，其中，形成所述第一金属层的步骤包括：沉积所述第一金属层，并且执行蚀刻步骤来去除位于所述栅极电介质的侧壁部分上的所述第一金属层的部分。
16.根据权利要求12所述的方法，其中，所述第一金属层和所述第二金属层的所述第一部分形成栅电极的顶部，所述第二金属层的所述第二部分形成所述栅电极的第二部分，并且其中，所述栅电极的顶部和所述栅电极的所述第二部分具有不同的功函。
17.根据权利要求12所述的方法，还包括：在形成所述栅极电介质的步骤之后并且在形成所述第一金属层的步骤之前，在所述栅极电介质上方形成保护层，其中，所述第一金属层和所述第二金属层均与所述保护层相接触。
18.根据权利要求17所述的方法，还包括：
在所述保护层上方形成伪栅极；以及
去除所述伪栅极，其中，在去除所述伪栅极的步骤之后暴露出所述保护层，并且其中，在去除所述伪栅极的步骤之后执行形成所述第一金属层和所述第二金属层的步骤。
19.根据权利要求12所述的方法，其中，所述第一金属层和所述第二金属层具有大于0.1eV的功函差。
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