CN103854965B - 平坦化处理方法 - Google Patents

平坦化处理方法 Download PDF

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CN103854965B
CN103854965B CN201210505359.5A CN201210505359A CN103854965B CN 103854965 B CN103854965 B CN 103854965B CN 201210505359 A CN201210505359 A CN 201210505359A CN 103854965 B CN103854965 B CN 103854965B
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layer
fin
sacrificial gate
material layer
region
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CN103854965A (zh
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朱慧珑
罗军
李春龙
邓坚
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210505359.5A priority Critical patent/CN103854965B/zh
Priority to PCT/CN2012/087003 priority patent/WO2014082356A1/zh
Publication of CN103854965A publication Critical patent/CN103854965A/zh
Priority to US14/722,597 priority patent/US10068803B2/en
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Abstract

本申请公开了一种平坦化处理方法。一示例方法可以包括：在材料层中对于溅射的负载条件较高的区域中形成沟槽；以及对材料层进行溅射，以使材料层平坦。

Description

平坦化处理方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种平坦化处理方法。
背景技术
在半导体工艺中，经常用到平坦化工艺，例如化学机械抛光(CMP)，以获得相对平坦的表面。然而，在通过CMP对材料层进行平坦化的情况下，如果需要研磨掉相对较厚的部分，则难以控制CMP后材料层的表面平坦度，例如控制到几个纳米之内。
另一方面，如果要对覆盖特征、特别是非均匀分布特征的材料层进行平坦化，那么材料层由于特征的存在而可能出现非均匀分布的凹凸起伏，因此可能导致平坦化不能一致地执行。
发明内容
本公开的目的至少部分地在于提供一种平坦化处理方法。
根据本公开的一个方面，提供了一种对衬底上形成的材料层进行平坦化的方法，包括：在材料层中对于溅射的负载条件较高的区域中形成沟槽；以及对材料层进行溅射，以使材料层平坦。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-17示出了制造半导体器件的示例流程，其中利用了根据本公开实施例的平坦化处理方法。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的示例，可以通过溅射(sputtering)，例如Ar或N等离子体溅射，来对材料层进行平坦化处理。通过这种溅射平坦化处理，而非常规的CMP平坦化处理，可以实现更加平坦的材料层表面。这种材料层可以包括半导体制造工艺中使用的多种材料层，例如，包括但不限于绝缘体材料层、半导体材料层和导电材料层。
另外，在进行溅射时，可能存在负载效应(loading effect)。所谓“负载相应”，是指溅射所针对的材料层上存在的图案以及图案的密度(或者说，材料层的形貌)等将会影响溅射后材料层的厚度和/或形貌等。因此，为了获得较为平坦的表面，优选地在溅射时考虑负载效应。
例如，如果材料层由于之下存在(凸出的)特征而存在凸起，那么相对于其他没有凸起的部分而言，存在凸起的部分需要经受“更多”的溅射，才能与其他部分保持平坦。在此，所谓“更多”的溅射，例如是指在相同的溅射参数(如，溅射功率和/或气压)情况下，需要进行更长时间的溅射；或者，在相同溅射时间的情况下，溅射强度的更大(如，溅射功率和/或气压更大)；等等。也就是说，对于溅射而言，这种凸起对应的负载条件(loadingcondition)更大。
另一方面，如果材料层由于之下存在(凹入的)特征而存在凹陷，那么相对于其他没有凹陷的部分而言，存在凹陷的部分需要经受“更少”的溅射，才能与其他部分保持平坦。也就是说，对于溅射而言，这种凹陷对应的负载条件更小。
另外，如果存在多个非均匀分布的特征，那么材料层可能由于特征而具有非均匀分布的凸起和/或凹陷，因此导致负载条件在衬底上发生变化。例如，对于凸起而言，其分布密度较高区域的负载条件要高于分布密度较低区域的负载条件；而对于凹陷而言，其分布密度较高区域的负载条件要低于分布密度较低区域的负载条件。非均匀分布的负载条件可能不利于溅射均匀地进行。
根据本公开的示例，在通过溅射对材料层进行平坦化的处理中，可以结合光刻，以便能够实现选择性平坦化。例如，在进行溅射之前，可以在材料层中负载条件较高的区域(例如，凸起)中形成沟槽，以降低其负载条件，从而整个材料层上负载条件的分布均匀性可以得到改善。这样，之后的溅射可以在衬底上大致均匀地进行，从而有助于获得平坦的表面。
另外，如果衬底上形成有非均匀分布的多个特征(从而导致材料层存在例如多个非均匀分布的凸起)，那么在特征分布较密的区域(凸起分布较密的区域，即负载条件较高的区域)形成的沟槽数可以多于特征分布较疏的区域(凸起分布较疏的区域，即负载条件较较低的区域)形成的沟槽数。这样，可以使得这两种区域上的负载条件更加接近，即负载条件的均匀性改善。根据一示例，特征分布较疏的区域形成的沟槽数甚至可以为零。
上述特征可以包括能够在衬底上形成的各种特征，例如，包括但不限于衬底上的凸出特征如栅、鳍等，和/或衬底上的凹入特征如替代栅工艺中去除牺牲栅而形成的栅槽等。
上述沟槽例如可以通过掩模，对材料层进行构图而实现。由于材料层上负载条件的分布与之下的特征相关，因此这种掩模可以根据用来形成特征的掩模进行设计。根据一示例，可以利用与用来形成特征的掩模相同或相反的掩模，通过正性或者负性光刻胶，来形成与特征的图案相同或互补的沟槽图案。
本公开可以各种形式呈现，以下将描述其应用于鳍式场效应晶体管(FinFET)的一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
可以对衬底1000进行构图，以形成鳍。例如，这可以如下进行。具体地，在衬底1000上按设计形成构图的光刻胶(未示出)，然后以构图的光刻胶为掩模，刻蚀例如反应离子刻蚀(RIE)衬底1000，从而形成鳍1002。之后，可以去除光刻胶。在图1所示的示例中，根据设计需要，鳍1002在区域100-1中的分布密度较高，而在区域100-2中的分布密度较低。
这里需要指出的是，通过刻蚀所形成的(鳍之间的)沟槽的形状不一定是图1中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥台形。另外，所形成的鳍的位置和数目不限于图1所示的示例。
另外，鳍不限于通过直接对衬底进行构图来形成。例如，可以在衬底上外延生长另外的半导体层，对该另外的半导体层进行构图来形成鳍。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性，则在对鳍进行构图时，可以使构图基本上停止于衬底，从而实现对鳍高度的较精确控制。
在通过上述处理形成鳍之后，可以在衬底上形成隔离层。
具体地，如图1所示，可以在衬底上例如通过淀积形成电介质层1004，以覆盖形成的鳍1002。例如，电介质层1004可以包括氧化物(如，氧化硅)。由于鳍1002的存在，电介质层1004上存在凸起B。相应地，凸起B在区域100-1中的分布密度较高，而在区域100-2中的分布密度较低。为此，需要对电介质层1004进行平坦化。根据本公开的优选实施例，通过溅射来进行平坦化处理。
为了使得溅射能够在衬底上均匀地进行，首先可以对电介质层1004进行构图。具体地，如图2所示，可以在电介质层1004上涂覆光刻胶1006，并通过掩模进行曝光、显影等操作对光刻胶1006进行构图。在对光刻胶1006进行构图时考虑随后进行的溅射的负载条件。具体地，在图2所示的示例中，将光刻胶1006构图为在区域100-1中的凸起之上具有开口，而在区域100-2中没有开口。例如，可以根据用来形成鳍1002的掩模(确定鳍1002的位置和形状等，并因此部分地确定电介质层1004的起伏特性)，来设计用来对光刻胶1006进行曝光的掩模。
随后，如图3所示，利用构图的光刻胶1006为掩模，对电介质层1004进行构图，例如反应离子刻蚀(RIE)，以在其中形成沟槽G。
在此，可以控制对电介质层1004的构图，使得大致停止于电介质层1004的最低顶面附近，例如最低顶面的上下约50nm之间的范围处。电介质层1004的最低顶面例如可以根据淀积的电介质层1004的厚度确定。另外，可以根据RIE的刻蚀速度等工艺参数，来确定对电介质层1004构图的停止点。之后，可以去除光刻胶1006。
这样，区域100-1上的负载条件得以降低，并因此可以接近或者甚至等于区域100-2上的负载条件，这有利于随后的溅射均匀地进行。
这里需要指出的是，尽管在图3的示例中，仅在区域100-1中的凸起上形成了沟槽G，但是本公开不限于此。例如，在区域100-2中的凸起上同样也可以形成沟槽G，只要能够降低两个区域之间负载条件的非均匀性。
接下来，如图4所示，可以对电介质层1004进行溅射，来对电介质层1004进行平坦化处理。溅射可以使用等离子体，如Ar或N等离子体。在此，例如可以根据等离子体溅射对电介质层1004的切削速度，控制溅射参数例如溅射功率和气压等，来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段，充分平滑电介质层1004的表面。由于如上所述，由于沟槽G衬底上负载条件的均匀性得以改善，因此溅射可以大致均匀地执行，并因此可以实现更加平坦的表面。
图5示出了通过溅射进行平坦化之后的结果。尽管在图5中示出了微观上的起伏，但是事实上电介质层1004的顶面具有充分的平坦度，其起伏可以控制在例如几个纳米之内。在图5所示的示例中，等离子体溅射可以在到达鳍1002的顶面之前结束，以避免对鳍1002造成过多的损伤。根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的电介质层1004进行少许CMP。
在电介质层1004的表面通过等离子体溅射而变得充分平滑之后，如图6所示，可以对电介质层1004进行回蚀(例如，RIE)，以露出鳍1002的一部分，该露出的部分随后可以用作最终器件的真正鳍。剩余的电介质层1004构成隔离层。由于回蚀之前电介质层1004的表面通过溅射而变得平滑，所以回蚀之后隔离层1004的表面在衬底上基本上保持一致。
为改善器件性能，根据本公开的一示例，还可以如图6中的箭头所示，通过注入来形成穿通阻挡部(参见图7所示的1008)。例如，对于n型器件而言，可以注入p型杂质，如B、BF2或In；对于p型器件，可以注入n型杂质，如As或P。离子注入可以垂直于衬底表面。控制离子注入的参数，使得穿通阻挡部形成于鳍位于隔离层1004表面之下的部分中，并且具有期望的掺杂浓度。应当注意，由于鳍的形状因子，一部分掺杂剂(离子或元素)可能从鳍的露出部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火，以激活注入的杂质。这种穿通阻挡部有助于减小源漏泄漏。
随后，可以在隔离层1004上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图7所示，例如通过淀积，形成栅介质层1010。例如，栅介质层1010可以包括氧化物，厚度为约0.8-1.5nm。在图7所示的示例中，仅示出了“∏”形的栅介质层1010。但是，栅介质层1010也可以包括在隔离层1004的顶面上延伸的部分。然后，例如通过淀积，形成栅导体层1012。例如，栅导体层1012可以包括多晶硅，厚度为约30-200nm。栅导体层1012可以填充鳍之间的间隙。由于鳍的存在，栅导体层1012上也存在凸起。相应地，凸起在区域100-1中的分布密度较高，而在区域100-2中的分布密度较低。
在此，同样可以利用根据本公开的技术来对栅导体层1012进行平坦化。具体地，如图8所示，在栅导体层1012上形成构图的光刻胶1014。该光刻胶1014例如可以与上述光刻胶1006类似地构图(参见以上结合图2的说明)，从而在区域100-1中的凸起之上具有开口，而在区域100-2中没有开口。
随后，如图9所示，利用构图的光刻胶1014为掩模，对栅导体层1012进行构图，例如RIE，以在其中形成沟槽G。在此，可以控制对栅导体层1012的构图，使得大致停止于栅导体层1012的最低顶面附近，例如最低顶面的上下约50nm之间的范围处。栅导体层1012的最低顶面例如可以根据淀积的栅导体层1012的厚度确定。另外，可以根据RIE的刻蚀速度等工艺参数，来确定对栅导体层1012构图的停止点。之后，可以去除光刻胶1014。
如图9所示，在区域100-1，凸起由于沟槽G而被去除了一部分，从而该区域中的负载条件降低，并因此可以接近乃至大致等于区域100-2中的负载条件，这有利于随后的溅射均匀地进行。
这里需要指出的是，尽管在图9的示例中，仅在区域100-1中的凸起上形成了沟槽G，但是本公开不限于此。例如，在区域100-2中的凸起上同样也可以形成沟槽G，只要能够降低两个区域之间负载条件的非均匀性。
接下来，如图10所示，可以对栅导体层1012进行溅射，来对栅导体层1012进行平坦化处理。同样，溅射可以使用等离子体，如Ar或N等离子体。在此，例如可以根据等离子体溅射对栅导体层1012的切削速度，控制溅射参数例如溅射功率和气压等，来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段，充分平滑栅导体层1012的表面。由于如上所述，由于沟槽G衬底上负载条件的均匀性得以改善，因此溅射可以大致均匀地执行，并因此可以实现更加平坦的表面。
图11示出了通过溅射进行平坦化之后的结果。尽管在图11中示出了微观上的起伏，但是事实上栅导体层1012的顶面具有充分的平坦度，其起伏可以控制在例如几个纳米之内。根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的栅导体层1012进行少许CMP。
之后，如图12(图12是顶视图，以上图1-11是沿AA′线的截面图)所示，对栅导体层1012进行构图，以形成栅堆叠。在图12的示例中，栅导体层1012被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1012为掩模，进一步对栅介质层1010进行构图。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图13(图13(b)示出了沿图13(a)中BB′线的截面图)所示，可以在栅导体层1012的侧壁上形成侧墙1014。例如，可以通过淀积形成厚度约为5-20nm的氮化物(如，氮化硅)，然后对氮化物进行RIE，来形成侧墙1014。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，侧墙1014基本上不会形成于鳍的侧壁上。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区，得到FinFET。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。另外，还可以应用应变源/漏技术。
根据本公开的另一实施例，在图7中形成的栅介质层1010和栅导体层1012为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图8-13描述的方法来处理。
然后，如图14所示，首先选择性去除(例如，RIE)暴露在外的牺牲栅介质层1010。在牺牲栅介质层1010和隔离层1004均包括氧化物的情况下，由于牺牲栅介质层1010较薄，因此对牺牲栅介质层1010的RIE基本上不会影响隔离层1004。在以上形成牺牲栅堆叠的过程中，以牺牲栅导体为掩模进一步构图牺牲栅介质层的情况下，不再需要该操作。
然后，可以选择性去除(例如，RIE)由于牺牲栅介质层1010的去除而露出的鳍1002的部分。对鳍1002该部分的刻蚀可以进行至露出穿通阻挡部1008。由于牺牲栅堆叠(牺牲栅介质层、牺牲栅导体和侧墙)的存在，鳍1002可以留于牺牲栅堆叠下方。
接下来，如图15所示，例如可以通过外延，在露出的鳍部分上形成半导体层1016。随后可以在该半导体层1016中形成源/漏区。根据本公开的一实施例，可以在生长半导体层1016的同时，对其进行原位掺杂。例如，对于n型器件，可以进行n型原位掺杂；而对于p型器件，可以进行p型原位掺杂。另外，为了进一步提升性能，半导体层1016可以包括不同于鳍1002的材料，以便能够向鳍1002(其中将形成器件的沟道)施加应力。例如，在鳍1002包括Si的情况下，对于n型器件，半导体层1016可以包括Si:C(C的原子百分比例如为约0.2-2％)，以施加拉应力；对于p型器件，半导体层1016可以包括SiGe(例如，Ge的原子百分比为约15-75％)，以施加压应力。
在牺牲栅导体层1012包括多晶硅的情况下，半导体层1016的生长可能也会发生在牺牲栅导体层1012的顶面上。这在附图中并未示出。
接下来，如图16所示，例如通过淀积，形成另一电介质层1018。该电介质层1018例如可以包括氧化物。随后，对该电介质层1018进行平坦化处理例如CMP。该CMP可以停止于侧墙1014，从而露出牺牲栅导体1012。
随后，如图17所示，例如通过TMAH溶液，选择性去除牺牲栅导体1012，从而在侧墙1014内侧形成了空隙。根据另一示例，还可以进一步去除牺牲栅介质层1010。然后，通过在空隙中形成栅介质层1020和栅导体层1022，形成最终的栅堆叠。栅介质层1020可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1022可以包括金属栅导体。优选地，在栅介质层1020和栅导体层1022之间还可以形成功函数调节层(未示出)。
这里需要指出的是，尽管在上述实施例中描述了本公开的技术应用于FinFET的制造，但是本公开不限于此。本公开的技术可以适用于各种需要进行平坦化处理的应用中。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (12)

1.一种对衬底上形成的材料层进行平坦化的方法，包括：
在材料层中对于溅射的负载条件较高的区域中形成沟槽；以及
对材料层进行溅射，以使材料层平坦，
其中，所述衬底上形成有多个特征，并且特征分布较密的区域形成的沟槽数多于特征分布较疏的区域形成的沟槽数，所述材料层形成于衬底上覆盖所述特征，所述材料层中由于之下的特征而存在的凸起部分对应于所述负载条件较高的区域，并且所述特征包括鳍，所述材料层包括电介质。
2.根据权利要求1所述的方法，其中，特征分布较疏的区域形成的沟槽数为零。
3.根据权利要求2所述的方法，其中，根据用来形成所述特征的掩模，来设计用来形成沟槽的掩模。
4.根据权利要求1所述的方法，其中，利用Ar或N等离子体进行溅射。
5.根据权利要求1所述的方法，其中，在溅射之后，该方法还包括：
进一步回蚀材料层，以露出鳍。
6.根据权利要求5所述的方法，其中，在进一步回蚀之后，该方法还包括：进行离子注入，以在鳍位于进一步回蚀后的材料层的表面下方的部分中形成穿通阻挡层。
7.根据权利要求6所述的方法，其中，在离子注入之后，该方法还包括：
在材料层上形成横跨鳍的牺牲栅堆叠；
以牺牲栅堆叠为掩模，选择性刻蚀鳍，直至露出穿通阻挡层；
在鳍的露出部分上形成半导体层，用以形成源/漏区；以及
形成栅堆叠替代牺牲栅堆叠。
8.根据权利要求1所述的方法，其中，所述材料层包括栅导体层，所述栅导体层介由栅介质层覆盖鳍。
9.根据权利要求7所述的方法，其中，
形成牺牲栅堆叠包括：
在材料层上形成牺牲栅介质层；
在牺牲栅介质层上形成牺牲栅导体层；
对牺牲栅导体层进行平坦化，并构图；以及
在构图后的牺牲栅导体的侧壁上形成侧墙，
其中，对牺牲栅导体层进行平坦化包括：
在牺牲栅导体层中对于溅射的负载条件较高的区域中形成沟槽；以及
对牺牲栅导体层进行溅射，以使牺牲栅导体层平坦。
10.根据权利要求9所述的方法，其中，牺牲栅导体层中由于之下的鳍而存在的凸起部分对应于负载条件较高的区域。
11.根据权利要求10所述的方法，其中，所述衬底上形成有非均匀分布的多个鳍，并且鳍分布较密的区域在牺牲栅导体层中形成的沟槽数多于鳍分布较疏的区域在牺牲栅导体层中形成的沟槽数。
12.根据权利要求11所述的方法，其中，鳍分布较疏的区域在牺牲栅导体层中形成的沟槽数为零。
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