CN114649260A - 三维半导体结构的制作方法及三维半导体结构 - Google Patents

三维半导体结构的制作方法及三维半导体结构 Download PDF

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CN114649260A
CN114649260A CN202011505918.3A CN202011505918A CN114649260A CN 114649260 A CN114649260 A CN 114649260A CN 202011505918 A CN202011505918 A CN 202011505918A CN 114649260 A CN114649260 A CN 114649260A
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epitaxial
epitaxial layer
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陈中怡
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Futaihua Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hon Hai Precision Industry Co Ltd
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Abstract

一种三维半导体结构的制作方法，其包括在衬板上形成第一绝缘层，且第一绝缘层上开设至少一通道孔，每一通道孔贯穿第一绝缘层且暴露出衬板；在每一通道孔内的依次层叠生成第一外延层与第二外延层，其中所述第一外延层为不均匀掺杂层以形成较低阻值的源极区或漏极区；在第一绝缘层上形成交替层叠设置的第二绝缘层与牺牲层；以及在第二外延层上逐步生成交替层叠设置的多个第一外延层与多个第二外延层；本发明还提供一种由该三维半导体结构制作方法制作的三维半导体结构。

Description

三维半导体结构的制作方法及三维半导体结构
技术领域
本发明涉及一种三维半导体结构的制作方法以及应用该制作方法制得的三维半导体结构。
背景技术
近年来，为满足客户对高性能与低制造成本的微电子的需求，半导体器件需要高度集成。典型的二维或平面半导体结构的集成度主要由单位存储单元占据的面积决定，所述集成度受形成精细图案的技术水平的影响。然而，提高图案精细度需要的极其昂贵的工艺设备，如此，成本的提高限制二维或平面半导体结构的高集成度的发展。因此，三维半导体结构应运而生。相较于二维半导体结构，三维半导体结构的性能与集成度更优。
一个三维半导体结构一般包括层叠设置的多个堆叠层，所述多个堆叠层可包括多个三维垂直型晶体管。在现有的三维半导体结构中，刻蚀多个堆叠层形成通道孔，在通道孔内形成半导体材料以形成三维垂直型晶体管的漏极区与源极区。然，刻蚀多个堆叠组上形成的通道孔比较细长，较难保持直立与对正而出现歪斜与偏移，使得晶体管的漏极区、源极区与栅极区相关结构均容易不对称或偏移。由于一般三维半导体结构的源极区与漏极区的阻值较高而难以离子注入的方式形成，且当三维半导体结构包括层叠设置的多个堆叠层时，源极区与漏极区较高的串联阻值容易影响晶体管的工作电流与响应速度。
发明内容
鉴于此，有必要提供一种三维半导体结构的制作方法，其包括：
提供一衬板，在所述衬板上沉积第一绝缘层，在所述第一绝缘层上开设至少一通道孔，每一通道孔贯穿所述第一绝缘层且暴露出所述衬板；
在每一通道孔内依次层叠生成不均匀掺杂的第一外延层与第二外延层，所述第一外延层用于形成源极区或漏极区；
在所述第一绝缘层上形成牺牲层且使所述第二外延层相对所述牺牲层露出，在所述第二外延层上层叠生成又一第一外延层；在所述牺牲层上形成第二绝缘层且使该又一第一外延层相对所述第二绝缘层暴露，在该又一第一外延层上层叠生成又一第二外延层；
参照上一步骤，在所述第二绝缘层上依次交替地形成层叠设置的多个牺牲层与多个第二绝缘层，以及在所述又一第二外延层上依次交替地生成层叠设置的多个第一外延层与多个第二外延层。
本发明还提供一种三维半导体结构，所述三维半导体结构有所述三维半导体结构制作方法制得。
相对于现有技术，在该三维半导体结构的制作方法中，不需要开设贯穿所述第一绝缘层与所述多个第二绝缘层的通道孔且不需要在此通道孔内形成多个第一外延层与多个第二外延层；而是只形成贯穿所述第一绝缘层的通道孔且在该通道孔内形成层叠设置的一个第一外延层与一个第二外延层，后续也是直接在第二外延层上直接生长又一第一外延层且在第一外延层上直接生长又一第二外延层，可容易实现多个第一外延层与多个第二外延层的层叠正对，即使随着所述第二绝缘层的层数的增加，由该三维半导体结构的制作方法形成的多个第一外延层与多个第二外延层也能保持层叠正对，使得多个第一外延层与多个第二外延层为直立不歪斜的结构。在所述三维半导体结构中，所述第一外延层可作为源极区或漏极极区，形成不均匀掺杂的所述第一外延层有利于降低漏极区或漏极区的电阻值，且包括多个堆叠层的三维半导体结构能够维持较低源极区与漏极区的串联阻值，从而有利于增加晶体管的工作电流与提高晶体管的响应速度。
附图说明
图1为本发明实施例的三维半导体结构的制作方法的流程图。
图2为本发明实施例的三维半导体结构的制作方法中在衬板形成第一绝缘层、以及在第一绝缘层上开设通道孔的示意图。
图3为本发明实施例的三维半导体结构的制作方法中在通道孔内的形成叠层设置的第一外延层与第二外延层的示意图。
图4A为本发明实施例的三维半导体结构的制作方法中在第一绝缘层上形成覆盖第二外延层的牺牲层的示意图。
图4B为本发明实施例的三维半导体结构的制作方法中平坦化牺牲层的示意图。
图4C为本发明实施例的三维半导体结构的制作方法中在所述第二外延层上生长又一第一外延层的示意图。
图4D为本发明实施例的三维半导体结构的制作方法中在牺牲层上形成覆盖又一第一外延层的第二绝缘层的示意图。
图4E为本发明实施例的三维半导体结构的制作方法中平坦化第二绝缘层的示意图。
图4F为本发明实施例的三维半导体结构的制作方法中在又一第一外延层上形成又一第二外延层的示意图。
图5为本发明实施例的三维半导体结构的制作方法中形成多个第二绝缘层、多个第一外延层与多个第二外延层的示意图。
图6A为本发明实施例的三维半导体结构的制作方法中形成栅极孔与栅极通道的示意图。
图6B为本发明实施例的三维半导体结构的制作方法中形成介电层的示意图。
图6C为本发明实施例的三维半导体结构的制作方法中形成栅极的示意图。
主要元件符号说明
Figure BDA0002844943330000021
Figure BDA0002844943330000031
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
附图中示出了本发明的实施例，本发明可以通过多种不同形式实现，而并不应解释为仅局限于这里所阐述的实施例。相反，提供这些实施例是为了使本发明更为全面与完整的公开，并使本领域的技术人员更充分地了解本发明的范围。为了清晰可见，在图中，层与区域的尺寸被放大了。
除非另外定义，这里所使用的所有术语(包括技术与科学术语)具有与本发明所述领域的普通技术人员所通常理解的含义相同的含义。还应当理解，比如在通用的辞典中所定义的那些的术语，应解释为具有与它们在相关领域的环境中的含义相一致的含义，而不应以过度理想化或过度正式的含义来解释，除非在本文中明确地定义。
参照图1，本发明实施例提供的三维半导体结构的制作方法包括步骤S1至步骤S4。步骤S1至步骤S4如下所示：
步骤S1：提供一衬板，在所述衬板上沉积第一绝缘层，在所述第一绝缘层上开设至少一通道孔，每一通道孔贯穿所述第一绝缘层且暴露出所述衬板。
步骤S2：在每一通道孔内依次层叠生成不均匀掺杂的第一外延层与第二外延层，所述第一外延层用于形成源极区或漏极区。
步骤S3：在所述第一绝缘层上形成牺牲层且使所述第二外延层相对所述牺牲层露出，在所述第二外延层上层叠生成又一第一外延层；在所述牺牲层上形成第二绝缘层且使所述又一第一外延层相对所述第二绝缘层暴露，在所述又一第一外延层上层叠生成又一第二外延层。
步骤S4：参照上一步骤，在所述第二绝缘层上依次交替地形成层叠设置的多个牺牲层与多个第二绝缘层，以及在所述又一第二外延层上依次交替地生成层叠设置的多个第一外延层与多个第二外延层。
下面结合具体附图说明本发明实施例三维半导体结构的制作方法。
步骤S1请参照图2，在所述衬板10上沉积第一绝缘层11，在所述第一绝缘层11上开设至少一通道孔12，每一通道孔12贯穿所述第一绝缘层11且暴露出所述衬板10。
在本实施例中，通过黄光刻蚀工艺图案化所述第一绝缘层11以形成至少一所述通道孔12。所述刻蚀可以为干刻蚀或湿刻蚀。所述衬板10可以为但不限于单晶硅基板、单晶锗基半或单晶硅锗基板。所述第一绝缘层11为绝缘材料，可以为但不限于SiO2。
步骤S2请参照图3，在每一通道孔12内依次层叠生成第一外延层13与第二外延层14，具体地，利用选择性外延生长工艺在所述通道孔12内露出的衬板10上生长出第一外延层13，该第一外延层13与所述第一绝缘层11基本齐平。再在该第一外延层13上通过选择性外延生长工艺生长形成第二外延层14，且该第一外延层13与该第二外延层14上下层叠正对，形成直立不歪斜的结构。
在本实施例中，所述第一外延层13与所述第二外延层14均由半导体材料构成，所述半导体材料可为硅、锗、硅-锗及铟镓锌氧化物中的一种或几种的组合。所述第一外延层13包括两个轻掺杂的半导体层与一个重掺杂的半导体层以形成不均匀掺杂的半导体材质层，且该重掺杂的半导体层位于两个轻掺杂的半导体层的中间，所述第一外延层用于形成源极区或漏极区。所述第二外延层14为轻掺杂的半导体层，用于形成栅极区下的通道区。所述第一外延层与所述第二外延层二者可互为N型半导体层或P型半导体层，或者为同型半导体层。在本实施例中，一个第二外延层14以及接触设置于该第二外延层14两侧的两个第一外延层13属于同一个晶体管19，具体地，该晶体管19的栅极区包括该第二外延层14，且该晶体管19的源极区或漏极区包括该两个第一外延层13中一个；由于所述第一外延层13与所述第二外延层14上下层叠正对，则晶体管19的源极区与漏极区也能上下层叠正对。
在一实施例中，依次层叠生成一个第一外延层13与一个第二外延层14的步骤包括：依次形成一个不均匀的N型掺杂的半导体材质的所述第一外延层13与形成一个P型或者N型轻掺杂的半导体材质的所述第二外延层14。在此实施例中，形成不均匀的N型掺杂的半导体材质的所述第一外延层13的步骤包括：依次形成层叠设置的N型轻掺杂的半导体材质的第一掺杂层131、N型重掺杂的半导体材质的第二掺杂层132以及N型轻掺杂的半导体材质的第三掺杂层133，如图3所示。在一变更实施例中，形成不均匀的N型掺杂的半导体材质的所述第一外延层13的步骤包括：依次形成层叠设置的P型轻掺杂的半导体材质的第一掺杂层131、N型重掺杂的半导体材质的第二掺杂层132以及P型轻掺杂的半导体材质的第三掺杂层133，所述第二掺杂层132的N型掺杂剂向所述第一掺杂层131与所述第三掺杂层133扩散以形成不均匀的N型掺杂的半导体材质的所述第一外延层13。在上述实施例中，所述第一掺杂层131、所述第三掺杂层133与所述第二外延层14为轻掺杂且半导体掺杂剂可以为但不限于磷、硼或铟，所述第二掺杂层132为重掺杂且半导体掺杂剂可以为但不限于磷、氮或砷。在上述实施例中，一个第二外延层14以及接触设置于该第二外延层14两侧的两个第一外延层13属于同一个N型晶体管191。由此方法形成的不均匀的N掺杂的半导体材质的第一外延层13构成N型晶体管191的源极区或漏极区时，能降低所述N型晶体管191的源极区或漏极区的电阻。
在又一实施例中，依次层叠生成一个第一外延层13与一个第二外延层14的步骤包括：依次形成一个不均匀的P型掺杂的半导体材质的所述第一外延层13与形成一个N型或者P型轻掺杂的半导体材质的所述第二外延层14。在此实施例中，形成不均匀的P型掺杂的半导体材质的所述第一外延层13的步骤包括：依次形成层叠设置的P型轻掺杂的半导体材质的第一掺杂层131、P型重掺杂的半导体材质的第二掺杂层132以及P型轻掺杂的半导体材质的第三掺杂层133，如图3所示。在一变更实施例中，形成不均匀的P型掺杂的半导体材质的所述第一外延层13的步骤包括：依次形成层叠设置的N型轻掺杂的半导体材质的第一掺杂层131、P型重掺杂的半导体材质的第二掺杂层132以及N型轻掺杂的半导体材质的第三掺杂层133，所述第二掺杂层132的P型掺杂剂向所述第一掺杂层131与所述第三掺杂层133扩散以形成P型掺杂的半导体材质的所述第一外延层13。在上述实施例中，所述第一掺杂层131、所述第三掺杂层133与所述第二外延层14为轻掺杂且半导体掺杂剂可以为但不限于磷、氮或砷，所述第二掺杂层132为重掺杂且半导体掺杂剂可以为但不限于磷、硼或铟。在上述实施例中，一个第二外延层14以及接触设置于该第二外延层14两侧的两个第一外延层13属于同一个P型晶体管192。由此方法形成不均匀的P型掺杂的半导体材质的第一外延层13构成P型晶体管192的源极区或漏极区时，能降低所述P型晶体管192的源极区或漏极区的电阻。
步骤S3请参照图4A至4F。
如图4A与图4B所示，在所述第一绝缘层11上形成一个牺牲层15的步骤包括：在所述第一绝缘层11上沉积覆盖所述第二外延层14的该牺牲层15；平坦化该牺牲层15使该第二外延层相对该牺牲层15露出。
如图4C所示，在所述第二外延层14上层叠生成又一第一外延层13。在本实施例中，在相对所述牺牲层15暴露的第二外延层14上通过选择性外延生长工艺生成该又一第一外延层13，该第二外延层14与该又一第一外延层13上下层叠正对。
如图4D与图4E所示,在一个牺牲层15上形成一个第二绝缘层16的步骤包括：在该牺牲层15上沉积覆盖所述又一第一外延层13的该第二绝缘层16并平坦化该第二绝缘层16使所述第一外延层13相对该第二绝缘层16露出。
如图4F所示，在所述又一第一外延层13上通过选择性外延生长工艺生成又一第二外延层，所述层叠生成又一第二外延层。该又第一外延层13与该又一第二外延层14上下层叠正对，且均与步骤S1中形成的第一外延层13与第二外延层14上下层叠正对。
在本实施例中，采用化学机械抛光(Chemical Mechanical Polishing，CMP)平坦化所述第二绝缘层16与所述牺牲层15。在一实施例中，如果所述第二绝缘层16与所述牺牲层15采用区域选择性沉积(Area selective deposition,ASD)工艺形成，则可以省略CMP平坦化步骤。
步骤S4请参照图5。完成步骤S1与S2以及循环步骤S3，在由步骤S3形成的第二绝缘层16上沉积又一牺牲层15，平坦化该又一牺牲层15使由步骤S3形成的又一第二外延层14相对该又一牺牲层15暴露，在该又一第二外延层14上通过选择性外延生长工艺生长又一第一外延层13且该又一第一外延层13与该又一第二外延层14上下层叠正对。如此循环，形成位于所述衬板10上的所述第一绝缘层11、交替层叠设置的所述多个第二绝缘层16与所述多个牺牲层15、以及交替层叠设置的所述多个第一外延层13与所述多个第二外延层14；所述多个第一外延层13与所述第二外延层14贯穿所述第一绝缘层11、所述多个第二绝缘层16以及所述多个牺牲层15。
在一实施例中，位于不同层且层叠设置的所述多个第一外延层13与所述多个第二外延层14可形成层叠设置的多个P型晶体管192和/或层叠设置的多个N型晶体管191。具体地，多个N型晶体管191形成第一层叠区，多个P型晶体管192形成第二层叠区，所述第一层叠区与所述第二层叠区之间以一绝缘层间隔开。
本发明实施例的三维半导体结构的制作方法还包括：在完成步骤S4之后，在所述多个第二绝缘层16与所述多个牺牲层15中开设栅极孔17，所述栅极孔17贯穿所述多个第二绝缘层16与所述多个牺牲层15且暴露出所述第一绝缘层11；再去除所有多个牺牲层15，在所述栅极孔17与去除的所有多个牺牲层15后的位置处填充导电材料形成栅极21。此步骤请参照图6A至图6C。
如图6A所示，通过黄光刻蚀方法图案化交替层叠设置的所述多个第二绝缘层16与所述多个牺牲层15以形成所述栅极孔17。通过所述栅极孔17采用刻蚀方法去除所述多个牺牲层15以形成所述栅极通道18。在本实施例中，在相同的刻蚀条件下，每一牺牲层15的刻蚀速率高于所述第一绝缘层11与每一第二绝缘层16的刻蚀速率，即，每一牺牲层15与所述第一绝缘层11蚀刻选择比大于1，即每一牺牲层15与每一第二绝缘层16蚀刻选择比大于1，从而使得在去除所述多个牺牲层15时能保留所述第一绝缘层11与每一第二绝缘层16。每一第二绝缘层16与所述第一绝缘层11均为绝缘材料，且每一牺牲层15为绝缘材料或非绝缘材料。在一实施例中，所述第一绝缘层11与每一第二绝缘层16为SiO2，每一牺牲层15为氮化硅SiN。
如图6B所示，去除多个牺牲层15之后且在形成所述栅极21之前，所述三维半导体的制作方法还包括：通过去除所述多个牺牲层15形成栅极通道18，在所述第一绝缘层11与所述多个第二绝缘层16分别与所述栅极通道18相接触的侧壁181上共形形成一薄的介电层20，且在所述第一绝缘层11与所述多个第二绝缘层16分别与所述栅极孔17相接触的侧壁171上形成介电层20。
如图6C所示，在形成所述介电层20之后，在所述栅极通道18与在所述栅极孔17内填充导电材料以形成栅极21。在本实施例中，所述介电层20为绝缘材质，可以为但不限于SiO2或SiN。形成所述栅极21的导电材料可以为但不限于掺杂半导体(掺杂硅、掺杂锗等)、导电金属氮化物(氮化钛、氮化钽等)、金属或金属-半导体化合物(硅化钨、硅化钴、硅化钛等)中的至少一种。
在本实施例中，所述介电层20、所述第一绝缘层11、每一第二绝缘层16与每一牺牲层15均可以通过一种或多种薄膜沉积工艺形成，其包括但不限于化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、旋涂式介电材料(SOD)或其任何组合。
在一实施例中，最后形成的为所述第二绝缘层16。
综上所述，在所述三维半导体结构的制作方法中，不需要开设贯穿所述第一绝缘层11与所述多个第二绝缘层16的通道孔且不需要在此通道孔内形成多个第一外延层13与多个第二外延层14。而是只形成贯穿所述第一绝缘层11的通道孔12且在该通道孔12内形成层叠设置的一个第一外延层13与一个第二外延层14，后续也是直接在该第二外延层14上直接生长又一第一外延层13且在该又一第一外延层13上直接生长又一第二外延层14，可容易实现多个第一外延层13与多个第二外延层14的上下层叠正对，即形成直立不歪斜的结构。则，即使随着所述第二绝缘层16的层数的增加，由该三维半导体结构的制作方法形成的多个第一外延层13与多个第二外延层14也能保持层叠正对准，使得多个第一外延层13与多个第二外延层14为直立不歪斜的结构。在所述三维半导体结构中，所述第一外延层13可作为源极区或漏极极区，利用选择性生长工艺方式形成不均匀掺杂的所述第一外延层13有利于降低漏极区或漏极区的电阻值，且包括多个堆叠层的三维半导体结构能够维持较低源极区与漏极区的串联阻值，从而有利于增加晶体管的工作电流与提高晶体管的响应速度。在本实施例中，由于采用选择性外延生长工艺形成半导体材质的多个第一外延层13与所述多个第二外延层14，形成层叠设置的多个第一外延层13与所述多个第二外延层14时不受到所述通道孔12的限制，所述通道孔12可以减小到一定程度。
本发明实施例还提供三维半导体结构100，所述三维半导体结构100由上述三维半导体结构的制作方法制得。所述三维半导体结构100可以为存储器，包括动态随机存取存储器与静态随机存取存储器。所述三维半导体结构100还可以为互补金属氧化物半导体。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。最后应说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术案的范围。

Claims (10)

1.一种三维半导体结构的制作方法，其特征在于，包括：
提供一衬板，在所述衬板上沉积第一绝缘层，在所述第一绝缘层上开设至少一通道孔，每一通道孔贯穿所述第一绝缘层且暴露出所述衬板；
在每一通道孔内依次层叠生成不均匀掺杂的第一外延层与第二外延层，所述第一外延层用于形成源极区或漏极区；
在所述第一绝缘层上形成牺牲层且使所述第二外延层相对所述牺牲层露出，在所述第二外延层上层叠生成又一第一外延层；在所述牺牲层上形成第二绝缘层且使所述又一第一外延层相对所述第二绝缘层暴露，在所述又一第一外延层上层叠生成又一第二外延层；以及
参照上一步骤，在所述第二绝缘层上依次交替地形成层叠设置的多个牺牲层与多个第二绝缘层，以及在所述又一第二外延层上依次交替地生成层叠设置的多个第一外延层与多个第二外延层。
2.如权利要求1所述的三维半导体结构的制作方法，其特征在于，依次层叠生成一个第一外延层与一个第二外延层的步骤包括：形成不均匀的N型掺杂的半导体材质的所述第一外延层与形成P型或N型轻掺杂的半导体材质的所述第二外延层。
3.如权利要求2所述的三维半导体结构的制作方法，其特征在于，形成不均匀的N型掺杂的半导体材质的所述第一外延层的步骤包括：依次形成层叠设置的P型轻掺杂的半导体材质的第一掺杂层、N型重掺杂的半导体材质的第二掺杂层以及P型轻掺杂的半导体材质的第三掺杂层，所述第二掺杂层的N型掺杂剂向所述第一掺杂层与所述第三掺杂层扩散以形成N型轻掺杂的半导体材质的所述第一外延层；或者，形成不均匀的N型掺杂的半导体材质的所述第一外延层的步骤包括：依次形成层叠设置的N型轻掺杂的半导体材质的第一掺杂层、N型重掺杂的半导体材质的第二掺杂层以及N型轻掺杂的半导体材质的第三掺杂层。
4.如权利要求1所述的三维半导体结构的制作方法，其特征在于，依次层叠生成一个第一外延层与一个第二外延层的步骤包括：形成不均匀的P型掺杂的半导体材质的所述第一外延层与形成N型或P型轻掺杂的半导体材质的所述第二外延层。
5.如权利要求4所述的三维半导体结构的制作方法，其特征在于，形成不均匀的P型掺杂的半导体材质的所述第一外延层的步骤包括：依次形成层叠设置的N型轻掺杂的半导体材质的第一掺杂层、P型重掺杂的半导体材质的第二掺杂层以及N型轻掺杂的半导体材质的第三掺杂层，所述第二掺杂层的P型掺杂剂向所述第一掺杂层与所述第三掺杂层扩散以形成N型轻掺杂的半导体材质的所述第一外延层；或者，形成不均匀的P型掺杂的半导体材质的所述第一外延层的步骤包括：依次形成层叠设置的P型轻掺杂的半导体材质的第一掺杂层、P型重掺杂的半导体材质的第二掺杂层以及P型轻掺杂的半导体材质的第三掺杂层。
6.如权利要求1所述的三维半导体结构的制作方法，其特征在于，在所述第一绝缘层上形成一个所述牺牲层的步骤包括：在所述第一绝缘层上沉积该牺牲层，平坦化该牺牲层使所述第二外延层相对该牺牲层露出；在一个第二绝缘层上形成一个所述牺牲层的步骤包括：在该第一绝缘层上沉积该牺牲层，平坦化该牺牲层使所述第二外延层相对该牺牲层露出；在牺牲层上形成一个所述第二绝缘层的步骤包括：在该牺牲层上沉积该第二绝缘层，并平坦化该第二绝缘层使所述第一外延层相对该第二绝缘层暴露。
7.如权利要求1所述的三维半导体结构的制作方法，其特征在于，所述的三维半导体结构的制作方法还包括：在所述多个第二绝缘层与所述多个牺牲层中开设栅极孔，所述栅极孔贯穿所述多个第二绝缘层与所述多个牺牲层且暴露出所述第一绝缘层；再去除所有多个牺牲层，在所述栅极孔与去除的所有多个牺牲层后的位置处填充导电材料形成栅极。
8.如权利要求7所述的三维半导体结构的制作方法，其特征在于，去除多个牺牲层之后且在形成所述栅极之前，所述三维半导体的制作方法还包括：通过去除所述多个牺牲层形成栅极通道，在所述第一绝缘层与所述多个第二绝缘层分别与所述栅极通道相接触的侧壁上形成介电层，且在所述第一绝缘层与所述多个第二绝缘层分别与所述栅极孔相接触的侧壁上形成介电层。
9.如权利要求8所述的三维半导体结构的制作方法，其特征在于，每一所述第一外延层与每一第二外延层采用选择性外延生长工艺形成；在相同的刻蚀条件下，每一牺牲层的刻蚀速率高于所述第一绝缘层与每一第二绝缘层的刻蚀速率。
10.一种三维半导体结构，其特征在于，所述三维半导体结构由如权利要求1至9任意一项所述三维半导体结构的制作方法制得。
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