CN107026083B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN107026083B
CN107026083B CN201610073020.0A CN201610073020A CN107026083B CN 107026083 B CN107026083 B CN 107026083B CN 201610073020 A CN201610073020 A CN 201610073020A CN 107026083 B CN107026083 B CN 107026083B
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material layer
fins
layer
isolation material
remaining
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CN107026083A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201610073020.0A priority Critical patent/CN107026083B/zh
Priority to US15/384,194 priority patent/US9985037B2/en
Priority to EP17153086.8A priority patent/EP3203508A1/en
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Abstract

本发明公开了一种半导体装置的制造方法，涉及半导体技术领域。所述方法包括：提供衬底结构，所述衬底结构包括：衬底，位于所述衬底上的多个鳍片，所述鳍片包括半导体层和位于所述半导体层上的硬掩模层，覆盖各个鳍片并填充各个鳍片之间的空间的第一隔离材料层；对所述第一隔离材料层进行第一回刻蚀，以露出各个鳍片的半导体层的一部分；对剩余的第一隔离材料层进行离子注入，并使注入的离子扩散到各个鳍片的半导体层中以在各个鳍片的半导体层中形成杂质区；对剩余的第一隔离材料层进行第二回刻蚀，以去除所述剩余的第一隔离材料层中注入离子的部分；在剩余的第一隔离材料层上形成第二隔离材料层。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置的制造方法。
背景技术
随着金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor FieldEffect Transistor，MOSFET)关键尺寸的缩小，短沟道效应(Short Channel Effect，SCE)成为一个至关重要的问题。鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)具有良好的栅控能力，能够有效地抑制短沟道效应。因此，在小尺寸的半导体元件设计中通常采用FinFET器件。
由于器件尺寸的减小，容易出现穿通效应(punch through effect)。为了抑制穿通效应，通常需要在鳍片的底部进行沟道停止离子注入(channel stop IMP)。然而对于N型金属氧化物半导体(N-Metal Oxide Semiconductor，NMOS)器件来说，在退火激活后，由于随机掺杂波动(Random Dopant Fluctuation，RDF)，通过沟道停止离子注入掺入的杂质很容易扩散到沟道或鳍片间的隔离区中，从而造成阱注入的离子的损失。因此，用于NMOS器件的沟道停止离子注入通常需要更大的离子注入剂量。
但是，发明人发现，更大的注入剂量会导致在退火后使得所注入的离子扩散到P型金属氧化物半导体(P-Metal Oxide Semiconductor，PMOS)器件中，使得鳍片由N型变为P型，从而影响器件的性能。这一问题在鳍片尺寸很小的静态随机存取存储器(StaticRandom Access Memory，SRAM)中尤为严重。
发明内容
本公开的一个实施例的目的在于提出一种半导体装置的制造方法，以至少减轻上述问题。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括：衬底，位于所述衬底上的多个鳍片，所述鳍片包括半导体层和位于所述半导体层上的硬掩模层，覆盖各个鳍片并填充各个鳍片之间的空间的第一隔离材料层；对所述第一隔离材料层进行第一回刻蚀，以露出各个鳍片的半导体层的一部分；对剩余的第一隔离材料层进行离子注入，并使注入的离子扩散到各个鳍片的半导体层中以在各个鳍片的半导体层中形成杂质区；对剩余的第一隔离材料层进行第二回刻蚀，以去除所述剩余的第一隔离材料层中注入离子的部分；在剩余的第一隔离材料层上形成第二隔离材料层。
在一个实施方式中，所述衬底包括P阱和N阱，所述多个鳍片包括位于P阱上的用于N沟道器件的第一组鳍片和位于N阱上的用于P沟道器件的第二组鳍片；所述对剩余的第一隔离材料层进行离子注入，以在各个鳍片中形成杂质区包括：对与第一组鳍片中的鳍片相邻的剩余的第一隔离材料层进行P型离子注入，以在第一组鳍片中的各鳍片中形成第一杂质区；对与第二组鳍片中的鳍片相邻的剩余的第一隔离材料层进行N型离子注入，以在第二组鳍片中的各鳍片中形成第二杂质区。
在一个实施方式中，所述P型离子注入所注入的离子包括硼离子或二氟化硼离子；所述N型离子注入所注入的离子包括砷离子。
在一个实施方式中，所述第一杂质区的掺杂浓度大于所述P阱的掺杂浓度；所述第二杂质区的掺杂浓度大于所述N阱的掺杂浓度。
在一个实施方式中，所述在剩余的第一隔离材料层上形成第二隔离材料层包括：沉积第二初始隔离材料层以覆盖各个鳍片和剩余的第一隔离材料层；对所述第二初始隔离材料层进行平坦化，以使剩余的第二初始隔离材料层的顶表面与所述硬掩模层的顶表面基本齐平；对剩余的第二初始隔离材料层进行回刻蚀，从而形成所述第二隔离材料层。
在一个实施方式中，所述第二回刻蚀使得剩余的第一隔离材料层的顶表面低于杂质区的底表面。
在一个实施方式中，所述第二隔离材料层的顶表面高于杂质区的顶表面。
在一个实施方式中，所述提供衬底结构的步骤包括：提供初始衬底，所述初始衬底包括初始半导体层；在所述初始半导体层上形成图案化的硬掩模层；以所述图案化的硬掩模层为掩模对所述初始半导体层进行刻蚀，从而形成所述多个鳍片；沉积第一隔离材料层以填充各个鳍片之间的空间并覆盖各个鳍片，从而形成所述衬底结构。
在一个实施方式中，还包括：执行退火工艺，以激活杂质区中的杂质。
在一个实施方式中，通过流体化学气相沉积形成所述第一隔离材料层；通过高纵深比制程技术形成所述第二隔离材料层。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图；
图2是根据本公开一个实施例的衬底结构的示意图；
图3A-图3C是示出根据本公开一些实施例的形成图2所示衬底结构的工艺过程的示意图；
图4是根据本公开一个实施例的对第一隔离材料层进行第一回刻蚀的示意图；
图5是根据本公开一个实施例的形成杂质区的示意图；
图6是根据本公开一个实施例的对剩余的第一隔离材料层进行第二回刻蚀的示意图；
图7至图9是根据本公开一个实施例的在剩余的第一隔离材料层上形成第二隔离材料层的工艺过程的示意图；
图10是根据本公开一个实施例的去除硬掩模层的示意图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图。如图1所示，在步骤101，提供衬底结构。图2示出了根据本公开一个实施例的衬底结构的示意图。如图2所示，该衬底结构包括衬底201，在一个实施例中，衬底201中可以形成有P阱211和N阱221。衬底结构还包括位于衬底201上的多个鳍片202，例如，多个鳍片202可以包括位于P阱211上的用于N沟道器件的第一组鳍片和位于N阱上的用于P沟道器件的第二组鳍片，每个鳍片202包括半导体层212和位于半导体层212上的硬掩模层222。衬底结构还包括覆盖各个鳍片202并填充各个鳍片202之间的空间的第一隔离材料层203。
图3A-图3C示出了根据本公开一个实施例的形成图2的衬底结构的工艺过程。
如图3A所示，提供初始衬底，该初始衬底包括初始半导体层301，初始半导体层301例如可以是硅(Si)层、锗(Ge)层或其他元素半导体层，或者是砷化镓(GaAs)等化合物半导体层。然而本公开并不限于此。之后，可以对初始半导体层301进行离子注入形成P阱211和N阱221。本公开并不限于此，例如，也可以先形成N阱221，在鳍片形成之后再形成P阱211。
如图3B所示，在初始半导体层301上形成图案化的硬掩模层222。该硬掩模层222例如可以是硅的氮化物、硅的氧化物、硅的氮氧化物等等。
如图3C所示，以图案化的硬掩模222为掩模对初始半导体层301进行刻蚀，例如干法刻蚀，以形成衬底201和位于衬底201上的多个鳍片202。
之后，沉积第一隔离材料层203以填充各个鳍片202之间的空间并覆盖各个鳍片202，从而形成图2所示的衬底结构。例如，可以通过诸如流式化学气相沉积(FlowableChemical Vapour Deposition,FCVD)的CVD技术等沉积第一隔离材料层203(例如电介质材料层)来填充各个鳍片202之间的空间并覆盖各个鳍片202，另外，在沉积第一隔离材料层203后还可以进行平坦化工艺。可选地，在沉积第一隔离材料层203之前，还可以在各个鳍片202的半导体层212的表面形成衬垫层(例如，通过热氧化形成氧化硅层，未示出)，以修复在刻蚀形成鳍片时对鳍片202造成的表面损伤。这里，各个鳍片的表面的衬垫层的一部分可能会在随后对第一隔离材料层的回刻蚀工艺中被去除。
应理解，也可以根据现有的其他方式来形成上述衬底结构，在此不再赘述。
回到图1，在步骤103，对第一隔离材料层203进行第一回刻蚀，以露出各个鳍片的半导体层212的一部分，如图4所示。
在步骤105，对剩余的第一隔离材料层进行离子注入，并使注入的离子扩散到各个鳍片的半导体层中以在各个鳍片的半导体层中形成杂质区。
如图5所示，可以首先对与P阱211上的第一组鳍片中的鳍片相邻的剩余的第一隔离材料层401进行P型离子注入(例如，注入硼离子或二氟化硼离子等)，注入的离子横向扩散(lateral straggle)到相邻的第一组鳍片中，以在第一组鳍片中的各鳍片中形成第一杂质区501，第一杂质区501可以用作沟道停止层；然后，对与第二组鳍片中的鳍片相邻的剩余的第一隔离材料层401进行N型离子注入(例如，注入砷离子等)，注入的离子横向扩散(lateral straggle)到相邻的第二组鳍片中，以在第二组鳍片中的各鳍片中形成第二杂质区502，第二杂质区502可以用作沟道停止层。另外，也可以先进行N型离子注入，再进行P型离子注入。优选地，所形成的第一杂质区501的掺杂浓度大于P阱211的掺杂浓度；所形成的第二杂质区502的掺杂浓度大于N阱221的掺杂浓度。
继续参见图1，在步骤107，对剩余的第一隔离材料层进行第二回刻蚀，以去除所述剩余的第一隔离材料层中注入离子的部分。
如图6所示，通过第二回刻蚀工艺去除剩余的第一隔离材料层401中注入离子的部分，优选地，第二回刻蚀使得剩余的第一隔离材料层601的顶表面低于杂质区(第一杂质区501和第二杂质区502)的底表面，以尽可能减少或去除第一隔离材料层中注入离子的部分。
继续参见图1，在步骤109，在剩余的第一隔离材料层上形成第二隔离材料层。
下面结合图7至图9对根据本公开一个实施例的在剩余的第一隔离材料层上形成第二隔离材料层的工艺过程进行示例性说明。
首先，如图7所示，沉积第二初始隔离材料层701以覆盖各个鳍片202和剩余的第一隔离材料层203。优选地，可以通过高纵深比制程(HARP)技术形成第二隔离材料203，以使得形成的第二隔离材料层203的性能更优。
然后，如图8所示，对第二初始隔离材料层701进行平坦化，例如化学机械抛光(CMP)，以使剩余的第二初始隔离材料层801的顶表面与硬掩模层222的顶表面基本齐平。
之后，如图9所示，对剩余的第二初始隔离材料层801进行回刻蚀，从而形成第二隔离材料层901。优选地，第二隔离材料层901的顶表面高于杂质区(第一杂质区501和第二杂质区502)的顶表面。
之后，可选地，还可以去除硬掩模层222，如图10所示。另外，可以执行退火工艺，以激活杂质区中的杂质。
如上，描述了本公开的半导体装置的制造方法。现有技术中，第一隔离材料层203中注入离子后，由于P型离子注入的剂量通常大于N型离子注入的剂量，因此，在后续的退火工艺中P型离子注入注入的离子有一部分会扩散到N阱221上的第二组鳍片中，使得第二组鳍片中与第一组鳍片相邻的鳍片由N型变成P型，从而影响PMOS器件的性能。而本公开在第一隔离材料层中进行沟道停止离子注入后，通过第二回刻蚀工艺将第一隔离材料层中注入离子的部分去除，之后再重新形成第二隔离材料层，从而减可以很好地避免上述问题。
至此，已经详细描述了根据本公开实施例的半导体装置的制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (6)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：
衬底，包括P阱和N阱，
位于所述衬底上的多个鳍片，所述鳍片包括半导体层和位于所述半导体层上的硬掩模层，所述多个鳍片包括位于P阱上的用于N沟道器件的第一组鳍片和位于N阱上的用于P沟道器件的第二组鳍片，和
覆盖各个鳍片并填充各个鳍片之间的空间的第一隔离材料层；
对所述第一隔离材料层进行第一回刻蚀，以露出各个鳍片的半导体层的一部分；
对剩余的第一隔离材料层进行离子注入，并使注入的离子扩散到各个鳍片的半导体层中以在各个鳍片的半导体层中形成杂质区，包括：
对与第一组鳍片中的鳍片相邻的剩余的第一隔离材料层进行P型离子注入，以在第一组鳍片中的各鳍片中形成第一杂质区，和
对与第二组鳍片中的鳍片相邻的剩余的第一隔离材料层进行N型离子注入，以在第二组鳍片中的各鳍片中形成第二杂质区；
对剩余的第一隔离材料层进行第二回刻蚀，以去除所述剩余的第一隔离材料层中注入离子的部分，所述第二回刻蚀使得剩余的第一隔离材料层的顶表面低于杂质区的底表面；
在剩余的第一隔离材料层上形成第二隔离材料层，所述第二隔离材料层的顶表面高于杂质区的顶表面、且低于所述鳍片的顶表面；
执行退火工艺，以激活杂质区中的杂质；
其中，所述P型离子注入的剂量大于所述N型离子注入的剂量。
2.根据权利要求1所述的方法，其特征在于，
所述P型离子注入所注入的离子包括硼离子或二氟化硼离子；
所述N型离子注入所注入的离子包括砷离子。
3.根据权利要求1所述的方法，其特征在于，
所述第一杂质区的掺杂浓度大于所述P阱的掺杂浓度；
所述第二杂质区的掺杂浓度大于所述N阱的掺杂浓度。
4.根据权利要求1所述的方法，其特征在于，所述在剩余的第一隔离材料层上形成第二隔离材料层包括：
沉积第二初始隔离材料层以覆盖各个鳍片和剩余的第一隔离材料层；
对所述第二初始隔离材料层进行平坦化，以使剩余的第二初始隔离材料层的顶表面与所述硬掩模层的顶表面基本齐平；
对剩余的第二初始隔离材料层进行回刻蚀，从而形成所述第二隔离材料层。
5.根据权利要求1所述的方法，其特征在于，所述提供衬底结构的步骤包括：
提供初始衬底，所述初始衬底包括初始半导体层；
在所述初始半导体层上形成图案化的硬掩模层；
以所述图案化的硬掩模层为掩模对所述初始半导体层进行刻蚀，从而形成所述多个鳍片；
沉积第一隔离材料层以填充各个鳍片之间的空间并覆盖各个鳍片，从而形成所述衬底结构。
6.根据权利要求1所述的方法，其特征在于，
通过流体化学气相沉积形成所述第一隔离材料层；
通过高纵深比制程技术形成所述第二隔离材料层。
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