CN106816464B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN106816464B
CN106816464B CN201510861184.5A CN201510861184A CN106816464B CN 106816464 B CN106816464 B CN 106816464B CN 201510861184 A CN201510861184 A CN 201510861184A CN 106816464 B CN106816464 B CN 106816464B
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fins
well
substrate
hard mask
fin
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CN106816464A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/283,239 priority patent/US9984939B2/en
Priority to EP16199529.5A priority patent/EP3176816B1/en
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Abstract

本发明公开了一种半导体装置的制造方法，涉及半导体技术领域。所述方法包括：提供衬底；对所述衬底进行N型掺杂以在所述衬底中形成N阱；对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片；在各个鳍片之间形成隔离区以至少部分填充各个鳍片之间的空间；对所述第二组鳍片下的衬底进行P型掺杂，以形成与所述N阱邻接的P阱。本发明将形成N阱和P阱的时机分开，在鳍片形成之前进行N型掺杂形成N阱，在鳍片形成之后进行P型掺杂形成P阱，一方面，避免了P阱中掺杂的离子在形成隔离区时扩散到隔离区中导致的离子的损失；另一方面，也避免了N型掺杂对鳍片的损伤。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置的制造方法。
背景技术
随着金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor FieldEffect Transistor，MOSFET)关键尺寸的缩小，短沟道效应(Short Channel Effect，SCE)成为一个至关重要的问题。鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)具有良好的栅控能力，能够有效地抑制短沟道效应。并且，FinFET降低了器件的随机掺杂波动(Random Dopant Fluctuation，RDF)，提高了器件的稳定性。因此，在小尺寸的半导体元件设计中通常采用FinFET器件。
在FinFET器件的制造工艺中，通常情况下，进行阱注入(包括N阱注入和P阱注入)的时机可以是以下三种情况之一：在鳍片形成之前、或者在对浅沟槽隔离(STI)区进行平坦化之后、或者在鳍片形成之后。
如果在鳍片形成之前进行N阱注入和P阱注入，由于之后会采用流体化学气相沉积(FCVD)在鳍片之间的间隙中填充氧化物，阱注入的离子尤其是P阱注入的离子会很容易扩散到氧化物中，从而造成阱注入的离子的损失。
如果在STI区进行平坦化之后进行N阱注入和P阱注入，由于STI区上具有硬掩模，因此，进行阱注入需要很高的离子能量。
如果在鳍片形成之后进行N阱注入和P阱注入，可能会造成对鳍片的损伤，尤其对于N阱注入来说，注入的离子能量比较高，对鳍片的损伤会更严重。
发明内容
本公开的一个实施例的目的在于：至少解决或减轻上述问题中的一个。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底；对所述衬底进行N型掺杂以在所述衬底中形成N阱；对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片；在各个鳍片之间形成隔离区以至少部分填充各个鳍片之间的空间；对所述第二组鳍片下的衬底进行P型掺杂，以形成与所述N阱邻接的P阱。
在一个实施方式中，所述对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片包括：在所述衬底上形成图案化的硬掩模；以所述图案化的硬掩模为掩模对所述衬底进行刻蚀，从而形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片。
在一个实施方式中，所述在各个鳍片之间形成隔离区以至少部分填充各个鳍片之间的空间包括：沉积隔离材料以填充各个鳍片之间的空间并覆盖各个鳍片和鳍片上的硬掩模；对所述隔离材料进行平坦化，以使隔离材料的顶表面与所述硬掩模的顶表面基本齐平，从而在各个鳍片之间形成隔离区。
在一个实施方式中，对所述隔离材料进行平坦化之后，还包括：对所述隔离材料进行回刻蚀，以至少露出各个鳍片上的硬掩模；去除各个鳍片上的硬掩模，从而在各个鳍片之间形成隔离区。
在一个实施方式中，还包括：在形成P阱之后，去除所述隔离区的一部分以露出各个鳍片的至少一部分。
在一个实施方式中，通过离子注入的方式进行所述N型掺杂和所述P型掺杂。
在一个实施方式中，所述N型掺杂的杂质包括砷离子或磷离子；所述P型掺杂的杂质包括硼离子或二氟化硼离子。
根据本公开的另一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括衬底、位于所述衬底上的多个鳍片和位于各个鳍片之间的隔离区，其中所述鳍片上具有硬掩模，所述隔离区的顶表面与所述硬掩模的顶表面基本齐平；对所述衬底结构进行N型掺杂，以在衬底中形成N阱；对所述隔离区进行回刻蚀，以至少露出各个鳍片上的硬掩模；去除各个鳍片上的硬掩模；对所述衬底结构进行P型掺杂，以在所述衬底中形成与所述N阱邻接的P阱。
在一个实施方式中，所述提供衬底结构的步骤包括：提供初始衬底；在所述初始衬底上形成图案化的硬掩模；以所述图案化的硬掩模为掩模对所述初始衬底进行刻蚀以形成所述衬底和位于所述衬底上的多个鳍片；沉积隔离材料以填充各个鳍片之间的空间并覆盖各个鳍片和鳍片上的硬掩模；对所述隔离材料进行平坦化，以形成所述隔离区，从而形成所述衬底结构。
在一个实施方式中，还包括：在形成P阱之后，去除所述隔离区的一部分以露出各个鳍片的至少一部分。
在一个实施方式中，通过离子注入的方式进行所述N型掺杂和所述P型掺杂。
在一个实施方式中，所述N型掺杂的杂质包括砷离子或磷离子；所述P型掺杂的杂质包括硼离子或二氟化硼离子。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图；
图2示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图3示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图4示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图5示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图6示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图7示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图8示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图9示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图10示出了根据本公开的一些实施例的半导体装置的制造方法的一个阶段的截面图；
图11是根据本公开另一个实施例的半导体装置的制造方法的简化流程图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1为根据本公开一个实施例的半导体装置的制造方法的简化流程图。如图1所示，本实施例的半导体装置的制造方法包括：
步骤101，提供衬底，例如硅衬底等其他半导体衬底。
步骤103，对衬底进行N型掺杂以在衬底中形成N阱。例如，可以通过离子注入或扩散的方式对衬底(例如衬底的一部分)进行N型掺杂以在衬底中形成N阱，N型掺杂的杂质可以包括砷离子或磷离子等。
步骤105，对衬底进行刻蚀以形成位于N阱上的第一组鳍片以及位于与N阱邻接的衬底上的第二组鳍片。
步骤107，在各个鳍片之间形成隔离区(例如STI区)以至少部分填充各个鳍片之间的空间。
一种情况下，隔离区可以基本填充满各个鳍片之间的空间；另一种情况下，隔离区可以部分填充各个鳍片之间的空间。后文将针对这两种情况分别作出说明。
步骤109，对第二组鳍片下的衬底进行P型掺杂，以形成与N阱邻接的P阱。例如，可以通过离子注入或扩散的方式对第二组鳍片下的衬底(例如第二组鳍片下的衬底的一部分)进行P型掺杂，P型掺杂的杂质可以包括硼离子或二氟化硼离子等。
本实施例中，将形成N阱和P阱的时机分开，在鳍片形成之前进行N型掺杂形成N阱，在鳍片形成之后进行P型掺杂形成P阱，一方面，避免了P阱中掺杂的离子在形成隔离区时扩散到隔离区中导致的离子的损失；另一方面，也避免了N型掺杂对鳍片的损伤。
需要指出的是，除非特别指出，否则本文中的术语“基本填充满”和是指在半导体工艺偏差范围内的填充满，“基本齐平”是指在半导体工艺偏差范围内的齐平。
下面结合图2-图10对本公开一些实施例的半导体装置的制造方法进行详细说明。
首先，如图2所示，提供衬底201，并对衬底201进行N型掺杂以在衬底中形成N阱211。例如，可以通过离子注入的方式在衬底201(例如衬底201的一部分)中注入砷离子或磷离子，通过控制注入的深度和注入杂质的浓度可以形成期望的N阱211。这里，在进行离子注入前可以在衬底201上形成垫氧化层(pad oxide)(图中未示出)，以减少注入对衬底造成的损伤。此外，在进行N型掺杂后，可以进行退火工艺，例如快速热退火RTA，以激活掺入的杂质。
然后，如图3所示，在衬底201上形成图案化的硬掩模300，该硬掩模300例如可以是硅的氮化物、硅的氧化物、硅的氮氧化物等等。以图案化的硬掩模300为掩模对衬底201进行刻蚀，从而形成位于N阱211上的第一组鳍片301以及位于与N阱邻接的衬底上的第二组鳍片302。这里，在一些实施例中，第一组鳍片301与N阱211邻接的区域也可以包括一部分N型掺杂的区域，也即，在对衬底201进行刻蚀时也有可能对N阱的一部分进行了刻蚀。
之后，如图4所示，沉积隔离材料401以填充各个鳍片之间的空间并覆盖各个鳍片(301，302)和鳍片上的硬掩模300。例如，可以通过诸如流式化学气相沉积(FlowableChemical Vapour Deposition,FCVD)的CVD技术等沉积隔离材料401(例如电介质材料)来填充各个鳍片之间的空间并覆盖各个鳍片。
接下来，如图5所示，对隔离材料401进行平坦化，例如可以对隔离材料401进行化学机械抛光，以使隔离材料401的顶表面与硬掩模300的顶表面基本齐平，从而在各个鳍片之间形成隔离区501。这种情况下，隔离区501基本填充满各个鳍片之间的空间。
之后，如图6所示，对第二组鳍片302下的衬底的一部分进行P型掺杂，以形成与N阱211邻接的P阱221。例如，可以通过离子注入的方式在衬底201中注入硼离子或二氟化硼离子等，以形成P阱221。如果通过离子注入的方式进行P型掺杂，由于硬掩模300的存在，需要较大的注入能量。
在另一些实施例中，在图5所示的对隔离材料进行平坦化之后，可以对隔离材料401进行回刻蚀，以至少露出各个鳍片上的硬掩模300，如图7所示。这里，可以只露出各个鳍片上的硬掩模300，而不露出各个鳍片；或者也可以露出各个鳍片的一部分。图7示出的是露出各个鳍片上的硬掩模300，同时也露出各个鳍片的一部分的情况。
然后，如图8所示，去除各个鳍片上的硬掩模300，从而在各个鳍片之间形成隔离区501。这种情况下，隔离区501部分地填充各个鳍片之间的空间。
之后，如图9所示，对第二组鳍片302下的衬底的一部分进行P型掺杂，以形成与N阱211邻接的P阱221。在进行P型掺杂后，可以进行退火工艺，例如快速热退火RTA，以激活掺入的杂质。应理解，在前述掺杂和/或退火工艺中，掺入的杂质可能会存在于一部分鳍片(例如302)中或向鳍片302中扩散，从而使得形成的P阱221还包括鳍片302的一部分。
之后，如图10所示，在形成P阱221之后，去除隔离区501的一部分以露出各个鳍片的至少一部分，使得鳍片的顶表面与隔离区的顶表面达到期望的高度。应理解，该步骤不是必须的。在一些实施例中，也可以在图7所示的对隔离材料401进行回刻蚀的步骤中使得鳍片的顶表面与隔离区的顶表面达到期望的高度。
之后，可以进行阈值电压离子注入以及退火等工艺。由于之后的工艺并发本公开的重点，故在此不再赘述。
图11为根据本公开另一个实施例的半导体装置的制造方法的简化流程图。如图11所示，本实施例的半导体装置的制造方法包括：
步骤1101，提供衬底结构，该衬底结构包括衬底、位于衬底上的多个鳍片和位于各个鳍片之间的隔离区，其中鳍片上具有硬掩模，隔离区的顶表面与硬掩模的顶表面基本齐平(参见图5)。
步骤1103，对衬底结构的一部分进行N型掺杂，以在衬底中形成N阱。例如，可以通过离子注入或扩散的方式进行N型掺杂，N型掺杂的杂质可以包括砷离子或磷离子等(参见图5)。
步骤1105，对隔离区进行回刻蚀，以至少露出各个鳍片上的硬掩模(参见图7)。
步骤1107，去除各个鳍片上的硬掩模(参见图8)。
步骤1109，对衬底结构的另一部分进行P型掺杂，以在衬底中形成与N阱邻接的P阱(参见图9)。例如，可以通过离子注入或扩散的方式进行P型掺杂，P型掺杂的杂质可以包括硼离子或二氟化硼离子等。
本实施例中，将形成N阱和P阱的时机分开，与图1所示实施例相比，本实施例是硬掩模未去除之前进行N型掺杂形成N阱，在鳍片形成之后进行P型掺杂形成P阱，与图1所示实施例类似地，本实施例同样可以获得如下效果：一方面，避免了P阱中掺杂的离子在形成隔离区时扩散到隔离区中导致的离子的损失；另一方面，也避免了N型掺杂对鳍片的损伤。
上述步骤1101中提供衬底结构的步骤可以通过如下方式来实现：
提供初始衬底；在初始衬底上形成图案化的硬掩模；以图案化的硬掩模为掩模对初始衬底进行刻蚀以形成衬底和位于衬底上的多个鳍片；沉积隔离材料以填充各个鳍片之间的空间并覆盖各个鳍片和鳍片上的硬掩模；对隔离材料进行平坦化，以形成隔离区，从而形成衬底结构。
在一个实施例中，上述方法还可以包括：在形成P阱之后，去除隔离区的一部分以露出各个鳍片的至少一部分，使得鳍片的顶表面与隔离区的顶表面达到期望的高度。
至此，已经详细描述了根据本公开实施例的半导体装置的制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (10)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底；
对所述衬底进行N型掺杂以在所述衬底中形成N阱；
对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片；
在各个鳍片之间形成隔离区以至少部分填充各个鳍片之间的空间；
在形成所述隔离区之后，对所述第二组鳍片下的衬底进行P型掺杂，以形成与所述N阱邻接的P阱。
2.根据权利要求1所述的方法，其特征在于，所述对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片包括：
在所述衬底上形成图案化的硬掩模；
以所述图案化的硬掩模为掩模对所述衬底进行刻蚀，从而形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片。
3.根据权利要求2所述的方法，其特征在于，所述在各个鳍片之间形成隔离区以至少部分填充各个鳍片之间的空间包括：
沉积隔离材料以填充各个鳍片之间的空间并覆盖各个鳍片和鳍片上的硬掩模；
对所述隔离材料进行平坦化，以使隔离材料的顶表面与所述硬掩模的顶表面基本齐平，从而在各个鳍片之间形成隔离区。
4.根据权利要求1或3所述的方法，其特征在于，还包括：
在形成P阱之后，去除所述隔离区的一部分以露出各个鳍片的至少一部分。
5.根据权利要求1所述的方法，其特征在于，通过离子注入的方式进行所述N型掺杂和所述P型掺杂。
6.根据权利要求1所述的方法，其特征在于，所述N型掺杂的杂质包括砷离子或磷离子；
所述P型掺杂的杂质包括硼离子或二氟化硼离子。
7.一种半导体装置的制造方法，其特征在于，包括：
提供衬底；
对所述衬底进行N型掺杂，以在衬底中形成N阱；
在所述衬底上形成图案化的硬掩模；
以所述图案化的硬掩模为掩模对所述衬底进行刻蚀以形成位于所述N阱上的第一组鳍片以及位于与所述N阱邻接的衬底上的第二组鳍片；
沉积隔离材料以填充各个鳍片之间的空间并覆盖各个鳍片和鳍片上的硬掩模；
对所述隔离材料进行平坦化，以使得所述隔离材料的顶表面与所述硬掩模的顶表面基本齐平；
对所述隔离材料进行回刻蚀，以至少露出各个鳍片上的硬掩模；
去除各个鳍片上的硬掩模，从而在各个鳍片之间形成隔离区；
在去除所述硬掩模之后，对所述第二组鳍片下的衬底进行P型掺杂，以在所述衬底中形成与所述N阱邻接的P阱。
8.根据权利要求7所述的方法，其特征在于，还包括：
在形成P阱之后，去除所述隔离区的一部分以露出各个鳍片的至少一部分。
9.根据权利要求7所述的方法，其特征在于，通过离子注入的方式进行所述N型掺杂和所述P型掺杂。
10.根据权利要求7所述的方法，其特征在于，所述N型掺杂的杂质包括砷离子或磷离子；
所述P型掺杂的杂质包括硼离子或二氟化硼离子。
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