CN103378153A - 用于集成有电容器的FinFET的结构和方法 - Google Patents

用于集成有电容器的FinFET的结构和方法 Download PDF

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CN103378153A
CN103378153A CN2012102387397A CN201210238739A CN103378153A CN 103378153 A CN103378153 A CN 103378153A CN 2012102387397 A CN2012102387397 A CN 2012102387397A CN 201210238739 A CN201210238739 A CN 201210238739A CN 103378153 A CN103378153 A CN 103378153A
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胡嘉欣
张胜杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供用于集成有电容器的FinFET的结构和方法，其中，半导体结构的一个实施例包括：半导体衬底，具有第一区域和第二区域；浅沟槽隔离(STI)部件，形成在半导体衬底中。STI部件包括设置在第一区域中并具有第一厚度T1的第一部分和设置在第二区域中并具有大于第一深度的第二厚度T2的第二部分，STI部件的第一部分相对于STI部件的第二部分凹陷。半导体结构还包括：多个鳍式有源区，位于半导体衬底上；以及多个导电部件，设置在鳍式有源区和STI部件上，其中，一个导电部件覆盖第一区域中的STI部件的第一部分。

Description

用于集成有电容器的FinFET的结构和方法
技术领域
本发明涉及半导体领域，尤其涉及用于集成有电容器的FinFET的结构和方法。
背景技术
集成电路已经发展到具有高封装密度和较小部件尺寸(诸如45nm、32nm、28nm和20nm)的先进技术。在这些先进技术中，每个都具有多鳍结构的三维晶体管通常被期望用于增强的器件性能。然而，用于这种结构的现有方法和结构具有与器件质量和可靠性相关的多种问题和缺点。例如，在多晶硅蚀刻期间会引入多种缺陷或残留。在另一个实例中，电容器结构不容易在仍然保持在可接受范围内调整其电容的能力的同时与鳍式晶体管集成。此外，由于诸如需要附加掩膜来限定电容器的一个或多个部件的附加工艺步骤而导致制造成本更高。因此，需要集成有鳍式式晶体管和电容器的结构及其制造方法以解决以上问题。
发明内容
根据本发明的一个方面，提供了一种半导体结构，包括：半导体衬底，具有第一区域和第二区域；浅沟槽隔离(STI)部件，形成在半导体衬底中，其中，STI部件包括设置在第一区域中并具有第一厚度T1的第一部分和设置在第二区域中并具有大于第一厚度T1的第二厚度T2的第二部分，STI部件的第一部分相对于STI部件的第二部分凹陷；多个鳍式有源区，位于半导体衬底上；以及多个导电部件，设置在鳍式有源区和STI部件上，其中，一个导电部件覆盖第一区域中的STI部件的第一部分。
优选地，STI部件的第一部分相对于STI部件的第二部分凹陷，使得第一部分的顶面比第二部分的顶面低(T2-T1)。
优选地，半导体结构进一步包括多个介电部件，位于导电部件下方并使导电部件与鳍式有源区分离。
优选地，半导体结构进一步包括：电容器，设置在第一区域中，电容器包括一个鳍式有源区、一个导电部件以及使一个导电部件与一个鳍式有源区分离的一个介电部件；以及晶体管，设置在第二区域中。
优选地，电容器是去耦电容器，晶体管是场效应晶体管。
优选地，半导体结构进一步包括：第一晶体管，设置在第一区域中，第一晶体管包括第一栅叠层，第一栅叠层具有介电部件中的第一介电部件和覆盖介电部件中的第一介电部件的导电部件中的第一导电部件；以及第二晶体管，设置在第二区域中，第二晶体管包括第二栅叠层，第二栅叠层具有介电部件中的第二介电部件和覆盖介电部件中的第二介电部件的导电部件中的第二导电部件，其中，介电部件中的第一介电部件具有第一电介质厚度，介电部件中的第二介电部件具有不同于第一电介质厚度的第二电介质厚度。
优选地，多个导电部件包括：第一导电部件，设置在第一区域中并具有第一宽度W1；以及第二导电部件，设置在第二区域中并具有小于第一宽度W1的第二宽度W2。
优选地，多个介电部件包括：第一介电部件，设置在第一区域中，位于第一导电部件下方并具有第一介电材料；以及第二介电部件，设置在第二区域中，位于第二导电部件下方并具有不同于第一介电材料的第二介电材料。
优选地，第一导电部件、第一介电部件以及鳍式有源区的第一子集被配置成形成电容器；以及第二导电部件、第二介电部件以及鳍式有源区的第二子集被配置成形成鳍式场效应晶体管(FinFET)。
根据本发明的第二方面，提供了一种半导体结构，包括：半导体衬底，具有第一区域和第二区域；鳍式有源区，形成在半导体衬底上并在第一区域和第二区域中延伸；浅沟槽隔离(STI)部件，形成在半导体衬底中并与鳍式有源区相邻，其中，STI部件包括：设置在第一区域中的第一部分和设置在第二区域中的第二部分，并且STI部件的第一部分具有第一顶面，STI部件的所述第二部分具有高于第一顶面的第二顶面；第一导电部件，形成在鳍式有源区和STI部件上，其中，第一导电部件设置在第一区域中并覆盖STI部件的第一部分；以及第二导电部件，形成在鳍式有源区和STI部件上，其中，第二导电部件设置在第二区域中。
优选地，半导体结构进一步包括：第一介电部件，与第一导电部件对准并位于第一导电部件下方；以及第二介电部件，与第二导电部件对准并位于第二导电部件下方。
优选地，鳍式有源区、第一介电部件和第一导电部件被配置并耦合以形成电容器；以及鳍式有源区、第二介电部件和第二导电部件被配置并耦合以形成场效应晶体管。
优选地，第一导电部件包括第一宽度；以及第二导电部件包括小于第一宽度的第二宽度。
优选地，第一介电部件包括第一厚度；以及第二介电部件包括不同于第一厚度的第二厚度。
优选地，第一介电部件包括第一介电材料；以及第二介电部件包括不同于第一介电材料的第二介电材料。
优选地，鳍式有源区在第一方向上定向；以及第一导电部件和第二导电部件在垂直于第一方向的第二方向上定向。
根据本发明的又一方面，提供了一种方法，包括：蚀刻半导体衬底，以形成多个沟槽并限定多个鳍式有源区；用介电材料填充多个沟槽以形成浅沟槽隔离(STI)部件；使第一区域中的STI部件的第一子集凹陷第一尺寸；使第二区域中的STI部件的第二子集凹陷小于第一尺寸的第二尺寸；以及在STI部件和鳍式有源区上形成导电部件，其中，导电部件覆盖STI部件的第一子集。
优选地，使第一区域中的STI部件的所述第一子集凹陷第一尺寸；以及使第二区域中的STI部件的第二子集凹陷包括：在半导体衬底上形成图案化光刻胶层，图案化光刻胶层具有暴露第一区域的开口并覆盖第二区域；通过图案化光刻胶层的开口对第一区域中的STI部件的第一子集执行第一STI蚀刻；去除图案化光刻胶层；以及对第一区域中的STI部件的第一子集和第二区域中的STI部件的第二子集执行第二STI蚀刻，使得STI部件的第一子集相对于STI部件的第二子集凹陷。
优选地，该方法进一步包括：在执行第一STI蚀刻之后并且在执行第二STI蚀刻之前，对半导体衬底执行阱注入。
优选地，该方法进一步包括：在半导体衬底上沉积硬掩膜层；使用光刻工艺图案化硬掩膜层，其中，蚀刻半导体衬底以形成多个沟槽并限定多个鳍式有源区包括：通过硬掩膜层的开口蚀刻半导体衬底；以及在第一STI蚀刻之后并且在执行阱注入之前，去除硬掩膜层。
附图说明
当读取附图时，根据以下详细描述更好地理解本公开的多个方面。应该强调的是，根据工业中的标准实践，多种部件没有按比例绘制。事实上，为了论述的清楚，多种部件的尺寸可以任意增加或减小。
图1是一个或多个实施例中根据本公开的多个方面构造的具有鳍式式有源区和凹陷隔离部件的半导体结构的顶视图。
图2至图5是一个或多个实施例中根据本公开的多个方面构造的图1的半导体结构的截面图。
图6是一个或多个实施例中根据本公开的多个方面构造的图1的半导体结构的部分立体图。
图7是一个实施例中根据本公开的多个方面构造的图6的半导体结构的截面图。
图8是另一个实施例中根据本公开的多个方面构造的半导体结构的顶视图。
图9和图10是一个或多个其他实施例中根据本公开的多个方面构造的半导体结构的截面图。
图11是一个实施例中根据本公开的多个方面构造的图1的半导体结构的制造方法的流程图。
图12至图21是处于根据图11的方法构造的多个制造阶段的半导体结构的截面图。
具体实施方式
应该理解，以下公开提供了用于实现多种实施例的不同部件的多个不同实施例或实例。以下描述部件和布置的特定实例以简化本公开。当然，这些仅是实例并且不用于限制。另外，本公开可以在多个实例中重复参考数字和/或字母。这种重复是为了简单和清楚的目的并且其本身不表示所论述的多种实施例和/或配置之间的关系。此外，以下说明中第一部件在第二部件之上或上形成可以包括第一和第二部件直接接触形成的实施例，并且可以包括可形成插入第一和第二部件之间的附加部件，使得第一和第二部件可以不直接接触的实施例。
图1是具有鳍式有源区和凹陷隔离部件的半导体结构100的顶视图。图2至图5是半导体结构100的截面图。具体地，图2是从剖面线AA’截取的截面图，图3是从剖面线BB’截取的截面图，图4是从剖面线CC’截取的截面图，以及图5是从剖面线DD’截取的截面图。参照图1至图5描述半导体结构100。
半导体结构100包括衬底102。衬底102包括硅。可选地，衬底102包括锗、硅锗或其他合适的半导体材料。衬底102还包括多种掺杂区。在一个实施例中，衬底102包括外延半导体层。在另一个实施例中，衬底102包括通过适当技术(诸如称为注氧隔离(SIMOX)的技术)形成的用于隔离的掩埋介电材料层。
半导体衬底100包括在衬底102上形成的一个或多个鳍状有源区(鳍式有源区)104。鳍式有源区104是一种或多种半导体材料的有源区并且在衬底102的顶面之上突出。因此，鳍式有源区104是使多个表面暴露并提供将栅电极电容耦合至场效应晶体管(FET)中的相应沟道的有效方式的三维有源区。
鳍式有源区104包括硅或其他合适的半导体材料，诸如硅锗。鳍式有源区104包括与衬底102的半导体材料相同的半导体材料。在可选实施例中，鳍式有源区104包括与衬底102的半导体材料不同的半导体材料，通过诸如外延生长的合适技术形成。例如，在合适配置中，衬底102包括硅，并且鳍式有源区包括硅锗、碳化硅或两者。
半导体衬底100包括在衬底中形成的浅沟槽隔离(STI)部件106以隔离多种有源区。STI部件106包括一种或多种介电材料，诸如氧化硅、氮化硅、氮氧化硅、其他合适的介电材料或组合。STI部件的形成可以包括：在衬底中蚀刻沟槽；以及通过介电材料填充沟槽。所填充的沟槽可以具有多层结构，诸如具有填充沟槽的氮化硅的热氧化物衬里层。在一个实施例中，STI结构可以使用诸如以下的工艺序列来产生：生长焊盘氧化物，形成低压化学汽相沉积(LPCVD)氮化物层，使用光刻胶图案化STI开口并掩蔽，在衬底中蚀刻沟槽，可选地生长热氧化物沟槽衬里以改进沟槽界面，用氧化物填充沟槽，使用化学机械平面化(CMP)进行深蚀刻，以及使用氮化物蚀刻以去除氮化物层。
半导体结构100包括第一区域108和邻近第一区域的第二区域110。如图1所示，第一区域108是由虚线限定的区域。第二区域110包括图1中的其余区域。在本实施例中，第一区域108被第二区域110围绕。
具体地，第一区域108中的STI部件106(还被称为STI部件的第一部分)相对于第二区域110中的STI部件106(还被称为STI部件的第二部分)凹陷。如图2所示，第一区域108中的STI部件106具有第一厚度T1，并且第二区域110中的STI部件106具有第二厚度T2。第二厚度T2大于第一厚度T1。此外，STI部件的第一部分的顶面比STI部件的第二部分的顶面底(T2-T1)的距离。
半导体结构100包括一个或多个介电部件112和导电部件114。介电部件112设置在鳍式有源区104和STI部件106上。导电部件114设置在介电部件112上。导电部件114中的一个被配置成覆盖第一区域108并且覆盖第一区域108中的鳍式有源区104。
在图1所示的一个实施例中，鳍式有源区104被定向在第一方向(“X”方向)上，同时导电部件114被定向在第二方向(“Y”方向)上。两个方向相互垂直。
如图1所示，半导体结构100包括设置在第一区域108中的第一导电部件114。半导体结构100包括设置在第二区域110中的第二和第三导电部件114。第一区域108中的第一导电部件具有第一宽度W1，并且第二区域110中的第二(或第三)导电部件具有不同于第一宽度W1的第二宽度W2。具体地，W1大于W2。从而，第一、第二和第三介电部件是指分别位于第一、第二和第三导电部件下方的那些部件。
第一导电部件114被设计成覆盖第一区域108。在图1所示的实例中，第一区域具有沿着第一方向的尺寸D。对于全覆盖，W1大于D。而且，第一导电部件114在第一方向(X方向)上延伸到第二区域110中尺寸S 1，并且在第二方向(Y方向)上延伸到第二区域中尺寸S2，使得第一区域108被第一导电部件覆盖。
介电部件112与导电部件114对准并且使导电部件114与鳍式有源区104隔离。在一个实例中，介电部件112和导电部件114通过以下过程形成，包括：在衬底102上沉积介电层，在介电层上沉积导电层，以及使用光刻工艺和蚀刻图案化介电层和导电层以形成多种介电部件112和导电部件114。
在一个实施例中，第一导电部件、第一介电部件和鳍式有源区的部分在第一区域108中被配置和耦合以形成电容器，诸如去耦电容器。第二导电部件、第二介电部件和鳍式有源区的其他部分被配置并耦合以形成鳍式场效应晶体管(FinFET)。
在电容器中，第一导电部件、第一介电部件和鳍式有源区的部分分别用作第一电极、电容器电介质和第二电极。在场效应晶体管中，第二导电部件和第二介电部件用作栅电极和栅极电介质，共同作为栅叠层。源极和漏极部件形成在鳍式有源区的其他部分上并且插入栅叠层。
由于电容器形成在鳍式有源区中，所以其在制造方面与晶体管可兼容。另外，电容器形成在STI部件的凹陷部分中，电容器区域进一步增加，而不增加由电容器所占用的相应衬底面积。而且，当第一导电部件的宽度W1大于第二导电部件的宽度时，电容器区域甚至进一步增加用于更大范围以调整电容。
在一个实施例中，作为电容器电介质的第一介电部件包括第一介电材料，并且作为栅极电介质的第二介电部件包括第二介电材料。第一和第二介电材料相互相同或者可选地相互不同。例如，栅极电介质可以使用被调整用于晶体管性能的氧化硅、高k介电材料以及组合中的一个。电容器电介质可以使用被调整用于合适电容的氧化硅、高k介电材料和低k介电材料中的另一个。
在另一个实施例中，作为电容器电介质的第一介电部件包括第一厚度，并且作为栅极电介质的第二介电部件包括第二厚度。第一和第二电介质厚度相同或者可选地不同，以调整用于各自的器件性能。
在栅极电介质和电容器电介质具有不同成分、不同厚度或两者的情况下，它们被单独形成。在栅极电介质和电容器电介质具有相同成分和相同厚度的情况下，它们通过相同的过程同时形成。
在可选实施例中，第一导电部件、第一介电部件以及鳍式有源区的部分被配置并耦合以在第一区域108中形成第一FinFET。在这种情况下，第一导电部件和第一介电部件分别用作栅电极和栅极电介质，统称为第一栅叠层。第二导电部件、第二介电部件和鳍式有源区的其他部分被配置并耦合以形成第二FinFET。第二FinFET的栅叠层还被称为第二栅叠层。
在一个实施例中，作为用于第一FinFET的栅极电介质的第一介电部件包括第一介电材料，并且作为用于第二FinFET的栅极电介质的第二介电部件包括第二介电材料。第一和第二介电材料相互相同或者可选地相互不同。
在另一个实施例中，第一介电部件包括第一厚度，并且第二介电部件包括第二厚度。第一和第二电介质厚度相同或者可选地不同，以调整用于各自的器件性能。
在栅极电介质和电容器电介质具有相同成分和相同厚度的情况下，它们通过相同的过程同时形成。在第一介电部件和第二介电部件具有不同成分、不同厚度或者两者的情况下，它们被单独形成。此外，第一和第二FinFET可以被配置用于不同功能。在一个实例中，第一FinFET被配置为I/O器件，并且第二FinFET被配置为核心器件。在进一步的实例中，第一介电部件比第二介电部件更厚。
图6是一个实施例中根据本公开多个方面构造的半导体结构100的部分立体图。图7是沿着虚线EE’的图6的半导体结构的截面图。第一区域108中的106凹陷，并且第一区域108中的相应鳍式有源区104深入延伸至凹槽。具体地，导电部件114覆盖第一区域108中的凹槽并且延伸到第二区域以确保全覆盖。
图8是在另一个实施例中根据本公开多个方面构造的半导体结构130的顶视图。半导体结构130包括配置为阵列的多个单元100。每个单元100都包括图1的半导体结构100。在用于说明的本实例中，半导体结构130包括三列和三行，形成单元100的3X3阵列。根据一个实施例，电容器形成在半导体结构100的凹陷第一区域108中。在该实施例中，作为第一电极的导电部件连接至具有诸如高压的第一电压的第一电源线132。作为第二电极的鳍式有源区连接至具有诸如低压的第二电压的第二电源线134。通过不同布线，各自单元中的电容器可以串联、并联连接或混合连接。
图9和图10是根据多种实施例构造的半导体结构140和146的截面图。图9的半导体结构140类似于图1和图2中的相应截面图的半导体结构100。例如，半导体结构140包括形成在衬底102上的有源区104和STI部件106。衬底102包括第一区域108和第二区域110。第一区域108中的STI部件相对于第二区域110中的STI部件凹陷。介电部件142形成在衬底102上，并且导电部件114形成在介电部件142上。导电部件114覆盖第一区域108，具体地覆盖鳍式有源区之间的间隙内的凹陷STI部件。
在图9的半导体结构140中，导电部件114、介电部件142和鳍式有源区104被配置并耦合以形成FinFET(被称为FinFET 140)。在这种情况下，导电部件114和介电部件142分别用作栅电极和栅极电介质。
图10的半导体结构146类似于图1以及图2所示相应截面图的半导体结构100。例如，半导体结构146包括形成在衬底102上的有源区104和STI部件106。衬底102包括第一区域108和第二区域110。第一区域108中的STI部件相对于第二区域110中的STI部件凹陷。介电部件148形成在衬底102上，并且导电部件114形成在介电部件148上。导电部件114覆盖第一区域108。
在图10的半导体结构146中，导电部件114、介电部件142和鳍式有源区104被配置并耦合以形成另一个FinFET(被称为FinFET 146)。在这种情况下，导电部件114和介电部件148分别用作栅电极和栅极电介质。
在本实施例中，集成电路包括在相同衬底102中形成的FinFET 140和FinFET 146。然而，作为用于FinFET 140的栅极电介质的介电部件142包括第一厚度，并且作为用于FinFET 146的栅极电介质的介电部件148包括大于第一厚度的第二厚度。在一个实例中，FinFET 146被配置为I/O器件，并且FinFET 140被配置为核心器件。
图11是用于制造根据本公开实施例构造的半导体器件的方法200的流程图。半导体器件包括多鳍结构和双深隔离结构。图12至图21是处于多种制造阶段的半导体结构300的实施例的截面图。参考图12至图21共同描述半导体结构300及其制造方法200。提供半导体结构300来用于说明方法200并且其类似于图1的半导体100。因此，为了简单起见，简要描述类似部件。
参考图11和图12，方法200开始于步骤202，提供半导体衬底102。半导体衬底102包括硅。可选地，衬底102包括锗、硅锗或其他合适的半导体材料。
仍然参考图11和图12，方法200进行至步骤204，形成掩膜层301。掩膜层301是具有一种或多种合适介电材料的硬掩膜层。在优选实施例中，掩膜层301包括形成在衬底102上的氧化硅(SiO)层302和形成在氧化硅层302上的氮化硅(SiN)层304。在一个实例中，SiO层214包括范围在约5nm和约15nm之间的厚度。在另一个实例中，SiN层216包括范围在约40nm和约120nm之间的厚度。在另一个实施例中，步骤204包括：通过热氧化形成SiO层302，并且通过化学汽相沉积(CVD)形成SiN层304。例如，SiN层304通过使用包括六氯乙硅烷(HCD或Si2Cl6)、二氯甲硅烷(DCS或SiH2Cl2)、对-(叔丁胺基)硅烷(BTBAS或C8H22N2Si)和乙硅烷(DS或Si2H6)的化学物质的CVD形成。
方法200进行至步骤206，通过包括光刻图案化工艺和蚀刻工艺的过程图案化掩膜层301。在如图12所示的本实施例中，使用光刻工艺在硬掩膜层301上形成图案化的光刻胶层306，光刻工艺包括光刻胶涂布、软烘焙、曝光、曝光后烘焙(PEB)、显影和硬烘焙。
参考图13，通过蚀刻工艺经由图案化的光刻胶层306的开口蚀刻掩膜层301，形成图案化掩膜层301。此后，使用诸如湿式剥离或等离子体灰化的合适工艺去除图案化光刻胶层。在一个实例中，蚀刻工艺包括应用干(或等离子体)蚀刻，以去除图案化光刻胶层306的开口内的掩膜层301。在另一个实例中，蚀刻工艺包括应用等离子体蚀刻，以去除图案化光刻胶层306的开口内的SiN层304，并且通过氢氟酸(HF)溶液应用湿蚀刻，以去除开口内的SiO层302。在另一个实例中，蚀刻工艺包括应用等离子体蚀刻以去除开口内的SiN层304，但是SiO层302在该处理阶段可以保留。此后，图案化光刻胶层306通过诸如剥离或灰化的合适技术被去除。
图案化掩膜层301包括限定鳍式有源区104的多个开口。第一有源区104被配置用于多种器件，诸如FinFET、电容器或两者。在本实施例中，半导体结构300包括第一区域108和第二区域110。在特定实例中，电容器形成在第一区域108中，并且FinFET形成在第二区域110中。在一个实例中，FinFET包括金属氧化物半导体(MOSFET)。
仍然参考图13，方法200进行至步骤208，通过硬掩膜301的开口对衬底102执行蚀刻工艺，在衬底102中形成多种沟槽307。多种鳍式有源区104由蚀刻工艺限定。在一个实施例中，蚀刻工艺实现干蚀刻。例如，蚀刻工艺的蚀刻剂包括等离子体HBr、Cl2、SF6、O2、Ar和He。在另一个实例中，蚀刻剂包括等离子体CF4、C3F8、CHF3、CH2F2或它们的组合。
参考图11和图14，方法200进行至210，在沟槽307中形成一个或多个STI部件308。STI部件308包括在沟槽307中填充的一种或多种介电材料。在一个实施例中，STI部件308的形成包括电介质沉积和抛光。在特定实例中，STI部件308的形成包括通过诸如氧化硅、氮化硅或氮氧化硅的一种或多种介电材料填充沟槽。填充后的沟槽可以具有多层结构，诸如具有填充沟槽的氮化硅的热氧化物衬里层。在一个实施例中，填充多种STI部件包括：生长热氧化物沟槽衬里以改进沟槽界面，使用CVD技术用氧化硅或氮化硅填充沟槽，并且可选地执行热退火。在一个实例中，电介质沉积使用高密度等离子体CVD(HDPCVD)。在另一个实例中，抛光可以使用化学机械抛光(CMP)工艺，以去除硬掩膜上的过多介电材料，并且平坦化半导体结构300的顶面。
参考图11和图15，方法200进行至步骤212，使用光刻工艺在衬底102上形成另一个图案化光刻胶层310。图案化光刻胶层310限定凹陷区域。具体地，图案化光刻胶层310被图案化，以覆盖第二区域110，并且具有开口以暴露作为凹陷区域的第一区域108。
参考图11和图16，方法200进行至步骤214，使用图案化光刻胶层310作为蚀刻掩膜对STI部件308执行蚀刻工艺。蚀刻工艺使用蚀刻剂来选择性地蚀刻STI部件308。从而，第一区域108中的STI部件308被深蚀刻并且相对于第二区域110中的STI部件308凹陷。此后，去除图案化光刻胶层310。
参考图11和图17，方法200进行至步骤216，通过蚀刻工艺去除硬掩膜301。在优选实施例中，硬掩膜301被部分地去除。具体地，去除SiN层304。去除SiN层304的蚀刻工艺使用蚀刻剂，以选择性地去除氮化硅而不蚀刻氧化硅。在一个实例中，该蚀刻工艺中的蚀刻剂包括热磷酸(H3PO4)溶液。
参考图11和图18，方法200可以进行至步骤218，对衬底102执行离子注入工艺312，形成多种阱区，诸如n阱或p阱。在本实例中，氧化硅层302被用作注入阻挡层用于改进注入效果，诸如减少注入沟道效应问题。注入工艺312使用合适的注入物质和合适的剂量。例如，注入物质可以包括用于n阱的磷或用于p阱的硼。
参考图11和图19，方法200可以进行至步骤220，对STI部件308进行另一个蚀刻工艺，以在第一区域108和第二区域110中深蚀刻STI部件308。鳍式有源区104被形成并且从STI部件308突出。在步骤220之后，第一区域108中的STI部件仍然相对于第二区域110中的STI部件凹陷。该步骤中使用的蚀刻剂可以类似于在步骤214的蚀刻工艺中使用的蚀刻剂。
参考图11和图20，方法200可以进行至步骤222，在鳍式有源区104上形成介电层112。介电层112形成在鳍式有源区104的顶面和侧壁上。介电层112可以包括氧化硅、高k介电材料或它们的组合。介电层112可以通过合适的技术来形成，诸如热氧化、原子层沉积(ALD)、金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)或分子束外延(MBE)。在一个实例中，介电层112包括通过应用于包括硅的鳍式有源区104的热氧化所形成的氧化硅。在另一个实例中，使用高k介电材料，并且包括金属氧化物，诸如氧化锆(ZrO2)、氧化铝(Al2O3)或氧化铪(HfO2)。在又一实例中，高k介电材料通过UV-臭氧氧化形成，包括：进行溅射以形成金属膜；以及在存在超紫外线(UV)光的情况下通过O2原位氧化金属膜。在又一实例中，介电层112包括氧化硅膜和高k介电膜。当使用双电介质厚度或双介电材料时，独立地形成具有不同成分和/或不同厚度的电介质厚度。
参考图11和图21，方法200可以进行至步骤224，在介电层112上形成导电层114。导电层114包括多晶硅、金属(诸如铝、铜或钨)、硅化物、具有合适功函数(分别用于n型FET和p型FET)的其他导电材料或它们的组合。导电层114通过诸如PVD的合适技术形成。
仍然参考图11和图21，方法200可以进行至步骤226，图案化导电层114和介电层112以分别形成导电部件和介电部件。导电层114和介电层112的图案化包括一个或多个蚀刻步骤。在一个实例中，在蚀刻工艺期间，在导电层114上形成硬掩膜作为蚀刻掩膜。在另一个实例中，图案化光刻胶层被用作蚀刻掩膜，以图案化导电层114和介电层112。
具体地，导电层114被图案化，使得一个导电部件(并且还有相应的介电部件)覆盖凹陷的第一区域108。在本实例中，第一区域108中的一个导电部件延伸到第二区域110。由于凹陷第一区域108中的鳍式有源区104具有高纵横比并且很难在鳍式有源区104的间隙内完成导电层的蚀刻，所以通过导电层114全覆盖凹陷第一区域避免了对凹陷第一区域108中的导电层的直接蚀刻。
其他工艺步骤可以在方法200之前、期间或之后实现。在一个实施例中，可以实现形成源极和漏极区的另一过程，以形成一个或多个FinFET。在一个实例中，源极和漏极区包括通过多种离子注入工艺形成的轻掺杂漏极(LDD)区和重掺杂源极和漏极(S/D)部件。当半导体结构300包括n型FET(nFET)和p型FET(pFET)时，源极和漏极区使用合适掺杂物质形成，分别用于n型FET和p型FET。作为用于nFET的一个实例，LDD部件通过具有轻掺杂剂量的离子注入形成。此后，隔离结构通过电介质沉积和诸如等离子体蚀刻的各向异性蚀刻形成。然后，重掺杂S/D部件通过具有重掺杂剂量的离子注入形成。pFET的多种源极和漏极部件可以在相似过程中形成但具有相反的掺杂类型。在形成用于nFET和pFET的多种源极和漏极部件的过程的一个实施例中，nFET的LDD部件通过离子注入形成，同时pFET的区域被图案化光刻胶层覆盖；pFET的LDD部件通过离子注入形成，同时nFET的区域被图案化光刻胶层覆盖；然后，通过沉积和蚀刻形成用于nFET栅叠层和pFET栅叠层的隔离结构。nFET的S/D部件通过离子注入形成，同时pFET的区域被另一个图案化光刻胶层覆盖，并且pFET的S/D部件通过离子注入形成，同时nFET的区域被另一个图案化光刻胶层覆盖。在一个实施例中，之后进行高温退火工艺，以激活源极和漏极区中的多种掺杂物。
在另一个实施例中，层间介电(ILD)层形成在半导体衬底102上。ILD层包括氧化硅、低k介电材料、其他合适介电材料或它们的组合。ILD层通过诸如CVD的合适技术形成。例如，可以实施高密度等离子体CVD以形成ILD层。
在其他实施例中，形成多种互连部件以耦合多种器件来形成功能电路。互连部件包括诸如和通孔的垂直互连和诸如金属线的水平互连。多种互连部件可以使用包括铜、钨和硅化物的多种导电材料。在一个实例中，使用镶嵌工艺形成基于铜的多层互连结构。在另一个实施例中，使用钨在接触件孔中形成钨插塞。在另一个实例中，使用硅化物来在源极和漏极区上形成多种接触件，用于减小的接触件电阻。
在又一实施例中，pFET具有用于增强的载流子迁移率和改进的器件性能的应变结构。在进一步实施例中，硅锗(SiGe)形成在pFET的源极和漏极区中，以实现合适的应力效果。在另一个实施例中，nFET具有用于增强的载流子迁移率和改进的器件性能的应变结构。在进一步实施例中，碳化硅(SiC)形成在nFET的源极和漏极区中以实现合适的应力效果。
虽然提供了半导体结构及其制造方法的多种实施例。但是可以在不脱离本公开的范围的情况下，存在其他改变和添加。本公开可以在多种应用中使用。例如，具有FinFET和电容器的半导体结构100可以被用于形成静态随机存取存储器(SRAM)单元。在其他实例中，半导体结构100可以结合在多种集成电路中，诸如逻辑电路、动态随机存取存储器(DRAM)、闪存或成像传感器。
从而，本公开提供了半导体结构的一个实施例，包括：半导体衬底，具有第一区域和第二区域；浅沟槽隔离(STI)部件，形成在半导体衬底中。STI部件包括设置在第一区域中并具有第一厚度T1的第一部分以及设置在第二区域中并具有大于第一深度的第二厚度T2的第二区域，STI部件的第一部分相对于STI部件的第二部分凹陷。半导体结构还包括：位于半导体衬底上的多个鳍式有源区；以及设置在鳍式有源区和STI部件上的多个导电部件，其中，导电部件中的一个覆盖第一区域中的STI部件的第一部分。
在半导体结构的一个实施例中，STI部件的第一部分相对于STI部件的第二部分凹陷，使得第一部分的顶面低于第二部分的顶面(T2-T1)。
在另一个实施例中，半导体结构进一步包括位于导电部件下方并使导电部件与鳍式有源区分离的多个介电部件。
在又一实施例中，半导体结构进一步包括：电容器，设置在第一区域中；以及晶体管，设置在第二区域中。电容器包括一个鳍式有源区、一个导电部件以及使一个导电部件与一个导电部件分离的一个介电层。在一个实例中，电容器是去耦电容器，并且晶体管是场效应晶体管。
在又一实施例中，半导体结构进一步包括设置在第一区域中的第一晶体管，其中，第一晶体管包括第一栅叠层，第一栅叠层具有介电部件中的第一介电部件和位于介电部件中的第一介电部件上方的导电部件中的第一导电部件；以及第二区域中的第二晶体管，其中，第二晶体管包括第二栅叠层，第二栅叠层具有介电部件中的第二介电部件和位于介电部件中的第二介电部件上方的导电部件中的第二导电部件。介电部件中的第一介电部件具有第一厚度，并且介电部件中的第二介电部件具有不同于第一厚度的第二厚度。
在又一实施例中，多个导电部件包括：设置在第一区域中并具有第一宽度的第一导电部件；以及设置在第二区域中并具有小于第一宽度的第二宽度的第二导电部件。
在又一实施例中，多个介电部件包括：第一介电部件，设置在第一区域中、位于第一导电部件下方并具有第一介电材料；以及第二介电部件，设置在第二区域中、位于第二导电部件下方并具有不同于第一介电材料的第二介电材料。
在又一实施例中，第一导电部件、第一介电部件和鳍式有源区的第一子集被配置成形成电容器；以及第二导电部件、第二介电部件以及鳍式有源区的第二子集被配置成形成鳍式场效应晶体管(FinFET)。
本公开还提供了半导体结构的另一个实施例，包括：半导体衬底，具有第一区域和第二区域；鳍式有源区，形成在半导体衬底上并且延伸到第一和第二区域中；浅沟槽隔离(STI)部件，形成在半导体衬底中并且邻近鳍式有源区。STI部件包括设置在第一区域中的第一部分和设置在第二区域中的第二部分，并且STI部件的第一部分具有第一顶面，STI部件的第二部分具有高于第一顶面的第二顶面。半导体结构还包括形成在鳍式有源区和STI部件上的第一导电部件，其中，第一导电部件设置在第一区域中并覆盖STI部件的第一部分；以及在鳍式有源区和STI部件上形成的第二导电部件，其中，第二导电部件设置在第二区域中。
在一个实施例中，半导体结构进一步包括：第一介电部件，与第一导电部件对准并位于第一导电部件下方；以及第二介电部件，与第二导电部件对准并位于第二导电部件下方。
在另一个实施例中，鳍式有源区、第一介电部件和第一导电部件被配置并耦合以形成电容器；以及鳍式有源区、第二介电部件和第二导电部件被配置并耦合以形成场效应晶体管。
在又一实施例中，第一导电部件包括第一宽度；以及第二导电部件包括小于第一宽度的第二宽度。
在又一实施例中，第一介电部件包括第一厚度；以及第二介电部件包括不同于第一厚度的第二厚度。
在又一实施例中，第一介电部件包括第一介电材料；以及第二介电部件包括不同于第一介电材料的第二介电材料。
在又一实施例中，鳍式有源区定向在第一方向上；以及第一和第二导电部件定向在垂直于第一方向的第二方向上。
本公开还提供了方法的一个实施例，包括：蚀刻半导体衬底，以形成多个沟槽并限定多个鳍式有源区；用介电材料填充多个沟槽以形成浅沟槽隔离(STI)部件；使第一区域中的STI部件的第一子集凹陷第一尺寸；使第二区域中的STI部件的第二子集凹陷小于第一尺寸的第二尺寸；以及在STI部件和鳍式有源区上形成导电部件，其中，导电部件覆盖STI部件的第一子集。
在一个实施例中，使第一区域中的STI部件的第一子集凹陷第一尺寸；以及使第二区域中的STI部件的第二子集凹陷包括：在半导体衬底上形成图案化光刻胶层，其中，图案化光刻胶层具有使第一区域暴露的开口并且覆盖第二区域；通过图案化光刻胶层的开口，对第一区域中的STI部件的第一子集执行第一STI蚀刻；去除图案化光刻胶层；以及对第一区域中的STI部件的第一子集和第二区域中的STI部件的第二子集执行第二STI蚀刻，使得STI部件的第一子集相对于STI部件的第二子集凹陷。
在另一个实施例中，该方法进一步包括：在执行第一STI蚀刻之后并且在执行第二STI蚀刻之前，对半导体衬底执行阱注入。
在另一个实施例中，该方法进一步包括：在半导体衬底上沉积硬掩膜层；使用光刻工艺图案化硬掩膜层，其中，蚀刻半导体衬底以形成多个沟槽并限定多个鳍式有源区包括：通过硬掩膜层的开口蚀刻半导体衬底；以及在第一STI蚀刻之后和在执行阱注入之前去除硬掩膜层。
以上概述了多个实施例的特征。本领域技术人员将想到，他们可以容易地使用本公开作为用于设计或修改用于实现与在此介绍的实施例的相同目的和/或实现与其相同优点的其他工艺和结构的基础。本领域技术人员还将认识到，这样的等价结构不脱离本公开的精神和范围，并且他们可以在不脱离本公开的精神和范围的情况下在此作出多种改变、替换和更改。

Claims (10)

1.一种半导体结构，包括：
半导体衬底，具有第一区域和第二区域；
浅沟槽隔离(STI)部件，形成在所述半导体衬底中，其中，所述STI部件包括设置在所述第一区域中并具有第一厚度T1的第一部分和设置在所述第二区域中并具有大于所述第一厚度T1的第二厚度T2的第二部分，所述STI部件的所述第一部分相对于所述STI部件的所述第二部分凹陷；
多个鳍式有源区，位于所述半导体衬底上；以及
多个导电部件，设置在所述鳍式有源区和所述STI部件上，其中，一个导电部件覆盖所述第一区域中的所述STI部件的所述第一部分。
2.根据权利要求1所述的半导体结构，其中，所述STI部件的所述第一部分相对于所述STI部件的所述第二部分凹陷，使得所述第一部分的顶面比所述第二部分的顶面低(T2-T1)。
3.根据权利要求1所述的半导体结构，进一步包括：多个介电部件，位于所述导电部件下方并使所述导电部件与所述鳍式有源区分离。
4.根据权利要求3所述的半导体结构，进一步包括：
电容器，设置在所述第一区域中，所述电容器包括一个鳍式有源区、一个导电部件以及使所述一个导电部件与所述一个鳍式有源区分离的一个介电部件；以及
晶体管，设置在所述第二区域中。
5.根据权利要求4所述的半导体结构，其中，所述电容器是去耦电容器，所述晶体管是场效应晶体管。
6.根据权利要求3所述的半导体结构，进一步包括：
第一晶体管，设置在所述第一区域中，所述第一晶体管包括第一栅叠层，所述第一栅叠层具有所述介电部件中的第一介电部件和覆盖所述介电部件中的所述第一介电部件的所述导电部件中的第一导电部件；以及
第二晶体管，设置在所述第二区域中，所述第二晶体管包括第二栅叠层，所述第二栅叠层具有所述介电部件中的第二介电部件和覆盖所述介电部件中的所述第二介电部件的所述导电部件中的第二导电部件，
其中，所述介电部件中的所述第一介电部件具有第一电介质厚度，所述介电部件中的所述第二介电部件具有不同于所述第一电介质厚度的第二电介质厚度。
7.一种半导体结构，包括：
半导体衬底，具有第一区域和第二区域；
鳍式有源区，形成在所述半导体衬底上并在所述第一区域和所述第二区域中延伸；
浅沟槽隔离(STI)部件，形成在所述半导体衬底中并与所述鳍式有源区相邻，其中，所述STI部件包括：
设置在所述第一区域中的第一部分和设置在所述第二区域中的第
二部分，并且
所述STI部件的所述第一部分具有第一顶面，所述STI部件的所
述第二部分具有高于所述第一顶面的第二顶面；
第一导电部件，形成在所述鳍式有源区和所述STI部件上，其中，所述第一导电部件设置在所述第一区域中并覆盖所述STI部件的所述第一部分；以及
第二导电部件，形成在所述鳍式有源区和所述STI部件上，其中，所述第二导电部件设置在所述第二区域中。
8.根据权利要求7所述的半导体结构，进一步包括：
第一介电部件，与所述第一导电部件对准并位于所述第一导电部件下方；以及
第二介电部件，与所述第二导电部件对准并位于所述第二导电部件下方。
9.一种方法，包括：
蚀刻半导体衬底，以形成多个沟槽并限定多个鳍式有源区；
用介电材料填充所述多个沟槽以形成浅沟槽隔离(STI)部件；
使第一区域中的所述STI部件的第一子集凹陷第一尺寸；
使第二区域中的所述STI部件的第二子集凹陷小于所述第一尺寸的第二尺寸；以及
在所述STI部件和所述鳍式有源区上形成导电部件，其中，所述导电部件覆盖所述STI部件的所述第一子集。
10.根据权利要求9所述的方法，其中，使所述第一区域中的所述STI部件的所述第一子集凹陷所述第一尺寸；以及使所述第二区域中的所述STI部件的所述第二子集凹陷包括：
在所述半导体衬底上形成图案化光刻胶层，所述图案化光刻胶层具有暴露所述第一区域的开口并覆盖所述第二区域；
通过所述图案化光刻胶层的开口对所述第一区域中的STI部件的所述第一子集执行第一STI蚀刻；
去除所述图案化光刻胶层；以及
对所述第一区域中的所述STI部件的所述第一子集和所述第二区域中的所述STI部件的所述第二子集执行第二STI蚀刻，使得所述STI部件的所述第一子集相对于所述STI部件的所述第二子集凹陷。
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