WO2018004672A1

WO2018004672A1 - Thin film resistor with reduced capacitance

Info

Publication number: WO2018004672A1
Application number: PCT/US2016/040786
Authority: WO
Inventors: Chen-Guan LEE; Walid M. Hafez; Joodong Park; Jui-Yen Lin; En-Shao LIU; Hsu-Yu Chang; Neville L. DIAS; Rahul RAMASWAMY
Original assignee: Intel Corporation
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04

Abstract

An embodiment includes an apparatus comprising: a fin coupled to a substrate; a first contact on the fin; a thin film resistor (TFR); and a bottom metallization (M) layer; wherein the TFR is below the bottom M layer and is not located directly over any fin. Other embodiments are described herein.

Description

Thin Film Resistor with Reduced Capacitance

Technical Field

[0001 ] Embodiments of the invention are in the field of semiconductor devices and, in particular, thin film resistors.

Background

[0002] As discussed more fully in U.S. Patent Application Publication No.

2007/0218685 (assigned to Intel Corp. of Santa Clara, California, USA), Metal-oxide- semiconductor (MOS) transistors, such as MOS field effect transistors (MOSFET), are commonly used in the manufacture of integrated circuits. A conventional MOS transistor includes a gate stack formed atop a semiconductor substrate. The gate stack generally consists of a conductive metal or polysilicon layer formed on an insulating oxide layer. The gate stack is flanked by two diffusion regions, also known as a source region and a drain region. The diffusion regions are regions within the semiconductor substrate (possibly located in a fin formed from the substrate) that have been implanted with dopants such as boron, aluminum, phosphorous, arsenic, or antimony. Between the source and drain regions, directly subjacent to the gate stack, is a channel region. Typically, three electrical contacts are made to the MOS transistor. Two contacts are made to the two diffusion regions (i.e., one to the source region and one to the drain region) and one contact is made to the gate stack.

[0003] As discussed more fully in U.S. Patent Application Publication No.

2006/0176145 (assigned to Intel Corp. of Santa Clara, California, USA), transistors such as those described above are included in electronic devices that are

continuously scaled smaller and smaller. This typically means that the electronic components that make up these devices, such as microelectronic packages (which include the aforementioned transistors), must also become smaller in terms of vertical thickness and horizontal area. These microelectronic packages commonly include a die that is coupled to a supporting substrate. One approach to making such packages smaller is to embed passive components such as resistors into metallization (M) layers of the "backend" of a device. One such embedded resistor is a thin-film resistor (TFR), which may be thin and have a thickness of less than or equal to about 1 m. As used herein, a TFR is formed using a thin film deposition process, which may include a vacuum based process such as sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). In addition to freeing up surface space, these TFRs may have the added advantage of better stability and electrical performance (less overshooting, ringing, and crosstalk). Also, a TFR has a benefit of good thickness control as well as better resistance variation compared to other resistor structures that require a recess etch (e.g., polysilicon resistors).

[0004] Including the above mentioned transistors and TFRs in aggressively scaled, reliable, cost effective electronic systems is a continuing challenge for electronic system designers.

Brief Description of the Drawings

[0005] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0006] Figure 1 includes a conventional thin film resistor (TFR) located in a backend of a device.

[0007] Figure 2 includes a conventional polysilicon resister in a temporary gate.

[0008] Figure 3 includes a TFR in an embodiment.

[0009] Figure 4 includes a TFR in an embodiment.

[0010] Figures 5(a)-(h) include a process for forming a TFR in a frontend of a device in an embodiment.

[001 1 ] Figure 6 includes a process in an embodiment.

[0012] Figures 7, 8, and 9 depict systems that include embodiments of TFRs described herein.

Detailed Description

[0013] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown. "An embodiment", "various embodiments" and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.

[0014] As mentioned above, thin film resistors may be included in M layers of the "backend" of the device. Such film resistors may couple to the above mentioned contacts that couple to the gate, source, and/or drain nodes of transistors.

[0015] Regarding the "backend", once semiconductor wafers are prepared, a large number of process steps are still necessary to produce desired semiconductor integrated circuits. In general the steps can be grouped into four areas: Frontend Processing, Backend Processing, Test, and Packaging. Frontend and backend processing are pertinent to embodiments and are therefore described below.

[0016] Frontend processing refers to the initial steps in device fabrication. In this stage the actual semiconductor devices (e.g., transistors) are created. A typical front end (also referred to herein as "frontend") process includes: preparation of the wafer surface (e.g., fin formation), patterning and subsequent implantation of dopants to obtain desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials to isolate neighboring devices.

[0017] Once the semiconductor devices have been created they must be

interconnected to form the desired electrical circuits. This "Back End Processing" (BEOL) of the back end (also referred to herein as "backend") involves depositing various layers of metal (sometimes referred to herein as M layers used to form traces, bit lines, word lines, and the like) and insulating material (sometimes referred to herein as V layers because such layers often include vias) in the desired pattern. Typically the metal layers consist of aluminum, copper, and the like. The insulating material may include SiO2, low-K materials, and the like. The various metal layers are interconnected by etching holes, called "vias", in the insulating material and depositing metal (e.g., Tungsten) in them. Thus, a backend portion may include, for example, 12 metal layers: a bottom metal layer (M0), a top metal layer (M1 1 ), and a plurality of metal layers (M1 , M2, M3, M4, M5, M6, M7, M8, M9, and/or M10) between the bottom and top metal layers. The "bottom metal layer" is so named because the backend portion includes no metal layer between the bottom metal layer and a top of the frontend portion. The "top metal layer" is so named because the backend portion includes no metal layer between the top metal layer and the top of the backend portion. Having 12 metal layers is just an example and backend portions may include more (e.g., 14, 16, 18, 20 or more) or less (e.g., 4, 6, 8) metal layers.

[0018] Figure 1 depicts a conventional TFR in a backend M layer. As mentioned above, a typical location to place a TFR is in between routing layers (i.e., M layers). The contact to the TFR is made with a via.

[0019] In Figure 1 , substrate 101 includes fins 102, 103, 104, 105 for polygate FinFET devices. A FinFET is a transistor built around a thin strip of semiconductor material (referred to as the "fin"). The transistor includes the standard field effect transistor (FET) nodes/components: a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both "sidewalls" of the fin as well as along the top side of the fin. Because the conductive channel essentially resides along the three different outer, planar regions of the fin, such a FinFET is typically referred to as a "tri-gate" FinFET. Other types of FinFETs exist (such as "double-gate" FinFETs in which the conductive channel principally resides only along both sidewalls of the fin and not along the top side of the fin).

[0020] Trench-shaped electrical contacts (TCN) 107, 108 include, for example, electrical connections to diffusion regions (e.g., a source region and a drain region). Contacts 109, 1 10 are also TCNs. Therefore, unlike contacts 107, 108, contacts 109, 1 10 illustrate that not all TCNs comprise diffusion contacts. If there is no diffusion contact (e.g., contacts 109, 1 10), the TCN may be considered a "dummy TCN". A contact for a gate may be referred to as a GCN (not shown in Figure 1 ). TCNs maximize the surface area in contact with, for example, the diffusion regions and therefore reduce electrical resistance relative to conventional round contacts. Interlayer dielectric (ILD) 1 13 and etchstop 106 are also shown in frontend 121 .

[0021 ] In some cases, the frontend may include a local interconnect. Unlike global interconnects that connect separate devices to one another in backend 122 (possibly across several metal layers), local interconnects connect diffusions or gates. For example, a gate or source/drain of a single transistor may be connected to other gates or source/drains by a local interconnect in front end 121. As another example, a gate or TCN of a first transistor may connect to a transistor node of a second transistor by a local interconnect in front end 121. TFR 1 14, in contrast to local interconnects, is not located in the frontend 121 of conventional device 100. Instead, TFR 1 14 is included in backend 122 along with ILD 1 1 1 . Additional ILD 1 1 1 ' is included in metal layer 1 12, which includes interconnects 1 15, 1 16. Via 1 17 connects to TFR 1 14. Via 1 17 is included in additional ILD 1 1 1 ". Vias 1 18, 1 19 couple interconnects (e.g., interconnect lines 1 15, 1 16) from layer 1 12 to frontend 121.

[0022] While Figure 1 addresses a conventional TFR in a backend, Figure 2 depicts a conventional polysilicon resistor (although not a TFR) in a frontend.

Specifically, Figure 2 addresses a polysilicon resistor located within a "dummy gate", which is described below. [0023] As noted in Patent Application Publication Number WO2014046755

(assigned to Intel Corp., Santa Clara, CA, USA) gate electrodes were initially formed from metal (e.g., aluminum). However, for many technology nodes, a MOSFET had included a gate electrode that was fabricated from polysilicon so as to permit ion implantation (e.g., to customize doping to N- or P-type in the same circuit) and silicidation (to reduce contact resistance). Consequently, a resistor associated with the MOSFET in a circuit was also fabricated with polysilicon. A so-called "gate-first" process sequence was universally practiced so as to permit blanket deposition of the polysilicon, plasma etch-defined gate lengths, lightly- doped tip regions, dielectric sidewall spacers, and self-aligned source/drain (i.e., to the gate electrode).

[0024] As dimensions of the MOSFET continued to be scaled down, polysilicon depletion became an increasingly severe problem. As a result, gate electrodes started being formed from metal again. However, gate electrodes are typically no longer formed strictly from aluminum. In order to achieve desired work functions, the gate electrodes are now usually formed from a transition metal, an alloy of transition metals, or a transition metal nitride. However, adoption of the metal gate also provided advantages to an alternative so-called "gate-last" process. One

implementation of the gate-last process involved a so-called "replacement gate" process which allowed use of different metals for the N-FET and P-FET in the circuit. When the material in the gate electrode was changed from polysilicon back to metal, the material in the resistor was also changed from polysilicon back to metal.

[0025] Unfortunately, metal resistors often suffer from high process variability and a poor temperature coefficient. Thus, it would be desirable to form the resistor with polysilicon again. However, such a change causes many challenges in process integration particularly for non-planar architectures such as trigate process

architectures.

[0026] With the above description regarding replacement gates that take the place of dummy gates, attention again turns to Figure 2. Figure 2 includes polysilicon resistors 203 located within an area of substrate 201 that is formed from a dummy gate for a gate last process. Polysilicon resistors 203 are formed on oxide 202 and couple to resistor contact nodes 204 (and another resistor contact not shown).

Elements 205, 206 (which are covered by hard mask 207) are dummy gates.

[0027] Polysilicon resistors have superior temperature coefficients as compared to conventional metal resistors. However, polysilicon resistors 203 within polysilicon dummy gates (which serve as resistor bodies) have a variation penalty due to the variation induced by polysilicon recess etch. In other words, resistors 203 are etched but their polysilicon sometimes etches unevenly leading to inconsistence resistance performance. In addition, the capacitance coupling between resistors 203 and substrate 201 can be substantial (which can have adverse resistance-capacitance (RC) performance on neighboring transistors).

[0028] Figure 3 includes a TFR in an embodiment. TFR 304 is embedded in or located on isolation material 302 (sometimes referred to as gate isolation or fin isolation material). The resistor material is metal in some embodiments but polysilicon in other embodiments depending on desired resistor properties. The resistor material may be treated (e.g., doping the polysilicon) to alter resistor properties. The main body of TFR 303 may have any number of heights such as below the tops of fins 31 1 , 312, 313, 314, even with the tops of fins 31 1 , 312, 313, 314, or above the tops of fins 31 1 , 312, 313, 314. Figure 3 shows main body of TFR 303 with a height 315 just above the tops of fins 31 1 , 312, 313, 314. This variability of height 315 is possible because TFR 303 is no longer tied to the location of the dummy gate floor (e.g., see Figure 2), which is not a height that is easily varied. Further, because the resistor body 303 may be raised above the fin isolation 302 at varying heights (depending on thickness of isolation material 302) the resistor 303/substrate 301 capacitance coupling may be managed according to design requirements.

[0029] Further, due to variability of height 315 the embodiment of Figure 3 enables robust contact formation. In other words, resistor contact 306 may be formed with the same material as (and during the same step as) source and drain contact (TCN) formation. For instance, to form a good TCN contact the TCN etch on the

source/drain region (not shown in Figure 3) needs to aggressive enough to touch the top of the fin (height of 316). If height 315 were below height 316, contact on the TFR is not guaranteed. For example, if height 315 is significantly below height 316 a TCN contact etch may be sufficient to reach diffusion areas on the fins (and have good contact resistance to the source and drain nodes) while not being deep enough to reach the TFR, resulting in open circuit.

[0030] Figure 3 addresses other components of apparatus 300, some of which are addressed further below with regard to Figures 5(a)-(h). Those components include dielectric 305, gate insulation layer 303 (e.g., gate insulation), insulation layer 310 (e.g., dummy oxide from replace gate process), hard mask 308, and insulation plug 312 (e.g., nitride, carbide, oxide).

[0031 ] Figure 4 includes an embodiment of a TFR arrangement. TFR 404 is located adjacent fins 41 1 , 412, 413, 414 but not on those fins and not included in temporary gates located on those fins. TFR 404 and gates 407, 409 all intersect axis 424. TFR 404 and gates 421 , 422 all intersect axis 425. In an embodiment contacts 407, 409, 420, 422, 421 , 423 are gate contacts (TCNs for S/D nodes are not shown). With TFR 404 being free from having to be included in a temporary gate, TFR 404 is free to be as long or short in direction 426 and/or direction 427 as needed. Further, TFR 404 may not align with an axis going through a contact if the TFR is too high or too low, in which case the TFR may intersect the same plane as the contacts in an embodiment (i.e., replace axis 424 with vertical plane 424).

[0032] In an embodiment, contacts for the TFR may be linear and have a major or long axis (similar to any of contacts 407, 409, 420, 422, 421 , 423) wherein current flows in the same direction as the long axis. In an embodiment, the long axis of the TFR contacts may be parallel to the long axis of contacts 407, 409, 420, 422, 421 , 423 (so current in TFR contacts runs parallel to current in contacts 407, 409, 420, 422, 421 , 423 and current in the TFR between the contacts runs parallel to current in the fins). In an embodiment, the long axis of the TFR contacts may be non-parallel to the long axis of contacts 407, 409, 420, 422, 421 , 423 (so current in TFR contacts runs non-parallel to current in contacts 407, 409, 420, 422, 421 , 423 and current in the TFR between the contacts runs non-parallel to current in the fins). In an embodiment, the long axis of the TFR contacts may be orthogonal to the long axis of contacts 407, 409, 420, 422, 421 , 423 (so current in TFR contacts runs orthogonal to current in contacts 407, 409, 420, 422, 421 , 423 and current in the TFR between the contacts runs orthogonal to current in the fins).

[0033] Figures 5(a)-(h) include a process flow for building a TFR based

embodiment. This process uses a standard gate-last flow but other embodiments are not so limited. Figures 5(a)-(h) are the cross-sectional view take along axis 524 of Figure 4.

[0034] An embodiment process begins with fin formation (fins 51 1 , 512, 513, 514) on substrate 501 and substrate isolation material 502 (e.g., oxide, nitride, carbide) deposition on substrate 501 (Figure 5(a)). Isolation material 502 is planarized to level 515. Level of planarization 515 determines the distance between the resistor and the substrate (see Figure 5(d)) and therefore determines substrate/TFR capacitance coupling.

[0035] In Figure 5(b), the resistor area (width 527 is shown but depth analogous to dimension 426 of Figure 4 is not shown) is patterned before the fin recess-etch. In Figure 5(b) the resistor region is blocked from the recess etch by photoresist 528 to thereby keep the full isolation thickness 515. The resistor area helps determine resistance for the resistor.

[0036] In Figure 5(c), dummy oxide 510 and dummy polysilicon 529 for the gate are formed (along with hard mask 508). In the resistor region 530 there is no dummy polysilicon formation. Gate spacer 503 (Figure 5(d)) and source/drain epi are later formed (not shown in the figure). In Figure 5(d), resistor material 504 is deposited. The resistor material may be polysilicon and/or other materials with desired resistor properties, including metals and compound materials. In Figure 5(e) isolation material 505 is deposited and planarized. At this step, the source/drain region are also filled with isolation material 505. In Figure 5(f), the gate-to-gate region is patterned and back filled with plug material 521 . Also in Figure 5(f) the resistor material 504 on the sidewall 531 is recessed. In Figure 5(g), the dummy polysilicon in the gate is replaced with work function metals to form gate contacts 507, 509. Then contact 506 for resistor 504 is formed as well as contacts for source/drain nodes (not shown in Figure 5H) are formed. [0037] Figure 6 includes method 600 for creating a TFR based embodiment. Block 601 includes forming a fin on a substrate and forming an insulative layer on the fin and the substrate. Block 602 includes removing a first portion of the insulative layer. Block 603 includes determining a desired capacitance between the TFR and the substrate and/or determining a desired resistance for the TFR. Block 604 includes maintaining a second portion of the insulative layer based on determining the desired capacitance and/or determining the desired resistance. For example, the area under resist 528 in Figure 5(b) is maintained. That is not to say the maintained portion (which appears as an insulative layer (e.g., oxide, nitride, carbide) in Figure 5(b)) is not recessed or lessened in some way. This just to say at least a portion is maintained. The maintained portion forms island 589 in Figure 5(c).

[0038] Block 605 includes forming a temporary gate. Block 606 includes forming a thin film resistor (TFR) layer on the maintained second portion of the insulative layer. Block 607 includes forming a first contact on the fin and a second contact on the TFR. Block 608 includes forming a bottom metallization (M) layer over the TFR (i.e., TFR is in the front end).

[0039] Please note the determination or determinations of block 603 may include only one or both of the determinations. If a high resistance is desired then the TFR shape (which is determined based on the maintained portion) may be narrowed or lengthened and the like. Further, height 315 (which is influenced by the island 589 of Figure 5(c)) helps determine TFR/substrate capacitance (where capacitance may decrease as height 315 increases). Whether these determinations occurred may be inferred as part of a typical process in circuit design whereby the characteristics of a component (e.g., resistance for a resistor) are determined in order to make circuit perform as desired.

[0040] Various embodiments are described herein. TFRs addressed have controllable substrate capacitance coupling (e.g., capacitance between TFR 304 and substrate 301 in Figure 3) by optimizing height 315. Such embodiments can include TFRs including polysilicon for temperature coefficient benefits. Compared to conventional polysilicon resistors (e.g., Figure 2), the deposition of the polysilicon resistor body (e.g., TFR 314) is independent from the replacement-gate process and no recess etch is required (i.e., the polysilicon with in a replacement gate area is conventional etched unevenly resulting in non-optimal resistance and/or capacitance properties). Thus, the proposed embodiments have more consistent electrical properties and design freedom (i.e., does not need to be formed within a dummy gate) compared to conventional systems.

[0041 ] Insulation layers (sometimes referred to as isolation layers or interlayer dielectric layers) (e.g., layers 302, 303, 305, and/or 310) may be formed from materials such as silicon dioxide, silicon nitride, carbides, organic polymers such as perfluorocyclobutane and polytetrafluoroethylene, organosilicate glass, fluorosilicate glass (FSG), organosilicates such as silsesquioxane, siloxane, and the like.

[0042] Metallization processes such as CVD, plasma enhanced chemical vapor deposition (PECVD), PVD, sputter deposition, ALD, electroplating, electroless plating, or a combination of any of these processes, may be used to deposit one or more layers of metal in contacts 307, 309, 306. Metals that may be used for the metallization of contacts 307, 309, 306 include, but are not limited to, copper, ruthenium, palladium, platinum, cobalt, nickel, ruthenium oxide, tungsten, aluminum, titanium, tantalum, titanium nitride, tantalum nitride, hafnium, zirconium, a metal carbide, a conductive metal oxide, or combinations of the above. The metal layer that forms contacts 307, 309, 306 may consist of multiple layers of metals. For instance, in one implementation, a first metal layer may consist of a seed layer, such as a copper seed layer or a noble metal catalyst layer, and a second metal layer may consist of a bulk metal layer such as copper. In further implementations, the various metal layers may provide various functionality, such as barrier layers, adhesion layers, and capping layers.

[0043] Various embodiments include a semiconductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material. [0044] Referring now to Figure 7, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other internet of things (loT) device. A

baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.

[0045] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 and a system memory, namely a DRAM 935. In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0046] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations. Such an input device may use a TFR

embodiment described herein.

[0047] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

[0048] A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0049] To enable communications to be transmitted and received such as in one or more loT networks, various circuitry may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 (which may also use TFRs described herein) and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless

communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.1 1 standard can also be realized.

[0050] Referring now to Figure 8, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to- point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, loT network onboarding or so forth.

[0051 ] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098.

[0052] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 (which may use a TFR embodiment described herein) may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device. As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.

[0053] Embodiments may be used in environments where loT devices may include wearable devices or other small form factor loT devices. Referring now to Figure 9, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a TEE as described herein. Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340. In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or loT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

[0054] Components such as the above mentioned transceivers, processors, user interfaces, memories and the like may rely lightly or heavily on TFR embodiments described herein.

[0055] The following examples pertain to further embodiments.

[0056] Example 1 includes an apparatus comprising: a fin coupled to a substrate; a first contact on the fin; a thin film resistor (TFR); and a bottom metallization (M) layer; wherein the TFR is below the bottom M layer and is not located directly over any fin.

[0057] For instance, in Figure 4 TFR 404 is not located directly over any fin.

[0058] Example 2 includes the apparatus of example 1 wherein: the TFR includes a bottom TFR surface generally parallel to a long axis of the substrate; and a first height between a top of the fin and the substrate is no greater than a second height between the TFR surface and the substrate.

[0059] For instance, see surface 385, long axis 384 for substrate 301 , and heights 315, 316. [0060] Example 3 includes the apparatus of example 2 wherein the first height is less than the second height.

[0061 ] For instance, see Figure 3.

[0062] Example 4 includes the apparatus of example 1 comprising a monolithic dielectric layer including a first portion immediately adjacent the fin and second portion directly beneath the TFR, wherein a first height between a top of the first portion and the substrate is less than a second height between a top the second portion and the substrate.

[0063] For instance, see material 302 and portions 382, 383 as well as heights 380, 381.

[0064] Example 5 includes the apparatus of example 2 comprising a first vertical plane, orthogonal to the fin, which intersects the first contact and the TFR.

[0065] For instance, see vertical plane (coming out of the page) defined by axis 424.

[0066] Example 6 includes the apparatus of example 5 comprising: a second contact on the fin; and a second vertical plane, orthogonal to the fin, which intersects the second contact and the TFR.

[0067] For instance, see vertical planes (coming out of page) defined by axes 424, 425.

[0068] Example 7 includes the apparatus of example 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and unequal to the first width.

[0069] For instance, see widths 485, 426.

[0070] Example 8 includes the apparatus of example 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and greater than the first width. [0071 ] Example 9 includes the apparatus of example 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is orthogonal to the first width and unequal to the first width.

[0072] For instance, see widths 485, 427.

[0073] Example 10 includes the apparatus of example 1 comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts.

[0074] For instance, see axis 386 and contacts 307, 306.

[0075] Example 1 1 includes the apparatus of example 10, wherein the first contact includes a material and the second contact also includes the material.

[0076] For instance, both may include polysilicon and/or a metal. The first contact may include a TCN for a S/D node. In another embodiment the first contact may be a gate contact.

[0077] Example 12 includes the apparatus of example 10, wherein the second contact includes at least one of a metal and polysilicon.

[0078] Example 13 includes the apparatus of example 1 comprising a second contact on the TFR, wherein the first contact includes a gate contact having a first material and the second contact includes a second material unequal to the first material.

[0079] For example, the gate contact may include a metal (e.g., a metal alloy) and the resistor may include polysilicon.

[0080] Example 14 includes the apparatus of example 1 comprising a second contact on the TFR, wherein the first contact includes a gate contact comprising a metal and the second contact includes polysilicon.

[0081 ] Example 15 includes the apparatus of example 1 , wherein: the TFR includes a top TFR surface generally parallel to a long axis of the substrate; the top TFR surface is un-etched; there are no other M layers between the fin and the bottom M layer; and the TFR has a thickness, measured orthogonal to a long axis of the substrate, that is less than 1 micron.

[0082] Thus, an unetched TFR (formed by film deposition) differs from a polysilicon resistor etched within a dummy gate.

[0083] Example 16 includes the apparatus of example 1 comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts but not the fin.

[0084] For instance, see axis 386 and contacts 307, 306.

[0085] Example 17 includes a method comprising: forming a fin on a substrate; forming an insulative layer on the fin and the substrate; removing a first portion of the insulative layer and maintaining a second portion of the insulative layer; forming a temporary gate; forming a thin film resistor (TFR) layer on the maintained second portion; and forming a first contact on the fin and a second contact on the TFR.

[0086] Example 18 includes the method of example 17 comprising: determining a desired capacitance between the TFR and the substrate; and maintaining the second portion of the insulative layer based on determining the desired capacitance.

[0087] Example 19 includes the method of example 18 comprising: determining a desired resistance for the TFR; and maintaining the second portion of the insulative layer based on determining the desired resistance.

[0088] Example 20 includes the method of example 18 comprising forming a bottom metallization (M) layer; wherein the TFR is below the bottom M layer and is not located directly over any fin.

[0089] Example 1 a includes an apparatus comprising: a fin coupled to a substrate; a first contact on the fin; a thin film resistor (TFR); and a bottom metallization (M) layer including an interconnect line located in a trench; wherein the TFR is between the bottom M layer and the substrate and is not located directly on any fin.

[0090] For instance, the bottom layer including a trench having an interconnect line would not include a layer simply having a via or a contact for a transistor node. In an embodiment, the interconnect line is formed using damascene or dual damascene techniques.

[0091 ] Example 2a includes the apparatus of example 1 a wherein: the TFR includes a bottom TFR surface generally parallel to a long axis of the substrate; and a first height between a top of the fin and the substrate is no greater than a second height between the TFR surface and the substrate.

[0092] Example 3a includes the apparatus of example 2a wherein the first height is less than the second height.

[0093] Example 4a includes the apparatus of example 1 a comprising a monolithic dielectric layer including a first portion immediately adjacent the fin and second portion directly between the TFR and the substrate, wherein a first height between a top of the first portion and the substrate is less than a second height between a top the second portion and the substrate.

[0094] Example 5a includes the apparatus of example 2a comprising a first vertical plane, orthogonal to the fin, which intersects the first contact and the TFR.

[0095] Example 6a includes the apparatus of example 5a comprising: a second contact on the fin; and a second vertical plane, orthogonal to the fin, which intersects the second contact and the TFR.

[0096] Example 7a includes the apparatus of example 1 a, wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and unequal to the first width.

[0097] Example 8a includes the apparatus of example 1 a, wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and greater than the first width.

[0098] Example 9a includes the apparatus of example 1 a, wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is orthogonal to the first width and unequal to the first width.

[0099] Example 10a includes the apparatus of example 1 a comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts.

[0100] Example 1 1 a includes the apparatus of example 10a, wherein the first contact includes a material and the second contact also includes the material.

[0101 ] Example 12a includes the apparatus of example 10a, wherein the second contact includes at least one of a metal and polysilicon.

[0102] Example 13a includes the apparatus of example 1 a comprising a second contact on the TFR, wherein the first contact includes a gate contact having a first material and the second contact includes a second material unequal to the first material.

[0103] Example 14a includes the apparatus of example 1 a comprising a second contact on the TFR, wherein the first contact includes a gate contact comprising a metal and the second contact includes polysilicon.

[0104] Example 15a includes the apparatus of example 1 a, wherein: the TFR includes a TFR surface generally parallel to a long axis of the substrate, the TFR being between the TFR surface and the substrate; the TFR surface is un-etched; there are no other M layers between the fin and the bottom M layer; and the TFR has a thickness, measured orthogonal to a long axis of the substrate, which is less than 1 micron.

[0105] Example 16a includes the apparatus of example 1 a comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts but not the fin.

[0106] Example 17a includes a method comprising: forming a fin on a substrate; forming an insulative layer on the fin and the substrate; removing a first portion of the insulative layer and maintaining a second portion of the insulative layer; forming a temporary gate; forming a thin film resistor (TFR) layer on the maintained second portion; and forming a first contact on the fin and a second contact on the TFR.

[0107] Example 18a includes the method of example 17a comprising: determining a desired capacitance between the TFR and the substrate; and maintaining the second portion of the insulative layer based on determining the desired capacitance.

[0108] Example 19a includes the method of example 18a comprising: determining a desired resistance for the TFR; and maintaining the second portion of the insulative layer based on determining the desired resistance.

[0109] Example 20a includes the method of example 18a comprising forming a bottom metallization (M) layer including an interconnect line located in a trench; wherein the TFR is between the bottom M layer and the substrate and is not located directly on any fin.

[01 10] Example 21 a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory include the TFR according to any one of examples 1 a to 16a.

[01 1 1 ] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is: 1 . An apparatus comprising:

a fin coupled to a substrate;

a first contact on the fin;

a thin film resistor (TFR); and

a bottom metallization (M) layer including an interconnect line located in a trench;

wherein the TFR is between the bottom M layer and the substrate and is not located directly on any fin.

2. The apparatus of claim 1 wherein:

the TFR includes a bottom TFR surface generally parallel to a long axis of the substrate; and

a first height between a top of the fin and the substrate is no greater than a second height between the TFR surface and the substrate.

3. The apparatus of claim 2 wherein the first height is less than the second height.

4. The apparatus of claim 1 comprising a monolithic dielectric layer including a first portion immediately adjacent the fin and second portion directly between the TFR and the substrate, wherein a first height between a top of the first portion and the substrate is less than a second height between a top the second portion and the substrate.

5. The apparatus of claim 2 comprising a first vertical plane, orthogonal to the fin, which intersects the first contact and the TFR.

6. The apparatus of claim 5 comprising:

a second contact on the fin; and

a second vertical plane, orthogonal to the fin, which intersects the second contact and the TFR.

7. The apparatus of claim 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and unequal to the first width.

8. The apparatus of claim 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is parallel to the first width and greater than the first width.

9. The apparatus of claim 1 , wherein the first contact includes a gate contact having a first width parallel to a long axis of the fin and the TFR has a second width that is orthogonal to the first width and unequal to the first width.

10. The apparatus of claim 1 comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts.

1 1 . The apparatus of claim 10, wherein the first contact includes a material and the second contact also includes the material.

12. The apparatus of claim 10, wherein the second contact includes at least one of a metal and polysilicon.

13. The apparatus of claim 1 comprising a second contact on the TFR, wherein the first contact includes a gate contact having a first material and the second contact includes a second material unequal to the first material.

14. The apparatus of claim 1 comprising a second contact on the TFR, wherein the first contact includes a gate contact comprising a metal and the second contact includes polysilicon.

15. The apparatus of claim 1 , wherein:

the TFR includes a TFR surface generally parallel to a long axis of the substrate, the TFR being between the TFR surface and the substrate;

the TFR surface is un-etched;

there are no other M layers between the fin and the bottom M layer; and the TFR has a thickness, measured orthogonal to a long axis of the substrate, which is less than 1 micron.

16. The apparatus of claim 1 comprising a second contact on the TFR, wherein a horizontal axis intersects the first and second contacts but not the fin.

17. A method comprising:

forming a fin on a substrate;

forming an insulative layer on the fin and the substrate;

removing a first portion of the insulative layer and maintaining a second portion of the insulative layer;

forming a temporary gate;

forming a thin film resistor (TFR) layer on the maintained second portion; and forming a first contact on the fin and a second contact on the TFR.

18. The method of claim 17 comprising:

determining a desired capacitance between the TFR and the substrate; and maintaining the second portion of the insulative layer based on determining the desired capacitance.

19. The method of claim 18 comprising:

determining a desired resistance for the TFR; and

maintaining the second portion of the insulative layer based on determining the desired resistance.

20. The method of claim 18 comprising forming a bottom metallization (M) layer including an interconnect line located in a trench; wherein the TFR is between the bottom M layer and the substrate and is not located directly on any fin.

21 . A system comprising:

a memory; and

a processor coupled to the memory,

wherein at least one of the processor and the memory include the TFR according to any one of claims 1 to 16.