WO2019009872A1 - Self-aligned back-gate top-contact thin-film transistor - Google Patents

Self-aligned back-gate top-contact thin-film transistor Download PDF

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Publication number
WO2019009872A1
WO2019009872A1 PCT/US2017/040551 US2017040551W WO2019009872A1 WO 2019009872 A1 WO2019009872 A1 WO 2019009872A1 US 2017040551 W US2017040551 W US 2017040551W WO 2019009872 A1 WO2019009872 A1 WO 2019009872A1
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WIPO (PCT)
Prior art keywords
tft
forming
layer
backbone
hardmask
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PCT/US2017/040551
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French (fr)
Inventor
Kevin Lin
Van Le
Abhishek Sharma
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Intel Corporation
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Priority to PCT/US2017/040551 priority Critical patent/WO2019009872A1/en
Publication of WO2019009872A1 publication Critical patent/WO2019009872A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • Embodiments of the invention are in the field of semiconductor processing and, in particular, thin-film transistors and methods of forming such devices with self-aligned electrodes.
  • TFTs thin- film transistors
  • a TFT 100 includes a gate electrodel70 that is separated from an active region 120 by a gate dielectric layer 150.
  • the gate electrode 170 may be connected to an interconnect line 190 by a via 180.
  • a source electrode 141 and a drain electrode 142 may be formed in direct contact with the active region 120.
  • the components of the TFT are typically fabricated in layers of interlay er dielectric (ILD) material 110.
  • ILD interlay er dielectric
  • the source electrode 141 and the drain electrode 142 are not properly aligned over the active region 120.
  • sidewall 146 of the source electrode 141 is not coplanar with a sidewall 119 of the active region 120.
  • TFTs that are currently available may not have aligned sidewalls because the source electrodes and drain electrodes are typically patterned with a subtractive patterning process that requires a mask to etch the source and drain electrodes. Accordingly, the alignment of the source and drain electrodes is dependent on the alignment of a mask. Furthermore, any misalignment between the source/drain and the active region results in higher contact resistances. As such, misalignment results in a decrease in the performance of the TFT.
  • FIG. 1 is a cross-sectional illustration of a thin-film transistor (TFT) that is formed with misaligned source and drain electrodes.
  • TFT thin-film transistor
  • FIG. 2 is a cross-sectional illustration of a TFT that is formed with self-aligned source and drain electrodes, according to an embodiment of the invention.
  • Figures 3A - 3B are cross-sectional illustrations of an incoming film stack that will be fabricated into a TFT, according to an embodiment of the invention.
  • Figures 4A - 4B are cross-sectional illustrations of the film stack in Figure 3A after trenches are etched into the stack, according to an embodiment of the invention.
  • Figure 5A - 5B are cross-sectional illustrations of the film stack after an interlayer dielectric is blanket deposited, according to an embodiment of the invention.
  • Figures 6A - 6B are cross-sectional illustrations of the film stack after a first backbone hardmask with sidewall spacers is formed over the film stack, according to an embodiment of the invention.
  • Figures 7A - 7B are cross-sectional illustrations of the film stack after etching trenches into the stack while using the hardmask and spacers as an etching mask, according to an embodiment of the invention.
  • Figures 8A - 8B are cross-sectional illustrations of the film stack after the trenches are filled with an ILD and a second backbone hardmask is deposited over the ILD, according to an embodiment of the invention.
  • Figures 9A - 9B are cross-sectional illustrations of the film stack after a lithographic mask for a source/drain plug has been formed, according to an embodiment of the invention.
  • Figures 10A - 10B are cross-sectional illustrations of the film stack after the spacers are removed, and the underlying ILD is etched using the first and second backbones as an etch mask, according to an embodiment of the invention.
  • Figures 11A -11B are cross-sectional illustrations of the film stack after the source electrodes and the drain electrodes have been formed, according to an embodiment of the invention.
  • Figure 12 is an interposer implementing one or more embodiments of the invention.
  • Figure 13 is a computing device built in accordance with an embodiment of the invention.
  • TFTs thin-film transistors
  • methods of forming such devices so that the source electrode and drain electrode are self-aligned with the TFT semiconductor layer.
  • TFTs thin-film transistors
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • embodiments of the invention include processing operations that allow for the source electrode and the drain electrode to be self-aligned with the TFT semiconductor layer.
  • the self-alignment is provided by the use of a backbone hardmask with spacers, as will be described in greater detail.
  • FIG. 2 a cross-sectional illustration of a TFT 200 is shown, according to an embodiment of the invention.
  • the TFT 200 is substantially similar to the TFT 100 described above with respect to Figure 1, with the exception that the source electrode 241 and the drain electrode 242 are self-aligned to the TFT semiconductor layer 220.
  • the self-aligned nature may be seen by comparing the position of the sidewalls of the source and drain electrodes to a sidewall of the TFT semiconductor layer 220.
  • a sidewall 246 of the source electrode 241 is substantially coplanar with a sidewall 219 of the TFT
  • the contact resistance is reduced because the source electrode 241 and the drain electrode 242 have bottom surfaces that are entirely in contact with the TFT semiconductor layer 220. Furthermore, it is to be appreciated that the dimensions of the source electrodes 341 and the drain electrodes 342 will have substantially similar dimensions, since their shape is defined by the shape of the spacers.
  • FIGS. 3A-11B a series of cross-sectional illustrations are shown that illustrate a process for forming a TFT with self-aligned source electrodes and drain electrodes, according to an embodiment of the invention.
  • the figures provide cross-sectional illustrations along two different views of the TFT at different points along the process.
  • the "A” figures e.g., 3A, 4A, 5A, etc.
  • the "B” figures e.g., 3B, 4B, 5B, etc.
  • the TFT stack may include an interlay er dielectric (ILD) 310 on which the other layers are patterned and/or otherwise formed.
  • the ILD 310 may be a first layer of ILD formed on a support substrate (not shown), or it may be any subsequent ILD in a stack-up of multiple ILDs.
  • the ILD 310 may be any suitable low-k dielectric material.
  • low-k dielectric materials may include, but are not limited to, silicon dioxide (S1O 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD material may include pores or air gaps to further reduce their dielectric constant.
  • an interconnect line 390 may be formed at the bottom of the TFT stack.
  • the interconnect line 390 may be any suitable conductive material.
  • the interconnect line 390 may be copper.
  • the interconnect line 390 may be electrically coupled to the gate electrode 370 by a via 380 that passes through the ILD 310.
  • the via 380 may be any suitable conductive material.
  • the vias 380 may be a workfunction metal, such as TaN.
  • the gate electrode 370 may be any suitable conductive material.
  • the gate electrode 370 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.
  • metals that may be used for the gate electrode 370 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • the gate electrode may be deposited with any suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputtering, or the like.
  • a gate dielectric layer 350 may be formed over the gate electrode 370.
  • the gate dielectric layer 350 may be any suitable high-K dielectric material.
  • the gate dielectric layer 350 may include one layer or a stack of layers.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • the gate dielectric layer 350 may be blanket deposited over the gate electrode 350.
  • the gate dielectric layer may be deposited with CVD, PECVD, or the like.
  • a TFT semiconductor layer 320 may be formed over the surface of the gate dielectric layer 350.
  • the TFT semiconductor layer may be any suitable semiconductor material used for thin film transistors.
  • the TFT semiconductor layer 320 may include one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
  • the TFT semiconductor layer 320 is deposited to a thickness between approximately 5 nm and approximately 50 nm. However, it is to be appreciated that the thickness may also be less than 5 nm or greater than 50 nm according to different embodiments of the invention.
  • the trenches 366 may be patterned with any suitable etching process.
  • the trenches 366 may be patterned with typical wet and/or dry etching processes.
  • the trenches 366 are only shown in Figure 4B, since the trenches 366 are out of the plane illustrated in Figure 4 A. While the trenches 366 are formed in the orthogonal plane in Figure 4B, it is to be appreciated that alternative embodiments may include forming the trenches 366 in the plane illustrated in Figure 4A instead.
  • the ILD 316 completely fills the trenches 366 and covers a top surface of the TFT semiconductor layer 320.
  • the ILD 316 may be any suitable low-k dielectric material, such as those described above.
  • the ILD 316 may be the same material as ILD 310. In an alternative embodiment, ILD 316 may be a different material than ILD 310.
  • an etch stop layer 388 may be formed over the top surface of ILD 316.
  • the etch stop layer 388 may be any suitable hardmask material, such as SiN, or the like.
  • the backbone hardmask 392 may be formed.
  • the backbone hardmask 392 may be formed by depositing the blanket depositing the backbone material and patterning the layer with typical patterning processes.
  • spacers 393 may be formed along the sidewalls of the backbone hardmask 392.
  • the spacers 393 may be formed with a material that is etch selective to the material used to form the backbone hardmask 392. Accordingly, either the spacers 393 or the backbone hardmask 392 may be preferentially removed with an etching process in subsequent processing operations.
  • the spacers 393 may be formed with standard processes known in the art. For example, a conformal layer of the spacer material may be deposited over the structure. Thereafter a spacer etch may be implemented to preferentially remove the spacer material along planar surfaces.
  • a cap layer 394 may be formed over a top surface of the backbone hardmask 392 and the spacers 393.
  • the cap layer 394 may be used to protect the backbone hardmask 392 and the spacers 393 from subsequent etching operations.
  • the cap layer 394 may be any suitable mask layer, such TiN.
  • trenches 395 are formed using the backbone hardmask 392 and the spacers 393 as a mask.
  • the trenches 395 define the shape and dimensions of the gate electrode 370, the gate dielectric 350, and the TFT semiconductor layer 320.
  • the trenches 395 define the sidewalls of the TFT semiconductor layer 320 that will subsequently be aligned to the sidewalls of the source and drain electrodes.
  • the trenches 395 are only shown in Figure 7A, since the trenches 395 are out of the plane illustrated in Figure 7B. While the trenches 395 are formed in the plane in Figure 7A, it is to be appreciated that alternative embodiments may include forming the trenches 395 in the plane illustrated in Figure 7B instead.
  • FIGS 8A and 8B cross-sectional illustrations of the device after an additional ILD layer 317 has been deposited into the trenches 395, and a second backbone hardmask 396 is formed between the spacers 393 are shown, according to an embodiment of the invention.
  • the device may be planarized with a polishing process.
  • the polishing process may result in the cap layer 394 being removed.
  • the ILD 317 may be any suitable low-k dielectric material, such as those described above. In an embodiment, the ILD 317 may be the same material or a different material than the other ILD materials 316, 310. In an embodiment, the second backbone hardmask 396 may be the same material as the first backbone hardmask 392. Accordingly, the first and second backbone hardmasks may be etch selective to the spacers 393.
  • FIGS 9A and 9B cross-sectional illustrations of the device after a mask is formed for the source and drain plug are shown, according to an embodiment of the invention.
  • the mask 397 is shown in Figure 9B.
  • the mask 397 is illustrated as dashed lines to indicate that the mask 397 is out of the plane of the illustration.
  • the mask 397 may be formed with suitable lithographic and etching processes, as is well known in the art.
  • the mask 397 is formed from a material that is etch selective to the first and second backbone hardmasks 392, 396.
  • the spacers 393 may be removed with an etching process that selectively removes the spacers 393, and the first backbone hardmask 392 and the second backbone hardmask 396 are substantially resistant to the etching processes.
  • the pattern defined by the first backbone hardmask 392 and the second backbone hardmask 396 is then transferred into the material stack, to form the trenches 398.
  • the trenches 398 may be formed with an etching process.
  • the trenches 398 may be formed through the ILD 316 and expose a top surface of the TFT semiconductor layer 320.
  • the etching chemistry used may preferentially attack the ILD material 316, and the TFT semiconductor layer 330 may be substantially resistant to the etching chemistry used.
  • the source electrode 341 and the drain electrode 342 may be formed with conductive materials, such as copper.
  • the conductive material may be blanket deposited until the trenches 398 are filled.
  • the device may be planarized (e.g., with a chemical mechanical planarizing process). The device may be planarized so that the first backbone hardmask 392, the second backbone hardmask 396, and remaining portions of the etch stop layer 388 are removed.
  • the device may include source electrodes 341 and drain electrodes 342 that have a top surface that is
  • Embodiments of the invention include source electrodes 341 and drain electrodes 342 that are aligned with the TFT semiconductor layer 320.
  • the source electrodes 341 and drain electrodes 342 are aligned so that a sidewall surface is substantially coplanar with a sidewall surface of the TFT semiconductor layer 320.
  • sidewall surface 346 of the source electrode 341 is substantially coplanar with the sidewall surface 319 of the TFT semiconductor layer 320. Accordingly, the contact resistance is reduced because the source electrode 341 and the drain electrode 342 have bottom surfaces that are entirely in contact with the TFT semiconductor layer 320.
  • the dimensions of the source electrodes 341 and the drain electrodes 342 will have substantially similar dimensions, since their shape is defined by the shape of the spacers.
  • FIG. 6 illustrates an interposer 600 that includes one or more embodiments of the invention.
  • the interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604.
  • the first substrate 602 may be, for instance, an integrated circuit die.
  • the second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604.
  • BGA ball grid array
  • the first and second substrates 602/604 are attached to opposing sides of the interposer 600.
  • the first and second substrates 602/604 are attached to the same side of the interposer 600.
  • three or more substrates are interconnected by way of the interposer 600.
  • the interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 608 and vias 610, including but not limited to through- silicon vias (TSVs) 612.
  • the interposer 600 may further include embedded devices 614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
  • Figure 7 illustrates a computing device 700 in accordance with one embodiment of the invention.
  • the computing device 700 may include a number of components.
  • the computing device 700 may include a number of components.
  • these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard.
  • SoC system-on-a-chip
  • the components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communication chip 708. In some
  • the communication chip 708 is fabricated as part of the integrated circuit die 702.
  • the integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM
  • eDRAM spin- transfer torque memory
  • STTM spin- transfer torque memory
  • Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, an antenna 722, a display or a touchscreen display 724, a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage
  • the communications chip 708 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 708.
  • a first communication chip 708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes one or more devices, such as
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 708 may also include one or more devices, such as TFT devices with self- aligned source and drain electrodes, that are formed in accordance with embodiments of the invention.
  • another component housed within the computing device 700 may contain one or more devices, such as TFT devices with self-aligned source and drain electrodes, that are formed in accordance with implementations of the invention.
  • the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • Example 1 a method of forming a thin- film transistor (TFT), comprising: forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer; forming a first backbone hardmask over the TFT stack; forming spacers along sidewalls of the first backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches; depositing a interlay er dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers; removing the spacers; forming second trenches into the material stack; and forming source electrodes and drain electrodes in the trenches.
  • TFT thin- film transistor
  • Example 2 the method of Example 1, wherein the source electrodes and the drain electrodes are aligned with the TFT semiconductor layer.
  • Example 3 the method of Example 1 or Example 2, wherein a side wall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer.
  • Example 4 the method of Example 1, Example 2, or Example 3, further comprising: forming an etch stop layer below the first backbone hardmask and the spacers.
  • Example 5 the method of Example 1, Example 2, Example 3, or Example 4, further comprising: forming a cap layer over a top surface of the first backbone hardmask and the spacers.
  • Example 6 the method of Example 1, Example 2, Example 3, Example 4, or Example 5, further comprising: forming a first ILD layer over the material stack prior to forming the first backbone hardmask and the spacers.
  • Example 7 the method of Example 1, Example 2, Example 3, Example 4, Example 5, or Example 6, wherein the TFT stack is formed over a lower ILD layer.
  • Example 8 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, further comprising vias formed through the lower ILD layer.
  • Example 9 the method of Example 1, Example 2, Example 3, Example 4, Example 5,
  • Example 6 Example 7, or Example 8, wherein the vias contact an interconnect line below the lower ILD layer and the gate electrode layer.
  • Example 10 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, further comprising: forming trenches through the TFT stack, wherein the trenches run substantially parallel to the interconnect line.
  • Example 11 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, or Example 10, wherein the trenches that run substantially parallel to the interconnect line are filled with an ILD.
  • Example 12 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, or Example 11, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
  • Example 13 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, or Example 12, wherein the TFT semiconductor layer has a thickness that is between approximately 5 nm and 50 nm.
  • Example 14 the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, Example 12, or Example 13, wherein the source electrode and the drain electrode have the same dimensions.
  • Example 15 a thin- film transistor (TFT) device, comprising: a gate electrode; a gate dielectric layer formed over a top surface of the gate electrode; a TFT semiconductor layer formed over a top surface of the gate dielectric layer; a source electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the source electrode is aligned with a first sidewall of the gate dielectric layer; and a drain electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the drain electrode is aligned with a second sidewall of the gate dielectric layer.
  • TFT thin- film transistor
  • Example 16 the TFT device of Example 15, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer.
  • Example 17 the TFT device of Example 15 or Example 16, further comprising:
  • ILD interlayer dielectric
  • Example 18 the TFT device of Example 15, Example 16, or Example 17, further comprising: an ILD layer formed below a bottom surface of the gate electrode.
  • Example 19 the TFT device of Example 15, Example 16, Example 17, or Example 18, wherein a via is formed through the ILD layer, and wherein the via contacts a surface of the gate electrode.
  • Example 20 the TFT device of Example 15, Example 16, Example 17, Example 18, or
  • Example 19 wherein the via contacts an interconnect line formed below the ILD layer.
  • Example 21 the TFT device of Example 15, Example 16, Example 17, Example 18, Example 19, or Example 20, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
  • Example 22 the TFT device of Example 15, Example 16, Example 17, Example 18,
  • Example 19 Example 19, Example 20, or Example 21, wherein the TFT semiconductor layer that has a thickness that is between approximately 5 nm and approximately 50 nm.
  • Example 23 the TFT device of Example 15, Example 16, Example 17, Example 18, Example 19, Example 20, Example 21, or Example 22, wherein the source electrode and the drain electrode have the same dimensions.
  • Example 24 a method of forming a thin-film transistor, comprising: forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer; forming a first backbone hardmask over the TFT stack; forming spacers along sidewalls of the first backbone hardmask; forming a cap layer over a top surface of the backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches; depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers; removing the spacers; forming second trenches into the material stack; and forming source electrodes and drain electrodes in the trenches, wherein a sidewall of each of the source electrodes and drain electrodes
  • Example 25 the method of Example 24, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer

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Abstract

Embodiments of the invention include a method of forming a thin-film transistor (TFT) with self-aligned source and drain electrodes. In an embodiment, the method includes forming a TFT stack. Embodiments include forming a first backbone hardmask over the TFT stack, and forming spacers along sidewalls of the first backbone hardmask. In an embodiment the method also includes forming first trenches into the TFT stack, where the first backbone hardmask and the spacers are used as an etch mask to define the trenches, and depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, where the second backbone hardmask is formed between the spacers, and removing the spacers. In an embodiment the method includes forming second trenches into the material stack, and forming source electrodes and drain electrodes in the trenches.

Description

SELF- ALIGNED BACK-GATE TOP- CONTACT THIN-FILM TRANSISTOR FIELD OF THE INVENTION
Embodiments of the invention are in the field of semiconductor processing and, in particular, thin-film transistors and methods of forming such devices with self-aligned electrodes.
BACKGROUND OF THE INVENTION
Some thin- film transistors (TFTs) are fabricated with a gate beneath the active region and a source/drain formed above the active region. A cross-sectional illustration of such a TFT is shown in Figure 1. In Figure 1, a TFT 100 includes a gate electrodel70 that is separated from an active region 120 by a gate dielectric layer 150. The gate electrode 170 may be connected to an interconnect line 190 by a via 180. A source electrode 141 and a drain electrode 142 may be formed in direct contact with the active region 120. The components of the TFT are typically fabricated in layers of interlay er dielectric (ILD) material 110.
As illustrated in Figure 1, the source electrode 141 and the drain electrode 142 are not properly aligned over the active region 120. For example, sidewall 146 of the source electrode 141 is not coplanar with a sidewall 119 of the active region 120. TFTs that are currently available may not have aligned sidewalls because the source electrodes and drain electrodes are typically patterned with a subtractive patterning process that requires a mask to etch the source and drain electrodes. Accordingly, the alignment of the source and drain electrodes is dependent on the alignment of a mask. Furthermore, any misalignment between the source/drain and the active region results in higher contact resistances. As such, misalignment results in a decrease in the performance of the TFT.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a cross-sectional illustration of a thin-film transistor (TFT) that is formed with misaligned source and drain electrodes.
Figure 2 is a cross-sectional illustration of a TFT that is formed with self-aligned source and drain electrodes, according to an embodiment of the invention.
Figures 3A - 3B are cross-sectional illustrations of an incoming film stack that will be fabricated into a TFT, according to an embodiment of the invention.
Figures 4A - 4B are cross-sectional illustrations of the film stack in Figure 3A after trenches are etched into the stack, according to an embodiment of the invention.
Figure 5A - 5B are cross-sectional illustrations of the film stack after an interlayer dielectric is blanket deposited, according to an embodiment of the invention.
Figures 6A - 6B are cross-sectional illustrations of the film stack after a first backbone hardmask with sidewall spacers is formed over the film stack, according to an embodiment of the invention.
Figures 7A - 7B are cross-sectional illustrations of the film stack after etching trenches into the stack while using the hardmask and spacers as an etching mask, according to an embodiment of the invention.
Figures 8A - 8B are cross-sectional illustrations of the film stack after the trenches are filled with an ILD and a second backbone hardmask is deposited over the ILD, according to an embodiment of the invention.
Figures 9A - 9B are cross-sectional illustrations of the film stack after a lithographic mask for a source/drain plug has been formed, according to an embodiment of the invention.
Figures 10A - 10B are cross-sectional illustrations of the film stack after the spacers are removed, and the underlying ILD is etched using the first and second backbones as an etch mask, according to an embodiment of the invention.
Figures 11A -11B are cross-sectional illustrations of the film stack after the source electrodes and the drain electrodes have been formed, according to an embodiment of the invention.
Figure 12 is an interposer implementing one or more embodiments of the invention.
Figure 13 is a computing device built in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
Described herein are systems that include thin-film transistors (TFTs) and methods of forming such devices so that the source electrode and drain electrode are self-aligned with the TFT semiconductor layer. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As noted above, the performance of TFTs is reduced when the source electrode and the drain electrode are misaligned with the TFT semiconductor layer. Accordingly, embodiments of the invention include processing operations that allow for the source electrode and the drain electrode to be self-aligned with the TFT semiconductor layer. Particularly, the self-alignment is provided by the use of a backbone hardmask with spacers, as will be described in greater detail.
Referring now to Figure 2, a cross-sectional illustration of a TFT 200 is shown, according to an embodiment of the invention. The TFT 200 is substantially similar to the TFT 100 described above with respect to Figure 1, with the exception that the source electrode 241 and the drain electrode 242 are self-aligned to the TFT semiconductor layer 220. The self-aligned nature may be seen by comparing the position of the sidewalls of the source and drain electrodes to a sidewall of the TFT semiconductor layer 220. According to an embodiment, a sidewall 246 of the source electrode 241 is substantially coplanar with a sidewall 219 of the TFT
semiconductor layer 220. Accordingly, the contact resistance is reduced because the source electrode 241 and the drain electrode 242 have bottom surfaces that are entirely in contact with the TFT semiconductor layer 220. Furthermore, it is to be appreciated that the dimensions of the source electrodes 341 and the drain electrodes 342 will have substantially similar dimensions, since their shape is defined by the shape of the spacers.
Referring now to Figures 3A-11B, a series of cross-sectional illustrations are shown that illustrate a process for forming a TFT with self-aligned source electrodes and drain electrodes, according to an embodiment of the invention. The figures provide cross-sectional illustrations along two different views of the TFT at different points along the process. Particularly, the "A" figures (e.g., 3A, 4A, 5A, etc.) are views parallel to the length of the gate electrode, and the "B" figures (e.g., 3B, 4B, 5B, etc.) are views orthogonal to the length of the gate electrode.
Referring now to Figures 3A and 3B, cross-sectional illustrations of a TFT stack are shown, according to an embodiment of the invention. According to an embodiment, the TFT stack may include an interlay er dielectric (ILD) 310 on which the other layers are patterned and/or otherwise formed. The ILD 310 may be a first layer of ILD formed on a support substrate (not shown), or it may be any subsequent ILD in a stack-up of multiple ILDs. In an embodiment, the ILD 310 may be any suitable low-k dielectric material. For example, low-k dielectric materials may include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD material may include pores or air gaps to further reduce their dielectric constant.
In an embodiment, an interconnect line 390 may be formed at the bottom of the TFT stack. The interconnect line 390 may be any suitable conductive material. For example, the interconnect line 390 may be copper. In an embodiment, the interconnect line 390 may be electrically coupled to the gate electrode 370 by a via 380 that passes through the ILD 310. In an embodiment, the via 380 may be any suitable conductive material. In an embodiment, the vias 380 may be a workfunction metal, such as TaN. In an embodiment, the gate electrode 370 may be any suitable conductive material. In some embodiments, the gate electrode 370 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. For example, metals that may be used for the gate electrode 370 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. In an embodiment the gate electrode may be deposited with any suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputtering, or the like.
In an embodiment, a gate dielectric layer 350 may be formed over the gate electrode 370. In an embodiment, the gate dielectric layer 350 may be any suitable high-K dielectric material. In an embodiment, the gate dielectric layer 350 may include one layer or a stack of layers. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In an embodiment, the gate dielectric layer 350 may be blanket deposited over the gate electrode 350. For example, the gate dielectric layer may be deposited with CVD, PECVD, or the like.
In an embodiment, a TFT semiconductor layer 320 may be formed over the surface of the gate dielectric layer 350. In an embodiment, the TFT semiconductor layer may be any suitable semiconductor material used for thin film transistors. In an embodiment, the TFT semiconductor layer 320 may include one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors. In an embodiment, the TFT semiconductor layer 320 is deposited to a thickness between approximately 5 nm and approximately 50 nm. However, it is to be appreciated that the thickness may also be less than 5 nm or greater than 50 nm according to different embodiments of the invention.
Referring now to Figures 4A and 4B, cross-sectional illustrations after trenches 366 are etched through the TFT semiconductor layer 320, the gate dielectric layer 350, and the gate electrode layer 370, according to an embodiment of the invention. According to an embodiment, the trenches 366 may be patterned with any suitable etching process. For example, the trenches 366 may be patterned with typical wet and/or dry etching processes. In the Figures, the trenches 366 are only shown in Figure 4B, since the trenches 366 are out of the plane illustrated in Figure 4 A. While the trenches 366 are formed in the orthogonal plane in Figure 4B, it is to be appreciated that alternative embodiments may include forming the trenches 366 in the plane illustrated in Figure 4A instead.
Referring now to Figured 5 A and 5B, cross-sectional illustrations after the trenches 366 have been filled with an ILD 316 are shown, according to an embodiment. As illustrated, the ILD 316 completely fills the trenches 366 and covers a top surface of the TFT semiconductor layer 320. In an embodiment, the ILD 316 may be any suitable low-k dielectric material, such as those described above. In some embodiments, the ILD 316 may be the same material as ILD 310. In an alternative embodiment, ILD 316 may be a different material than ILD 310.
Referring now to Figures 6A and 6B, cross-sectional illustrations after a backbone hardmask 392 and spacers 393 have been formed are shown, according to an embodiment of the invention. In an embodiment, an etch stop layer 388 may be formed over the top surface of ILD 316. For example, the etch stop layer 388 may be any suitable hardmask material, such as SiN, or the like. After the etch stop layer 388 is formed, the backbone hardmask 392 may be formed. For example, the backbone hardmask 392 may be formed by depositing the blanket depositing the backbone material and patterning the layer with typical patterning processes.
In an embodiment, spacers 393 may be formed along the sidewalls of the backbone hardmask 392. The spacers 393 may be formed with a material that is etch selective to the material used to form the backbone hardmask 392. Accordingly, either the spacers 393 or the backbone hardmask 392 may be preferentially removed with an etching process in subsequent processing operations. In an embodiment, the spacers 393 may be formed with standard processes known in the art. For example, a conformal layer of the spacer material may be deposited over the structure. Thereafter a spacer etch may be implemented to preferentially remove the spacer material along planar surfaces. In some embodiments, a cap layer 394 may be formed over a top surface of the backbone hardmask 392 and the spacers 393. The cap layer 394 may be used to protect the backbone hardmask 392 and the spacers 393 from subsequent etching operations. In an embodiment, the cap layer 394 may be any suitable mask layer, such TiN.
Referring now to Figures 7A and 7B, cross-sectional illustrations of the device after trenches 395 are formed through the TFT semiconductor layer 320, the gate dielectric layer 350, and the gate electrode 370 are shown, according to an embodiment of the invention. In an embodiment, the trenches are formed using the backbone hardmask 392 and the spacers 393 as a mask. The trenches 395 define the shape and dimensions of the gate electrode 370, the gate dielectric 350, and the TFT semiconductor layer 320. Particularly, the trenches 395 define the sidewalls of the TFT semiconductor layer 320 that will subsequently be aligned to the sidewalls of the source and drain electrodes. In the Figures, the trenches 395 are only shown in Figure 7A, since the trenches 395 are out of the plane illustrated in Figure 7B. While the trenches 395 are formed in the plane in Figure 7A, it is to be appreciated that alternative embodiments may include forming the trenches 395 in the plane illustrated in Figure 7B instead.
Referring now to Figures 8A and 8B, cross-sectional illustrations of the device after an additional ILD layer 317 has been deposited into the trenches 395, and a second backbone hardmask 396 is formed between the spacers 393 are shown, according to an embodiment of the invention. In an embodiment, after the second backbone hardmask 396 is formed, the device may be planarized with a polishing process. For example, the polishing process may result in the cap layer 394 being removed.
In an embodiment, the ILD 317 may be any suitable low-k dielectric material, such as those described above. In an embodiment, the ILD 317 may be the same material or a different material than the other ILD materials 316, 310. In an embodiment, the second backbone hardmask 396 may be the same material as the first backbone hardmask 392. Accordingly, the first and second backbone hardmasks may be etch selective to the spacers 393.
Referring now to Figures 9A and 9B, cross-sectional illustrations of the device after a mask is formed for the source and drain plug are shown, according to an embodiment of the invention. In the illustrated embodiment, the mask 397 is shown in Figure 9B. In Figure 9A, the mask 397 is illustrated as dashed lines to indicate that the mask 397 is out of the plane of the illustration. In an embodiment, the mask 397 may be formed with suitable lithographic and etching processes, as is well known in the art. In an embodiment, the mask 397 is formed from a material that is etch selective to the first and second backbone hardmasks 392, 396.
Referring now to Figures 10A and 10B, cross-sectional illustrations of the device after the spacers 393 are removed and trenches 398 are formed into the material stack are shown, according to an embodiment of the invention. In an embodiment, the spacers 393 may be removed with an etching process that selectively removes the spacers 393, and the first backbone hardmask 392 and the second backbone hardmask 396 are substantially resistant to the etching processes. In an embodiment, the pattern defined by the first backbone hardmask 392 and the second backbone hardmask 396 is then transferred into the material stack, to form the trenches 398. For example, the trenches 398 may be formed with an etching process. In an embodiment, the trenches 398 may be formed through the ILD 316 and expose a top surface of the TFT semiconductor layer 320. According to an embodiment, the etching chemistry used may preferentially attack the ILD material 316, and the TFT semiconductor layer 330 may be substantially resistant to the etching chemistry used.
Referring now to Figures 11A and 11B, cross-sectional illustrations of the device after the source electrode 341 and the drain electrode 342 are formed are shown, according to an embodiment of the invention. In an embodiment, the source electrode 341 and the drain electrode 342 may be formed with conductive materials, such as copper. In an embodiment, the conductive material may be blanket deposited until the trenches 398 are filled. In an embodiment, the device may be planarized (e.g., with a chemical mechanical planarizing process). The device may be planarized so that the first backbone hardmask 392, the second backbone hardmask 396, and remaining portions of the etch stop layer 388 are removed. In an embodiment, the device may include source electrodes 341 and drain electrodes 342 that have a top surface that is
substantially planar with top surfaces of ILDs 316 and/or 317.
Embodiments of the invention include source electrodes 341 and drain electrodes 342 that are aligned with the TFT semiconductor layer 320. Particularly, the source electrodes 341 and drain electrodes 342 are aligned so that a sidewall surface is substantially coplanar with a sidewall surface of the TFT semiconductor layer 320. For example, sidewall surface 346 of the source electrode 341 is substantially coplanar with the sidewall surface 319 of the TFT semiconductor layer 320. Accordingly, the contact resistance is reduced because the source electrode 341 and the drain electrode 342 have bottom surfaces that are entirely in contact with the TFT semiconductor layer 320. Furthermore, it is to be appreciated that the dimensions of the source electrodes 341 and the drain electrodes 342 will have substantially similar dimensions, since their shape is defined by the shape of the spacers.
Figure 6 illustrates an interposer 600 that includes one or more embodiments of the invention. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.
The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
The interposer may include metal interconnects 608 and vias 610, including but not limited to through- silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
Figure 7 illustrates a computing device 700 in accordance with one embodiment of the invention. The computing device 700 may include a number of components. In one
embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communication chip 708. In some
implementations the communication chip 708 is fabricated as part of the integrated circuit die 702. The integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM
(eDRAM) or spin- transfer torque memory (STTM or STTM-RAM).
Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, an antenna 722, a display or a touchscreen display 724, a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communications chip 708 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 708. For instance, a first communication chip 708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 704 of the computing device 700 includes one or more devices, such as
TFT devices with self-aligned source and drain electrodes, that are formed in accordance with embodiments of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 708 may also include one or more devices, such as TFT devices with self- aligned source and drain electrodes, that are formed in accordance with embodiments of the invention.
In further embodiments, another component housed within the computing device 700 may contain one or more devices, such as TFT devices with self-aligned source and drain electrodes, that are formed in accordance with implementations of the invention.
In various embodiments, the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1: a method of forming a thin- film transistor (TFT), comprising: forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer; forming a first backbone hardmask over the TFT stack; forming spacers along sidewalls of the first backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches; depositing a interlay er dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers; removing the spacers; forming second trenches into the material stack; and forming source electrodes and drain electrodes in the trenches.
Example 2: the method of Example 1, wherein the source electrodes and the drain electrodes are aligned with the TFT semiconductor layer.
Example 3: the method of Example 1 or Example 2, wherein a side wall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer.
Example 4: the method of Example 1, Example 2, or Example 3, further comprising: forming an etch stop layer below the first backbone hardmask and the spacers.
Example 5: the method of Example 1, Example 2, Example 3, or Example 4, further comprising: forming a cap layer over a top surface of the first backbone hardmask and the spacers.
Example 6: the method of Example 1, Example 2, Example 3, Example 4, or Example 5, further comprising: forming a first ILD layer over the material stack prior to forming the first backbone hardmask and the spacers.
Example 7: the method of Example 1, Example 2, Example 3, Example 4, Example 5, or Example 6, wherein the TFT stack is formed over a lower ILD layer.
Example 8: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, further comprising vias formed through the lower ILD layer.
Example 9: the method of Example 1, Example 2, Example 3, Example 4, Example 5,
Example 6, Example 7, or Example 8, wherein the vias contact an interconnect line below the lower ILD layer and the gate electrode layer.
Example 10: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, further comprising: forming trenches through the TFT stack, wherein the trenches run substantially parallel to the interconnect line.
Example 11: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, or Example 10, wherein the trenches that run substantially parallel to the interconnect line are filled with an ILD.
Example 12: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, or Example 11, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
Example 13: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, or Example 12, wherein the TFT semiconductor layer has a thickness that is between approximately 5 nm and 50 nm.
Example 14: the method of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, Example 12, or Example 13, wherein the source electrode and the drain electrode have the same dimensions.
Example 15: a thin- film transistor (TFT) device, comprising: a gate electrode; a gate dielectric layer formed over a top surface of the gate electrode; a TFT semiconductor layer formed over a top surface of the gate dielectric layer; a source electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the source electrode is aligned with a first sidewall of the gate dielectric layer; and a drain electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the drain electrode is aligned with a second sidewall of the gate dielectric layer.
Example 16: the TFT device of Example 15, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer.
Example 17: the TFT device of Example 15 or Example 16, further comprising:
an interlayer dielectric (ILD) material formed between the source electrode and the drain electrode, wherein the ILD has a top surface that is substantially coplanar with a top surface of the source electrode and the drain electrode.
Example 18: the TFT device of Example 15, Example 16, or Example 17, further comprising: an ILD layer formed below a bottom surface of the gate electrode.
Example 19: the TFT device of Example 15, Example 16, Example 17, or Example 18, wherein a via is formed through the ILD layer, and wherein the via contacts a surface of the gate electrode.
Example 20: the TFT device of Example 15, Example 16, Example 17, Example 18, or
Example 19, wherein the via contacts an interconnect line formed below the ILD layer.
Example 21: the TFT device of Example 15, Example 16, Example 17, Example 18, Example 19, or Example 20, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
Example 22: the TFT device of Example 15, Example 16, Example 17, Example 18,
Example 19, Example 20, or Example 21, wherein the TFT semiconductor layer that has a thickness that is between approximately 5 nm and approximately 50 nm.
Example 23: the TFT device of Example 15, Example 16, Example 17, Example 18, Example 19, Example 20, Example 21, or Example 22, wherein the source electrode and the drain electrode have the same dimensions.
Example 24: a method of forming a thin-film transistor, comprising: forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer; forming a first backbone hardmask over the TFT stack; forming spacers along sidewalls of the first backbone hardmask; forming a cap layer over a top surface of the backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches; depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers; removing the spacers; forming second trenches into the material stack; and forming source electrodes and drain electrodes in the trenches, wherein a sidewall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer, and wherein the source electrode and the drain electrode have the same dimensions.
Example 25: the method of Example 24, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer

Claims

CLAIMS What is claimed is:
1. A method of forming a thin- film transistor (TFT), comprising:
forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer;
forming a first backbone hardmask over the TFT stack;
forming spacers along sidewalls of the first backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches;
depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers;
removing the spacers;
forming second trenches into the material stack; and
forming source electrodes and drain electrodes in the trenches.
2. The method of claim 1, wherein the source electrodes and the drain electrodes are aligned with the TFT semiconductor layer.
3. The method of claim 2, wherein a sidewall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer.
4. The method of claim 1, further comprising:
forming an etch stop layer below the first backbone hardmask and the spacers.
5. The method of claim 1, further comprising: forming a cap layer over a top surface of the first backbone hardmask and the spacers.
6. The method of claim 1, further comprising:
forming a first ILD layer over the material stack prior to forming the first backbone hardmask and the spacers.
7. The method of claim 1, wherein the TFT stack is formed over a lower ILD layer.
8. The method of claim 7, further comprising vias formed through the lower ILD layer.
9. The method of claim 8, wherein the vias contact an interconnect line below the lower ILD layer and the gate electrode layer.
The method of claim 9, further comprising:
forming trenches through the TFT stack, wherein the trenches run substantially parallel to the interconnect line.
The method of claim 9, wherein the trenches that run substantially parallel to the interconnect line are filled with an ILD.
The method of claim 1, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
13. The method of claim 1, wherein the TFT semiconductor layer has a thickness that is between approximately 5 nm and 50 nm.
14. The method of claim 1, wherein the source electrode and the drain electrode have the same dimensions.
15. A thin-film transistor (TFT) device, comprising:
a gate electrode;
a gate dielectric layer formed over a top surface of the gate electrode; a TFT semiconductor layer formed over a top surface of the gate dielectric layer; a source electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the source electrode is aligned with a first sidewall of the gate dielectric layer; and
a drain electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the drain electrode is aligned with a second sidewall of the gate dielectric layer.
16. The TFT device of claim 15, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer.
17. The TFT device of claim 15, further comprising:
an interlayer dielectric (ILD) material formed between the source electrode and the drain electrode, wherein the ILD has a top surface that is substantially coplanar with a top surface of the source electrode and the drain electrode.
18. The TFT device of claim 15, further comprising:
an ILD layer formed below a bottom surface of the gate electrode.
19. The TFT device of claim 18, wherein a via is formed through the ILD layer, and wherein the via contacts a surface of the gate electrode.
20. The TFT device of claim 19, wherein the via contacts an interconnect line formed below the ILD layer.
21. The TFT device of claim 15, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.
22. The TFT device of claim 15, wherein the TFT semiconductor layer that has a thickness that is between approximately 5 nm and approximately 50 nm.
23. The TFT device of claim 15, wherein the source electrode and the drain electrode have the same dimensions.
24. A method of forming a thin-film transistor, comprising:
forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer;
forming a first backbone hardmask over the TFT stack;
forming spacers along sidewalls of the first backbone hardmask; forming a cap layer over a top surface of the backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches;
depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers;
removing the spacers; forming second trenches into the material stack; and
forming source electrodes and drain electrodes in the trenches, wherein a sidewall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer, and wherein the source electrode and the drain electrode have the same dimensions.
The method of claim 24, wherein an entire bottom surface of the source electrode and entire bottom surface of the drain electrode contact a top surface of the TFT
semiconductor layer.
PCT/US2017/040551 2017-07-01 2017-07-01 Self-aligned back-gate top-contact thin-film transistor WO2019009872A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039081A1 (en) * 1998-05-01 2001-11-08 Takashi Miyamoto Thin film transistor for preventing a back channel effect and a method for fabricating the same
KR20020071060A (en) * 2001-03-02 2002-09-12 삼성에스디아이 주식회사 TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT
US20050110090A1 (en) * 2003-11-25 2005-05-26 Jae-Bon Koo Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor
US20060166415A1 (en) * 2004-06-07 2006-07-27 Sharp Laboratories Of America, Inc. Two-transistor tri-state inverter
US20160343828A1 (en) * 2014-11-03 2016-11-24 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for manufacturing amoled backplane

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039081A1 (en) * 1998-05-01 2001-11-08 Takashi Miyamoto Thin film transistor for preventing a back channel effect and a method for fabricating the same
KR20020071060A (en) * 2001-03-02 2002-09-12 삼성에스디아이 주식회사 TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT
US20050110090A1 (en) * 2003-11-25 2005-05-26 Jae-Bon Koo Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor
US20060166415A1 (en) * 2004-06-07 2006-07-27 Sharp Laboratories Of America, Inc. Two-transistor tri-state inverter
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