CN102044469A - 集成电路结构及其形成方法 - Google Patents
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Abstract
本发明提供一种集成电路结构及其形成方法。上述集成电路结构包括一基板;两个隔绝区,位于上述基板上方,其中两个上述隔绝区的其中之一包括位于其中的一孔洞;以及一第一半导体条状物,介于两个上述隔绝区之间且邻接于两个上述隔绝区,其中上述第一半导体条状物包括一顶部,上述顶部形成位于两个上述隔绝区上方的一鳍状物。本发明可在鳍状场效晶体管的栅极的正下方形成孔洞。因为孔洞为空气的袋状物,其介电常数约等于1.0,所以可以降低浅沟槽隔绝区的等效介电常数。因此可降低寄生电容的电容值,改善最终的集成电路的性能。
Description
技术领域
本发明涉及一种集成电路,尤其涉及一种浅沟槽隔绝区(STI)和半导体鳍状物的结构及其形成方法。
背景技术
为了增加集成电路的尺寸微缩程度,以及增加对集成电路的速度的要求,晶体管在尺寸微缩的同时需要更高的驱动电流。因此研发出鳍状场效晶体管(FinFET)。图1显示一公知鳍状场效晶体管的剖面图,其中上述剖面图是穿过鳍状物而并非穿过源极区和漏极区。鳍状物100形成为垂直的硅鳍状物,其延伸至基板102上方,且鳍状物100用以形成源极区、漏极区(图未显示)和源极区以及漏极区之间的沟道区。形成浅沟槽隔绝区(STI)120以定义鳍状物100。栅极108形成于鳍状物100上方。形成栅极介电质106以隔开鳍状物100和栅极108。
可以了解的是,栅极108和半导体条状物122之间会产生寄生电容(显示为电容110),其中浅沟槽隔绝区(STI)120作为寄生电容110的绝缘物。寄生电容会对各自的集成电路产生不利的影响,因而需要降低寄生电容。
发明内容
有鉴于此,本发明的一实施例提供一种集成电路结构。本发明一实施例的集成电路结构包括一基板;两个隔绝区,位于上述基板上方,其中两个上述隔绝区的其中之一包括位于其中的一孔洞;以及一第一半导体条状物,介于两个上述隔绝区之间且邻接于两个上述隔绝区,其中上述第一半导体条状物包括一顶部,上述顶部形成位于两个上述隔绝区上方的一鳍状物。
本发明的另一实施例提供一种集成电路结构,上述集成电路结构包括一半导体基板;一第一半导体条状物,位于上述半导体基板上方;一第二半导体条状物,位于上述半导体基板上方;一浅沟槽隔绝区,位于上述半导体基板上方,介于上述第一和第二半导体条状物之间且邻接于上述第一和第二半导体条状物,其中上述浅沟槽隔绝区包括位于其中的一孔洞,且其中位于上述浅沟槽隔绝区的一顶面的上方的上述第一半导体条状物的一部分形成一第一鳍状物,且其中位于上述浅沟槽隔绝区的上述顶面的上方的上述第二半导体条状物的一部分形成一第二鳍状物;一栅极介电质,位于上述第一和第二鳍状物的顶面和侧壁上;以及一栅极,位于上述栅极介电质上,上述栅极位于上述孔洞和上述第一和第二鳍状物的正上方。
本发明的又一实施例提供一种集成电路结构的形成方法,上述集成电路结构的形成方法包括提供一半导体基板;在上述半导体基板中形成两个隔绝区,且上述半导体基板的一条状物介于两个上述隔绝区之间且邻接于两个上述隔绝区;以及凹陷两个上述隔绝区的顶面,其中位于两个上述隔绝区上方的上述半导体基板的上述条状物的一顶部形成一第一鳍状物,且其中在上述凹陷步骤之后,两个上述隔绝区的其中之一包括位于其中的一孔洞。
本发明的又另一实施例提供一种集成电路结构的形成方法,上述集成电路结构的形成方法包括提供一半导体基板;蚀刻上述半导体基板以形成两个沟槽,且上述半导体基板的一条状物介于两个上述沟槽之间;以一介电材料填充上述些沟槽以形成两个浅沟槽隔绝区;凹陷两个上述浅沟槽隔绝区的顶面,其中在上述凹陷步骤之后,两个上述浅沟槽隔绝区的其中之一包括位于其中的一孔洞,其中位于两个上述浅沟槽隔绝区上方的上述半导体基板的上述条状物的一顶部形成一第一鳍状物;在上述第一鳍状物的一顶面和侧壁上形成一栅极介电质;以及在上述栅极介电质上形成一栅极。
本发明实施例具有许多优点。可在鳍状场效晶体管的栅极的正下方形成孔洞。因为孔洞为空气的袋状物,其介电常数约等于1.0,所以可以降低浅沟槽隔绝区的等效介电常数。可降低寄生电容的电容值。因此可以改善最终的集成电路的性能。
附图说明
图1为公知的鳍状场效晶体管的剖面图。
图2-图9为本发明一实施例的鳍状场效晶体管的工艺剖面图。
上述附图中的附图标记说明如下:
100~鳍状物;
102~基板;
106~栅极介电质;
108~栅极;
110~电容;
120~浅沟槽隔绝区;
122~半导体条状物;
20~半导体基板;
22~焊盘层;
24~掩模层;
26~光致抗蚀剂
28~开口;
32~沟槽;
34~焊盘氧化物;
36~氧化物;
38~孔洞;
39~开口;
40、40’~浅沟槽隔绝区;
42~半导体条状物;
43~缝隙;
52~凹陷;
60~鳍状物;
62~栅极介电质;
64~栅极;
66~鳍状场效晶体管;
80~寄生电容;
S~间隙;
W~宽度;
D~深度;
D’、D”~距离。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例,作为本发明的参考依据。在附图或说明书描述中,相似或相同的部分都使用相同的附图标记。且在附图中,实施例的形状或是厚度可扩大,并以简化或是方便标示。再者,附图中各元件的部分将以分别描述说明,值得注意的是,图中未显示或描述的元件,为所属技术领域中普通技术人员所知的形式,另外,特定的实施例仅为揭示本发明使用的特定方式,其并非用以限定本发明。
本发明实施例提供一种新颖的方法,其用以形成一浅沟槽隔绝区(STI)和一鳍状场效晶体管(FinFET)。以下利用工艺剖面图,以更详细地说明本发明较佳实施例的半导体装置及其形成方法,在本发明各实施例中,相同的符号表示相同的元件。
请参考图2,提供一半导体基板20。在本发明一实施例中,半导体基板20包括硅。半导体基板20也可包括其他常用的材料,例如碳、锗、镓、砷、氮、铟及/或磷或其他类似的材料。半导体基板20可为一块状基板或一半导体上覆硅(SOI)基板。
可在半导体基板20上形成焊盘层22和掩模层24。上述焊盘层22可包括利用热氧化法形成的一氧化硅薄膜。上述焊盘层22可作为介于半导体基板20和掩模层24之间一粘着层。上述焊盘层22也可作为掩模层24的蚀刻停止层。在本发明一实施例中,掩模层24可为利用例如利用低压化学气相沉积法(LPCVD)形成的氮化硅。在本发明其他实施例中,可利用热氮化硅的方式、等离子体增强型化学气相沉积法(PECVD)或等离子体阳极氮化法形成掩模层24。在后续光刻工艺期间,掩模层24可作为一硬掩模。在掩模层24上形成光致抗蚀剂26并接着图案化光致抗蚀剂26,且在光致抗蚀剂26中形成开口28。
请参考图3,蚀刻焊盘层22和掩模层24穿过开口28,且暴露其下的半导体基板20。接着,蚀刻上述暴露的半导体基板20,以形成沟槽32。介于沟槽32之间的半导体基板20部分形成半导体条状物42。沟槽32可为彼此平行的条状物(在上视图中),且彼此紧密地设置。举例来说,沟槽32之间的间隙S可小于30nm。然后,移除光致抗蚀剂26。之后,可进行一清洁步骤以移除半导体基板20的原生氧化物。可利用稀释的氢氟酸(HF)进行上述清洁步骤。
当沟槽32的宽度W约介于至之间时,沟槽32的深度D可约介于至之间。在本发明一实施例中,沟槽32的深宽比(aspect ratio,D/W)约大于7.0。在本发明其他实施例中,上述深宽比可约大于8。然而,上述深宽比也可约小于7.0或约介于7.0至8.0之间。然而,本领域普通技术人员可了解,说明书内容中的尺寸和数值仅作为范例,且可为了适合不同尺寸的集成电路以改变上述尺寸和数值。
接着,如图4所示,在沟槽32中形成焊盘氧化物34。在本发明一实施例中,焊盘氧化物34可为一热氧化物,其厚度可约介于至之间。在本发明其他实施例中,可利用现场蒸气产生法(ISSG)形成焊盘氧化物34。在本发明的其他实施例中,可利用能够形成顺应性氧化层的沉积法形成焊盘氧化物34,例如选择性面积化学气相沉积法(SACVD)或类似的方法。焊盘氧化物34的形成方式会使沟槽32的角落变圆,其可降低电场,且因此可改善最终集成电路的性能。
请参考图5A、图5B和图5C,以介电材料36填充上述沟槽32。上述介电材料36可包括氧化硅,且因此之后可视为氧化物36。然而,介电材料36也可使用例如氮化硅(SiN)、碳化硅(SiC)或类似材料的其他介电材料。在本发明一实施例中,可利用一高深宽比工艺(high aspect-ration process,HARP)形成氧化物36。上述工艺的气体可包括或四乙氧基硅烷(Tetraethoxysilane,TEOS)和臭氧(O3)。位于沟槽32中的部分氧化物36和焊盘氧化物34之后可视为浅沟槽隔绝(STI)区40。为简单说明起见,图5B、图5C和之后的附图不再显示焊盘氧化物34。
可在氧化物36中形成孔洞38。在本发明一实施例中,可选择例如高深宽比工艺(HARP)的适当方法和采用适当工艺条件形成孔洞38,上述高深宽比工艺(HARP)可帮助于氧化物36中形成孔洞38。半导体条状物42可用以形成一单一鳍状场效晶体管(FinFET)(请参考图8A和图9),然而,半导体条状物42也可用以形成多重鳍状场效晶体管(multiple FinFETs)。因此,介于半导体条状物42之间的浅沟槽隔绝区40可视为元件内(intra-device)浅沟槽隔绝区。相反地,介于半导体条状物42之间的一浅沟槽隔绝区40’(请参考图5B和图9)可视为一元件间(inter-device)浅沟槽隔绝区。在本发明一实施例中,元件内(intra-device)浅沟槽隔绝区40具有形成于其中的孔洞38,而元件间(inter-device)浅沟槽隔绝区40’不具有形成于其中的孔洞。孔洞较可能在具有较深宽比的沟槽中形成。另外,元件间浅沟槽隔绝区40’可具有较元件内浅沟槽隔绝区40小的深宽比。因此,可选择形成氧化物36的适当方法,且选择元件内浅沟槽隔绝区40和元件间浅沟槽隔绝区40’的适当深宽比,以在元件内浅沟槽隔绝区40中形成孔洞38(而不在元件间浅沟槽隔绝区40’中形成孔洞)。
另外,在形成鳍状场效晶体管元件(请参考图8A至图9)之后,孔洞38最好留在结构中。因此,孔洞38的理想位置会被在后续凹陷步骤(请参考图7A和图7B)移除的浅沟槽隔绝区的数量影响。在本发明一实施例中,孔洞38的顶端与半导体条状物42的顶端垂直间隔一距离D’(图5A),其值约大于25nm。例如可利用调整形成氧化物36的工艺条件,例如沉积率、工艺气体流速、基板20的温度或类似条件等,以形成上述距离D’。在本发明一实施例中,可在大于约500托尔(Torr)的低于一大气压的工艺气体压力下与四乙氧基硅烷(TEOS)和臭氧(O3)形成浅沟槽隔绝区40。工艺腔室内的工艺气体压力也可介于约500托尔至约760托尔之间。四乙氧基硅烷(TEOS)的气体流速可大于约10sccm,而臭氧(O3)的气体流速可大于约10sccm。高气体流速和高气体压力有助于形成孔洞。
如图5C所示,在本发明其他实施例中,没有孔洞38形成。然而,在沟槽32的相对侧壁上成长的氧化物36会彼此连结,以在沟槽32的中央形成缝隙43。由于高密度的悬键(dangling bond),缝隙43为氧化物36的较弱部分。
然后,进行化学机械研磨步骤,以移除掩模层24和焊盘层22。图6显示最终结构。如果掩模层24是由氮化硅形成,则可利用使用热磷酸(H3PO4)的湿蚀刻工艺去除掩模层24。而如果焊盘层22是由氧化硅形成,则可利用使用稀释的氢氟酸(HF)的湿蚀刻工艺去除焊盘层22。
接着,如图6所示的结构用以形成鳍状物,上述鳍状物用以形成鳍状场效晶体管(FinFET)。如图7A和图7B所示,可利用蚀刻方式凹陷浅沟槽隔绝区40,以形成凹陷52。半导体条状物42的一部分突出于残留的浅沟槽隔绝区40顶面的上方,因此上述半导体条状物42的一部分变成鳍状物60。在本发明一实施例中,凹陷氧化物36的步骤可包括在例如在一稀释的氢氟酸(HF)溶液中进行的一湿式浸泡法。在本发明其他实施例中,上述蚀刻方式可为干蚀刻。凹陷52的距离D”可约介于15nm至50nm。
请参考图7A,孔洞38嵌入残留的浅沟槽隔绝区40中,且被残留的浅沟槽隔绝区40包围。在图7B中,孔洞38暴露于外部环境中。然而,孔洞38的开口极小。如图5B所示的本发明一实施例中,因为缝隙43(图5C)为氧化物36的较弱部分,在凹陷浅沟槽隔绝区40期间,缝隙43会较其他部分快速的被蚀刻,所以形成孔洞38。另外,如果孔洞38已在形成浅沟槽隔绝区40之前形成,可能会扩大上述暴露的孔洞。
请参考图8A,形成栅极介电质62以覆盖鳍状物60的顶面和侧壁。可利用热氧化法形成栅极介电质62,且因此栅极介电质62可包括热氧化的氧化硅。在本实施例中,栅极介电质62形成于鳍状物60的顶面上,而没有形成于浅沟槽隔绝区40的顶面上。在本发明其他实施例中,可利用沉积步骤形成栅极介电质62。因此,栅极介电质62形成于鳍状物60和浅沟槽隔绝区40的顶面上。接着,在栅极介电质62上形成栅极64。如图8A和图8B所示,在本发明一实施例中,栅极64可覆盖多于一个鳍状物60,以便形成多鳍式鳍状场效晶体管的鳍状场效晶体管66。在本发明其他实施例中,每一个鳍状物60可用以形成一鳍状场效晶体管。然后,形成包括源极、漏极、源极硅化物和漏极硅化物(图未显示)的鳍状场效晶体管66的其他元件。上述元件的形成工艺为常用的工艺,在此不作重复说明。
图8B显示从图7B所示结构形成的另一实施例。虽然孔洞38从浅沟槽隔绝区40的顶面暴露出来,但开口39足够小以使形成栅极64之后,孔洞38的开口39被栅极64密封,且孔洞38未被填满。
虽然在图5A至图9所示的实施例中,每一个浅沟槽隔绝区40中只显示一个孔洞38,但每一个浅沟槽隔绝区40中的孔洞数量可以大于一个,且在单一浅沟槽隔绝区40中的多个孔洞可以遍布于浅沟槽隔绝区40。
图9显示从图5C所示结构形成的元件内浅沟槽隔绝区40和元件间浅沟槽隔绝区40’。值得注意的是,元件间浅沟槽隔绝区40’不具有孔洞,且元件间浅沟槽隔绝区40’的正上方不具有任何栅极。相较之下,元件内浅沟槽隔绝区40可具有孔洞38,且元件间元件内浅沟槽隔绝区40位于栅极64的正下方。
本发明实施例具有许多优点。可在鳍状场效晶体管的栅极的正下方形成孔洞。因为孔洞为空气的袋状物,其介电常数约等于1.0,所以可以降低浅沟槽隔绝区40的等效介电常数。可降低寄生电容80(图8A)的电容值。因此可以改善最终的集成电路的性能。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定为准。
Claims (15)
1.一种集成电路结构,包括:
一基板;
两个隔绝区,位于该基板上方,其中两个该隔绝区的其中之一包括位于其中的一孔洞;以及
一第一半导体条状物,介于两个该隔绝区之间且邻接于两个该隔绝区,其中该第一半导体条状物包括一顶部,该顶部形成位于两个该隔绝区上方的一鳍状物。
2.如权利要求1所述的集成电路结构,还包括:
一栅极介电质,位于该鳍状物的一顶面和侧壁上;以及
一栅极,位于该栅极介电质上,其中该栅极包括一部分,位于该孔洞的正上方。
3.如权利要求1所述的集成电路结构,还包括一第二半导体条状物,其中两个该隔绝区的其中之一介于该第一和第二半导体条状物之间且邻接于该第一和第二半导体条状物,且其中该栅极介电质和该栅极延伸位于该第一和第二半导体条状物的正上方。
4.如权利要求1所述的集成电路结构,还包括一额外隔绝区,其与该栅极水平隔开,其中该额外隔绝区不位于任何鳍状场效晶体管的任何栅极的下方,且其中该额外隔绝区不包括任何孔洞。
5.如权利要求1所述的集成电路结构,其中该栅极暴露出该孔洞。
6.如权利要求1所述的集成电路结构,其中该孔洞具有一顶端,其低于两个该隔绝区的其中之一的一顶面。
7.如权利要求3所述的集成电路结构,其中该第一半导体条状物、该第二半导体条状物和该半导体基板由硅形成,且其中该第一半导体条状物和该第二半导体连续地连接至该半导体基板。
8.一种集成电路结构的形成方法,包括下列步骤:
提供一半导体基板;
在该半导体基板中形成两个隔绝区,且该半导体基板的一条状物介于两个该隔绝区之间且邻接于两个该隔绝区;以及
凹陷两个该隔绝区的顶面,其中位于两个该隔绝区上方的该半导体基板的该条状物的一顶部形成一第一鳍状物,且其中在该凹陷步骤之后,两个该隔绝区的其中之一包括位于其中的一孔洞。
9.如权利要求8所述的集成电路结构的形成方法,其中形成该两个隔绝区的步骤包括:
蚀刻该半导体基板以形成多个沟槽;以及
以一介电材料填充该些沟槽以形成该两个隔绝区。
10.如权利要求9所述的集成电路结构的形成方法,其中该孔洞在填充该些沟槽的步骤期间产生。
11.如权利要求9所述的集成电路结构的形成方法,其中该孔洞在凹陷两个该隔绝区的顶面的步骤期间产生。
12.如权利要求8所述的集成电路结构的形成方法,还包括:
在该第一鳍状物的一顶面和侧壁上形成一栅极介电质;以及
在该栅极介电质上形成一栅极,其中该栅极包括一部分,位于该孔洞的正上方。
13.如权利要求12所述的集成电路结构的形成方法,其中该栅极邻接该孔洞。
14.如权利要求12所述的集成电路结构的形成方法,还包括:在该凹陷步骤期间,在两个该隔绝区的该顶面的上方形成一第二鳍状物,其中两个该隔绝区的其中之一水平介于该第一鳍状物和该第二鳍状物之间,且其中该栅极介电质和该栅极延伸位于该第一和第二鳍状物的正上方。
15.如权利要求8所述的集成电路结构的形成方法,在形成该两个隔绝区的步骤期间,同时形成与该栅极水平隔开的一额外隔绝区,其中该额外隔绝区不位于任何鳍状场效晶体管的任何栅极的下方,且其中该额外隔绝区无任何孔洞。
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US20130277757A1 (en) | 2013-10-24 |
US8723271B2 (en) | 2014-05-13 |
TWI430446B (zh) | 2014-03-11 |
JP2011086942A (ja) | 2011-04-28 |
KR20110040651A (ko) | 2011-04-20 |
US20110084340A1 (en) | 2011-04-14 |
KR101243414B1 (ko) | 2013-03-13 |
US8519481B2 (en) | 2013-08-27 |
TW201114036A (en) | 2011-04-16 |
JP5307783B2 (ja) | 2013-10-02 |
CN102044469B (zh) | 2014-03-12 |
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