KR100513405B1 - 핀 트랜지스터의 형성 방법 - Google Patents
핀 트랜지스터의 형성 방법 Download PDFInfo
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- KR100513405B1 KR100513405B1 KR10-2003-0091716A KR20030091716A KR100513405B1 KR 100513405 B1 KR100513405 B1 KR 100513405B1 KR 20030091716 A KR20030091716 A KR 20030091716A KR 100513405 B1 KR100513405 B1 KR 100513405B1
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- 238000000034 method Methods 0.000 title claims abstract description 123
- 230000005669 field effect Effects 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 48
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 150000004767 nitrides Chemical class 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 3
- 239000006227 byproduct Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 125000006850 spacer group Chemical group 0.000 description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000002086 nanomaterial Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (26)
- 반도체 기판에 측벽들이 노출된 상태로 핀 형태의 활성영역을 형성하는 단계;상기 활성영역의 상부 및 측벽들에 게이트 절연막을 형성한 후, 상기 활성영역을 둘러싸는 소자 분리막을 상기 활성영역의 상부 높이로 형성하고, 상기 소자 분리막 상에 상기 측벽들의 일부가 노출되는 개구부를 형성하는 단계;도전막으로 상기 개구부를 채우면서 상기 활성영역의 일부 상부를 덮는 것에 의해 게이트 전극을 형성하는 단계; 및상기 활성영역의 게이트 전극이 형성되지 않은 부위에 상기 게이트 전극을 사이에 두고 소오스 및 드레인을 형성하는 단계를 구비함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제1항에 있어서,상기 반도체 기판은 벌크(bulk) 반도체 기판임을 특징으로 하는 핀 트랜지스터 형성방법.
- 제2항에 있어서,상기 활성영역은 상부 에지 부위가 둥글게 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제3항에 있어서,상기 활성영역의 에지 부위를 둥글게 형성하는 것은 ISSG를 이용한 산화막 형성 공정에 의함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제3항에 있어서,상기 핀 형태의 활성영역을 형성하는 단계 이전에, 반도체 기판 전면에 제1산화막과 제1절연막을 순차적으로 형성하고, 상기 제1절연막 상부에 형성된 제1포토 레지스트 패턴을 이용하여 상기 반도체 기판의 일부 노출시키는 마스크 패턴을 형성하는 단계;상기 반도체 기판의 노출부위 및 상기 마스크 패턴의 측면 및 상부에 이용한 제2산화막을 형성함에 의하여 상기 반도체 기판의 노출 부위와 상기 마스크 패턴의 측면이 맞닿는 부위를 둥글게 형성하는 단계;상기 마스크 패턴의 측면에 형성된 제2산화막을 제외하고, 상기 마스크 패턴의 상부 및 상기 반도체 기판의 표면에 형성된 제2산화막을 제거하는 단계; 및상기 마스크 패턴 및 상기 제1절연막 측면의 제2산화막을 마스크로 하여 상기 반도체 기판을 이방성 식각하는 단계를 더 포함함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제5항에 있어서,상기 제2산화막의 형성은 ISSG 방법을 이용함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제6항에 있어서,상기 핀 형태의 활성영역의 상부에서 하부까지의 길이는 2000Å 내지 3000Å 임을 특징으로 하는 핀 트랜지스터 형성방법.
- 제7항에 있어서,상기 게이트 절연막은, 상기 활성영역의 상부에 형성되어 있는 제1산화막 및 상기 활성영역의 측벽들에 형성되는 제3산화막으로 구성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제8항에 있어서,상기 개구부는, 셀 영역 중 게이트 전극이 형성될 부분에 상기 활성영역의 상부에서 1000Å 내지 1500Å 의 깊이로 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제9항에 있어서,상기 게이트 전극은 폴리 실리콘을 재질로 함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제9항에 있어서,상기 게이트 전극의 상부에 금속 실리사이드 막이 추가로 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제11항에 있어서,상기 트랜지스터는 디램 셀(DRAM CELL)에 적용됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 반도체 기판에 측벽들이 노출된 상태로 핀(fin) 형태의 활성영역을 형성하고, 상기 활성영역의 상부 높이로 상기 활성영역을 둘러싸는 소자분리막을 형성하는 단계;상기 활성영역의 측벽들의 일부가 노출되도록 상기 소자 분리막의 일부에 개구부를 형성하는 단계;상기 개구부에 의해 노출된 측벽들의 일부 및 상기 개구부를 사이에 두는 상기 활성영역의 상부 일부에, 게이트 절연막을 개재하여 상기 개구부를 메우면서 상는 활성영역의 상부 일부를 덮는 게이트 전극을 형성하는 단계; 및상기 활성영역 중 게이트 전극이 형성되지 않은 부위에 상기 게이트 전극을 사이에 두고 소오스 및 드레인을 형성하는 단계를 포함함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제13항에 있어서,상기 반도체 기판은 벌크(bulk) 반도체 기판임을 특징으로 하는 핀 트랜지스터 형성방법.
- 제14항에 있어서,상기 활성영역은 상부 에지 부위가 둥글게 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제15항에 있어서,상기 둥글게 형성되는 상기 활성영역의 에지 부위는 상기 에지 부위에 ISSG를 이용한 산화막을 형성함에 의함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제14항에 있어서, 상기 소자 분리막을 형성하는 단계 이전에,벌크 반도체 기판 전면에 제1산화막과 제1절연막을 순차적으로 형성하고, 상기 제1절연막 상부에 형성된 제1포토 레지스트 패턴을 이용하여 상기 반도체 기판을 일부 노출시키는 마스크 패턴을 형성하는 단계;상기 반도체 기판의 노출부위 및 상기 마스크 패턴의 측면 및 상부에 제2산화막을 형성함에 의하여 상기 반도체 기판의 노출 부위와 상기 마스크 패턴의 측면이 맞닿는 부위를 둥글게 형성하는 단계;상기 마스크 패턴의 측면에 형성된 제2산화막을 제외하고 상기 마스크 패턴의 상부 및 상기 반도체 기판의 상부에 형성된 제2산화막을 제거하는 단계;상기 마스크 패턴 및 상기 마스크 패턴 측면의 제2산화막을 식각 마스크로 하여 상기 반도체 기판을 식각하여 핀 형태를 가지는 활성영역을 형성하는 단계;상기 마스크 패턴에 형성된 제2산화막을 제거하여 상기 활성영역 상부에 둥글게 형성된 에지 부위가 노출되도록 하는 단계;상기 활성영역을 포함하는 상기 반도체 기판의 노출부위에 제1산화막과 연결되는 제3산화막을 형성하고 상기 제3산화막 상에 질화막 라이너 형성하는 단계; 및상기 질화막 라이너가 형성된 반도체 기판 전면에 소자 분리용 절연막을 충진한 후 상기 마스크 패턴을 평탄화 저지막으로 하는 평탄화 공정을 수행하는 단계를 더 포함함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제17항에 있어서,상기 제2산화막의 형성은 ISSG 방법을 이용함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제18항에 있어서,상기 핀 형태의 활성영역의 상부에서 하부까지의 길이는 2000Å 내지 3000Å 임을 특징으로 하는 핀 트랜지스터 형성방법.
- 제19항에 있어서,상기 게이트 절연막은,상기 제1산화막 및 제3산화막을 제거하고, 상기 활성영역의 상부 및 측벽들의 일부에 형성되는 제4산화막으로 구성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제20항에 있어서,상기 개구부는, 셀 영역 중 게이트 전극이 형성될 부분에 상기 활성영역의 상부에서 1000Å 내지 1500Å 의 깊이로 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제21항에 있어서,상기 게이트 전극은 폴리 실리콘을 재질로 함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제22항에 있어서,상기 게이트 전극의 상부에 텅스텐 실리사이드 막이 추가로 형성됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 제23항에 있어서,상기 트랜지스터는 디램 셀(DRAM CELL)에 적용됨을 특징으로 하는 핀 트랜지스터 형성방법.
- 벌크 반도체 기판 전면에 핀 형태의 활성영역을 형성하기 위한 제1포토레지스트 패턴에 의해 제1산화막 및 질화막 적층구조의 마스크 패턴을 형성하는 단계;상기 반도체 기판 및 상기 마스크 패턴의 측면 및 상부에 ISSG를 이용한 제2산화막을 형성함에 의하여 상기 반도체 기판 및 상기 마스크 패턴의 측면이 맞닿는 부위를 둥글게 형성하는 단계;상기 마스크 패턴의 측면에 형성된 제2산화막을 제외하고 상기 마스크 패턴의 상부 및 상기 반도체 기판의 상부에 형성된 제2산화막을 제거한 후 상기 마스크 패턴 및 상기 마스크 패턴의 측면의 제2산화막을 마스크로 하여 상기 반도체 기판을 식각하여 핀 형태를 가지는 활성영역을 형성하는 단계;상기 마스크 패턴의 측면에 형성된 제2산화막을 제거하여 상기 활성영역 상부에 둥글게 형성된 에지 부위가 노출되도록 하고 상기 활성영역을 포함하는 상기 반도체 기판의 노출부위에 제3산화막을 형성하고 상기 제3산화막이 형성된 반도체 기판 전면에 질화막 라이너를 형성하는 단계;상기 질화막 라이너가 형성된 반도체 기판 전면에 소자 분리용 절연막을 충진한 후 상기 마스크 패턴을 평탄화 저지막으로 하는 평탄화 공정을 수행하여 소자 분리막을 형성하는 단계;상기 마스크 패턴을 식각 마스크로 하여 상기 활성영역의 상부높이까지 상기 소자분리막을 에치 백하는 단계;상기 반도체 기판 전면에 질화막 재질의 제2절연막을 일정 두께로 형성하고, 상기 소자 분리막의 상부가 노출되도록 상기 제2절연막을 에치 백하여 상기 마스크 패턴의 측벽에 질화막 스페이서를 형성하는 단계;셀 영역의 게이트가 형성될 부분만을 노출시키는 제2포토 레지스트 패턴 및 상기 질화막 스페이서를 마스크로 하여 상기 소자 분리막을 일정깊이까지 식각하여 상기 활성영역의 측벽들의 일부를 노출시키는 개구부를 형성하는 단계;상기 제2포토 레지스트 패턴을 제거하고 상기 질화막 스페이서를 마스크로 하여 등방성 식각 공정을 수행하여 상기 소자분리막 중 활성영역의 상부 에지 부위와 질화막 라이너 사이에 형성되어 있는 부분을 제거하는 단계;상기 활성영역 상부의 마스크 패턴, 질화막 스페이서 및 노출된 측벽의 질화막 라이너를 제거하는 단계;상기 질화막 라이너가 제거된 반도체 기판 전면에 상기 개구부를 메우면서 일정 두께를 가지는 도전막 인 폴리 실리콘막을 형성하고, 상기 도전막 상부에 텅스텐 실리사이드 막 및 캡핑막용 질화막을 순차적으로 형성하는 단계;제3 포토 레지스트 패턴에 의해 상기 캡핑막용 질화막, 텅스텐 실리사이드 막 및 폴리 실리콘 막을 상기 소자 분리막이 노출될 때까지 차례로 식각하여 게이트 전극 및 게이트 캡핑막을 형성하는 단계; 및상기 게이트 전극이 형성되지 않은 활성영역의 부위에 상기 게이트 전극을 사이에 두고 소오스 및 드레인을 형성하는 단계를 포함함을 특징으로 하는 핀 트랜지스터 형성방법.
- 제25항에 있어서,상기 활성영역 상부의 마스크 패턴, 질화막 스페이서 및 노출된 측벽의 질화막 라이너를 제거하는 단계 다음에, 상기 노출된 활성영역의 상부 및 노출된 측벽들에 형성되어 있는 제1산화막 및 제3산화막을 제거하여 활성영역의 상부 및 측벽들의 일부를 노출시키는 단계; 및상기 노출된 활성영역의 상부 및 측벽들의 일부에 게이트 절연막을 형성하는 단계를 더 포함함을 특징으로 하는 핀 트랜지스터 형성방법.
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