CN107546127A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN107546127A
CN107546127A CN201610490392.3A CN201610490392A CN107546127A CN 107546127 A CN107546127 A CN 107546127A CN 201610490392 A CN201610490392 A CN 201610490392A CN 107546127 A CN107546127 A CN 107546127A
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epitaxial layer
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CN107546127B (zh
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詹电鍼
李凡
李一凡
冯立伟
张明华
林钰书
詹书俨
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。首先形成一鳍状结构于一基底上，然后形成一第一衬垫层于基底及鳍状结构上，形成一第二衬垫层于第一衬垫层上，去除部分第二衬垫层及部分第一衬垫层并暴露出鳍状结构的上表面，去除鳍状结构及第二衬垫层之间的部分第一衬垫层以形成一凹槽。最后再形成一外延层于凹槽内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于鳍状结构上形成外延层作为半导体元件的通道的方法。
背景技术
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effecttransistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的形成仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先形成一鳍状结构于一基底上，然后形成一第一衬垫层于基底及鳍状结构上，形成一第二衬垫层于第一衬垫层上，去除部分第二衬垫层及部分第一衬垫层并暴露出鳍状结构的上表面，去除鳍状结构及第二衬垫层之间的部分第一衬垫层以形成一凹槽。最后再形成一外延层于凹槽内。
本发明另一实施例公开一种半导体元件，其包含：一基底；一鳍状结构设于基底上；一外延层设于鳍状结构上，外延层接触该鳍状结构的上表面与侧壁以及基底的上表面，其中外延层为倒U型；以及一浅沟隔离环绕外延层，其中浅沟隔离直接接触基底。
本发明又一实施例公开一种半导体元件，其包含：一基底；一鳍状结构设于基底上；一外延层设于鳍状结构上，该外延层接触鳍状结构的上表面与侧壁以及基底的上表面，其中外延层为倒U型；一浅沟隔离环绕外延层；以及一间隙壁设于浅沟隔离及外延层之间。
附图说明
图1至图6为本发明较佳实施例制作一半导体元件的方法示意图；
图7至图9为本发明一实施例制作一半导体元件的方法示意图；
图10为本发明另一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 第一衬垫层 18 第二衬垫层
20 牺牲层 22 凹槽
24 外延层 26 浅沟隔离
32 间隙壁 34 第一间隙壁
36 第二间隙壁 38 绝缘层
40 凹槽 42 外延层
44 浅沟隔离 46 间隙壁
48 第一间隙壁 50 第二间隙壁
52 浅沟隔离
具体实施方式
请参照图1至图6，图1至图6为本发明较佳实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，然后形成至少一鳍状结构14于基底上。
依据本发明的较佳实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)等技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
然后形成一第一衬垫层16于基底12并完全覆盖鳍状结构14，形成一第二衬垫层18于第一衬垫层16表面，再形成一牺牲层20于第二衬垫层18上。在本实施例中，第一衬垫层16与第二衬垫层18较佳包含不同材料，例如本实施例的第一衬垫层16包含氧化硅，第二衬垫层18包含氮化硅，牺牲层20包含氧化硅，但不局限于此。
如图2所示，接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)制作工艺去除部分牺牲层20，由此暴露出第二衬垫层18表面并使第二衬垫层18上表面切齐剩余的牺牲层20上表面。
然后如图3所示，进行至少一道蚀刻制作工艺，例如利用干蚀刻依序去除部分第二衬垫层18与部分第一衬垫层16并暴露出鳍状结构14上表面。需注意的是，由于本实施例的第一衬垫层16与牺牲层20包含相同材料，因此在去除部分第一衬垫层16的时候部分牺牲层20也较佳被去除，使剩余的牺牲层20上表面略低于第二衬垫层18上表面并切齐第一衬垫层16上表面。
如图4所示，接着进行一蚀刻制作工艺，例如利用稀释氢氟酸(dilutedhydrofluoric acid,dHF)或SiCoNi等蚀刻溶液去除剩余的牺牲层20以及鳍状结构14与第二衬垫层18之间的部分第一衬垫层16，使剩余的第一衬垫层16边缘切齐第二衬垫层18边缘。至此形成一凹槽22于鳍状结构14与第二衬垫层18之间，其中凹槽22剖面较佳为倒U型且暴露出部分基底12表面。需注意的是，由于本实施例的牺牲层20与第一衬垫层16均由氧化硅所构成，因此进行前述蚀刻制作工艺时较佳同时去除所有剩余的牺牲层20与部分第一衬垫层16，由此暴露出第二衬垫层18上表面并同时形成倒U型的凹槽22。
随后如图5所示，进行一外延成长制作工艺以形成一外延层24并填满凹槽22，其中外延层24较佳作为后续鳍状结构晶体管的通道，且外延层24可依据后续所制备晶体管元件的型式而有所不同，例如可包含锗化硅或磷化硅等。另外需注意的是，本实施例的外延层24虽较佳在成长过程中通过调整制作工艺参数的方式使外延层24填满凹槽22后直接与旁边的第二衬垫层18顶部切齐，但又可选择进行另一平坦化制作工艺，例如利用CMP去除部分外延层24，使外延层24上表面切齐第二衬垫层18上表面，此实施例也属本发明所涵盖的范围。
如图6所示，之后利用蚀刻方式完全去除第二衬垫层18与第一衬垫层16并暴露出约略倒U型的外延层24。然后进行一浅沟隔离制作工艺，例如可先沉积一绝缘层(图未示)于基底12上并完全覆盖外延层24，接着进行一平坦化制作工艺，例如以CMP去除部分绝缘层使倒U型外延层24上表面稍低于绝缘层上表面。最后再以蚀刻方式去除部分绝缘层，使剩余绝缘层上表面低于外延层24上表面以形成浅沟隔离26。之后可进行后续鳍状结构晶体管制作工艺，例如可形成栅极结构(图未示)于鳍状结构14上，以及于栅极结构两侧的鳍状结构中形成源极/漏极区域等。至此即完成本发明较佳实施例一半导体元件的制作。
需注意的是，依据本发明一实施例，又可选择在图4去除部分第一衬垫层16形成凹槽22时不去除所有的牺牲层20，等到图6再去部分牺牲层20直接形成浅沟隔离26，如此即可省略一道额外形成浅沟隔离的步骤。
请参照图7至图9，图7至图9为本发明一实施例制作一半导体元件的方法示意图。如图7所示，本发明可于图1形成第一衬垫层16与第二衬垫层18后便直接进行一回蚀刻制作工艺，以于鳍状结构14侧壁形成间隙壁32。其中间隙壁32更细部包含一第一间隙壁34与第二间隙壁36。在此阶段接触鳍状结构14侧壁的第一间隙壁34较佳为L型，而第二间隙壁36则跨在L型的第一间隙壁34上且为一字型。
如图8所示，接着可先形成一绝缘层38于基底12上并覆盖间隙壁32与鳍状结构14，然后进行一平坦化制作工艺，例如以CMP去除部分绝缘层38并使鳍状结构14上表面切齐绝缘层38上表面。接着去除部分第一间隙壁34，使剩余的第一间隙壁34边缘切齐第二间隙壁36边缘，并同时于鳍状结构14与间隙壁32之间形成凹槽40。需注意的是，在去除部分第一间隙壁34的同时第二间隙壁36旁的绝缘层38可能被部分去除，使所剩余的绝缘层38上表面略低于鳍状结构14顶部但仍设于间隙壁32旁的基底12上。
如图9所示，然后进行一外延成长制作工艺，以形成一约略倒U型的外延层42于凹槽40内。最后利用蚀刻制作工艺去除部分绝缘层38与部分第二间隙壁36，使绝缘层38与第二间隙壁36上表面切齐并低于外延层42上表面。至此形成一浅沟隔离44于第二间隙壁36旁。
以结构来看，本实施例中的外延层42是位于浅沟隔离44与鳍状结构14之间，而浅沟隔离44与外延层42之间又设有一第一间隙壁34与第二间隙壁36，其中第二间隙壁36设于第一间隙壁34上，第一间隙壁34与第二间隙壁36均为I字型且同时接触两侧的外延层42与浅沟隔离44。
请参照图10，图10为本发明另一实施例制作一半导体元件的方法示意图。如图10所示，本发明可于图5形成外延层24后利用蚀刻制作工艺去除部分第二衬垫层18的垂直部分，由此形成一间隙壁46，其中间隙壁46包含一字型的第一间隙壁48设于基底12表面以及一L型的第二间隙壁50跨在第一间隙壁48上，其中第二间隙壁50的垂直部分上表面略低于外延层24上表面。接着可进行浅沟隔离制作工艺，例如可先沉积一绝缘层(图未示)于基底上12并覆盖间隙壁46与外延层24，然后进行一平坦化制作工艺，例如以CMP去除部分绝缘层并使外延层24上表面切齐绝缘层上表面。最后再以蚀刻方式去除部分绝缘层甚至部分第二间隙壁50形成浅沟隔离52，使剩余浅沟隔离52上表面切齐第二间隙壁50的垂直部分顶部，且浅沟隔离52与第二间隙壁50上表面均低于外延层24与鳍状结构14上表面。
以结构来看，本实施例中的外延层24是位于浅沟隔离52与鳍状结构14之间，而浅沟隔离52与外延层24之间又设有一第一间隙壁48与第二间隙壁50，其中第二间隙壁50设于第一间隙壁48上，第一间隙壁48为一字型而第二间隙壁50则为L型。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，包含：
形成一鳍状结构于一基底上；
形成一第一衬垫层于该基底及该鳍状结构上；
形成一第二衬垫层于该第一衬垫层上；
去除部分该第二衬垫层及部分该第一衬垫层并暴露出该鳍状结构的上表面；
去除该鳍状结构及该第二衬垫层之间的部分该第一衬垫层以形成一凹槽；以及
形成一外延层于该凹槽内。
2.如权利要求1所述的方法，另包含：
形成一牺牲层于该第二衬垫层上；
平坦化部分该牺牲层；
去除部分该第二衬垫层及部分该第一衬垫层并暴露出该鳍状结构的上表面；以及
去除部分该第一衬垫层及该牺牲层以形成该凹槽。
3.如权利要求2所述的方法，其中该牺牲层包含氧化硅。
4.如权利要求1所述的方法，另包含：
去除该鳍状结构及该第二衬垫层之间的部分该衬垫层并使剩余的该第一衬垫层的边缘切齐该第二衬垫层的边缘。
5.如权利要求1所述的方法，其中该凹槽暴露部分该基底表面。
6.如权利要求1所述的方法，其中该凹槽为倒U型。
7.如权利要求1所述的方法，另包含：
平坦化部分该外延层并使该外延层上表面切齐该第二衬垫层上表面；以及
完全去除该第二衬垫层及该第一衬垫层。
8.如权利要求1所述的方法，其中该外延层为倒U型。
9.如权利要求1所述的方法，其中该第一衬垫层及该第二衬垫层包含不同材料。
10.如权利要求1所述的方法，其中该第一衬垫层包含氧化硅。
11.如权利要求1所述的方法，其中该第二衬垫层包含氮化硅。
12.一种半导体元件，包含：
基底；
鳍状结构设于该基底上；
外延层设于该鳍状结构上，该外延层接触该鳍状结构的上表面与侧壁以及该基底的上表面，其中该外延层为倒U型；以及
浅沟隔离环绕该外延层，其中该浅沟隔离直接接触该基底。
13.如权利要求12所述的半导体元件，其中该外延层位于该浅沟隔离及该鳍状结构之间。
14.如权利要求12所述的半导体元件，另包含一间隙壁设于该浅沟隔离及该外延层之间。
15.如权利要求14所述的半导体元件，其中该间隙壁接触该浅沟隔离、该外延层及该基底。
16.一种半导体元件，包含：
基底；
鳍状结构设于该基底上；
外延层设于该鳍状结构上，该外延层接触该鳍状结构的上表面与侧壁以及该基底的上表面，其中该外延层为倒U型；
浅沟隔离环绕该外延层；以及
间隙壁设于该浅沟隔离及该外延层之间。
17.如权利要求16所述的半导体元件，其中该间隙壁接触该浅沟隔离、该外延层及该基底。
18.如权利要求16所述的半导体元件，其中该间隙壁包含：
第一间隙壁设于该基底上；以及
第二间隙壁设于该第一间隙壁上，其中该第二间隙壁为L型。
19.如权利要求18所述的半导体元件，其中该第一间隙壁为一字型。
20.如权利要求18所述的半导体元件，其中该第一间隙壁及该第二间隙壁包含不同材料。
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