TWI745365B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI745365B
TWI745365B TW106109701A TW106109701A TWI745365B TW I745365 B TWI745365 B TW I745365B TW 106109701 A TW106109701 A TW 106109701A TW 106109701 A TW106109701 A TW 106109701A TW I745365 B TWI745365 B TW I745365B
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fin structure
fin
epitaxial layer
sidewall
semiconductor device
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TW106109701A
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TW201835982A (zh
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李一凡
胡益誠
陳俊仁
吳典逸
林鈺書
吳俊元
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聯華電子股份有限公司
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Priority to US15/496,000 priority patent/US10056490B1/en
Priority to US16/036,831 priority patent/US10446447B2/en
Publication of TW201835982A publication Critical patent/TW201835982A/zh
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Abstract

本發明較佳揭露一種製作半導體元件的方法。首先形成一鰭狀結構於一基底上，然後形成一淺溝隔離於鰭狀結構旁並同時將鰭狀結構定義出一上半部以及一下半部且淺溝隔離較佳環繞鰭狀結構下半部。接著形成一襯墊層於鰭狀結構上半部，然後進行一蝕刻製程完全去除襯墊層以及部分鰭狀結構並使鰭狀結構上半部之一側壁包含一曲面。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於鰭狀結構側壁形成曲面的方法。
隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體元件在同 樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構的形成仍存在許多瓶頸，進而影響整個元件的漏電流及整體電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一鰭狀結構於一基底上，然後形成一淺溝隔離於鰭狀結構旁並同時將鰭狀結構定義出一上半部以及一下半部且淺溝隔離較佳環繞鰭狀結構下半部。接著形成一襯墊層於鰭狀結構上半部，然後進行一蝕刻製程完全去除襯墊層以及部分鰭狀結構並使鰭狀結構上半部之一側壁包含一曲面。
本發明另一實施例揭露一種半導體元件，其主要包含一鰭狀結構設於一基底上，其中鰭狀結構之一側壁包含一曲面。
本發明又一實施例揭露一種半導體元件，其主要包含一鰭狀結構設於一基底上以及一磊晶層環繞鰭狀結構，其中磊晶層之一側壁包含波浪面。
12:基底
14:鰭狀結構
16:淺溝隔離
18:上半部
20:下半部
22:襯墊層
24:曲面
26:平坦部
28:彎曲部
30:磊晶層
32:側壁
34:內側壁
36:外側壁
38:平坦部
40:彎曲部
42:閘極結構
44:磊晶層
46:波浪面
d1:距離
d2:距離
第1圖至第5圖為本發明第一實施例製作一半導體元件之方法示意圖。
第6圖為本發明第二實施例製作一半導體元件之方法示意圖。
請參照第1圖至第4圖，第1圖至第4圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，然後形成至少一鰭狀結構14於基底上12。
依據本發明之較佳實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer,SIT)等技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案 轉移至基底12中以形成鰭狀結構14。另外，鰭狀結構14之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構14。這些形成鰭狀結構14的實施例均屬本發明所涵蓋的範圍。
然後形成一淺溝隔離(shallow trench isolation,STI)16環繞鰭狀結構14，並藉此將鰭狀結構14定義或分隔為兩部分，包括上半部18與下半部20而淺溝隔離16較佳環繞鰭狀結構14的下半部20。在本實施例中，形成淺溝隔離16的方式可先利用一可流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)製程形成一氧化矽層於基底12上並完全覆蓋鰭狀結構14。接著利用化學機械研磨(chemical mechanical polishing,CMP)製程並搭配蝕刻去除部分氧化矽層，使剩餘的氧化矽層低於鰭狀結構14表面以形成淺溝隔離16。
然後進行一熱氧化製程以形成一襯墊層22於基底12並完全覆蓋鰭狀結構14上半部18，包括上半部18的側壁與上表面。在本實施例中，襯墊層22較佳包含氧化矽，但不侷限於此。
如第2圖所示，接著去除襯墊層22與部分該鰭狀結構14並使鰭狀結構14的側壁32包含一曲面24。更具體而言，本實施例較佳在不形成任何圖案化遮罩的情況下進行一蝕刻製程，其中所使用的蝕刻氣體較佳完全去除襯墊層22以及部分鰭狀結構14上半部18。在本實施例中，所使用的蝕刻氣體係選自由甲烷(CH4)以及二氟甲烷(CH2F2)所構 成的群組且蝕刻製程所使用的功率較佳介於300瓦至500瓦。
值得注意的是，由於本發明所使用蝕刻氣體的蝕刻對象物同時包含由矽所構成的鰭狀結構14以及由氧化物所構成的襯墊層22，因此利用上述之氣體組合並搭配蝕刻功率的調整本發明可在完全去除襯墊層22的情況下同時使剩餘鰭狀結構14上半部18的左右側壁32形成對稱曲面24。由於鰭狀結構14下半部20周圍在蝕刻之前便已被淺溝隔離16完全環繞，因此下半部20的左右側壁32在蝕刻的過程中較佳完全不受蝕刻氣體的影響而呈現原本約略傾斜但平坦的態樣。
若從細部來看，左右側壁32的曲面24各包含一平坦部26由鰭狀結構14上半部18的上表面向下延伸以及一彎曲部28由鰭狀結構14上半部18的下表面向上延伸。
另外需注意的是，由於蝕刻製程在去除襯墊層22的過程中會同時去除部分鰭狀結構14，因此第2圖中剩餘的鰭狀結構14上半部18的上表面較佳略低於第1圖中未進行蝕刻之前的鰭狀結構14上半部18的上表面。
請參照第3圖至第4圖，如第3圖至第4圖所示，接著進行一磊晶成長製程以形成一磊晶層30於鰭狀結構14側壁32，其中磊晶層30較佳覆蓋鰭狀結構14上半部18的側壁32但不形成於上半部18的上表面。
在本實施例中，磊晶層30較佳包含鍺化矽，而用來形成磊晶 層30所通入的氣體較佳包含兩種組合，其中一氣體組合可選自由二氯矽甲烷(dichlorosilane,DCS)、甲鍺烷(GeH4)以及鹽酸(HCl)所構成的群組，另一氣體組合則可選自由甲矽烷(SiH4)、甲鍺烷(GeH4)以及鹽酸(HCl)所構成的群組。另外本實施例在通入上述氣體組合的任何一者時溫度較佳控制介於攝氏500度至攝氏700度或最佳約攝氏500度，壓力較佳控制介於10托(Torr)至50托或最佳約10托，鍺濃度較佳介於20%至75%，且最後所形成由鍺化矽所構成的磊晶層30厚度較佳約介於5埃至100埃。
值得注意的是，如第3圖所示，本發明通入上述氣體組合中的任何一種組合形成磊晶層30時較佳先於鰭狀結構14上半部18的側壁32形成具有傾斜側壁的磊晶層30且鰭狀結構14頂部不會形成任何磊晶層30，接著再如第4圖所示，繼續通入相同氣體組合使磊晶層30向外側擴張成長，進而形成具有弧面的磊晶層30，其中磊晶層30較佳包含一內側壁34重疊鰭狀結構14上半部18之側壁32以及另一外側壁36相對於內側壁34。
在本實施例中，由於磊晶層30的內側壁34與鰭狀結構14的側壁32完全重疊，因此磊晶層30的內側壁34同樣包含平坦部26由鰭狀結構14上半部18的上表面向下延伸以及一彎曲部28由鰭狀結構14上半部18的下表面向上延伸。相對於內側壁34的外側壁36則包含一平坦部38由鰭狀結構14上半部18的下表面向上延伸以及一彎曲部40由鰭狀結構14上半部18的上表面向下延伸。
隨後如第5圖所示，可進行後續鰭狀結構電晶體製程，例如可依據製程需求形成一由例如多晶矽所構成的閘極結構42於基底12上並橫跨鰭狀結構14，然後可於閘極結構42側壁形成側壁子，於側壁子兩側的鰭狀結構內形成源極/汲極區域，形成層間介電層覆蓋閘極結構，甚至進行金屬閘極置換製程將閘極結構轉換為金屬閘極。至此即完成本發明第一實施例之一半導體元件的製作。
請接著參照第6圖，第6圖為本發明第二實施例製作一半導體元件之方法示意圖。如第6圖所示，首先如第1圖般先形成鰭狀結構14於基底12上，然後形成一淺溝隔離(STI)16環繞鰭狀結構14並藉此將鰭狀結構定義或分隔為兩部分，包括上半部18與下半部20而淺溝隔離16較佳環繞鰭狀結構14的下半部20。
接著省略第2圖中形成襯墊層22以及省略利用蝕刻將鰭狀結構14上半部18的側壁32形成曲面的步驟，改直接以第3圖所通入的氣體進行磊晶成長製程以形成磊晶層44於鰭狀結構14側壁32。
如同前述實施例，磊晶層44較佳包含鍺化矽，本實施例用來形成磊晶層44所通入的氣體較佳包含兩種組合，其中一氣體組合可選自由二氯矽甲烷(dichlorosilane,DCS)、甲鍺烷(GeH4)以及鹽酸(HCl)所構成的群組，另一氣體組合則可選自由甲矽烷(SiH4)、甲鍺烷(GeH4)以及鹽酸(HCl)所構成的群組。另外本實施例在通入上述氣體組合的任何一者時溫度較佳控制介於攝氏500度至攝氏700度或最佳約攝氏500度，壓力較佳控制介於10托(Torr)至50托或最佳約10托，鍺濃度較佳介 於20%至75%，且最後所形成由鍺化矽所構成的磊晶層厚度較佳約介於5埃至100埃。
需注意的是，雖然經由上述氣體組成所形成的磊晶層44同樣設置於鰭狀結構14上半部18的側壁32，但由於成長的上半部18的側壁32並未如前述實施例般具有曲面24，因此本實施例所形成的磊晶層44較佳具有約略波浪狀的輪廓或一波浪面46。
更具體而言，鰭狀結構14上半部18的側壁32呈現約略傾斜且平坦的表面，磊晶層44較佳環繞鰭狀結構14上半部18的側壁32及上表面，其中磊晶層44的整體厚度約略介於10埃至200埃，而磊晶層44最厚處與最薄處約介於5埃至100埃，例如圖中所示之最薄處距離d1約為10埃而最厚處距離d2約50埃。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
14:鰭狀結構
16:淺溝隔離
18:上半部
20:下半部
26:平坦部
28:彎曲部
30:磊晶層
32:側壁
34:內側壁
36:外側壁
38:平坦部
40:彎曲部

Claims (18)

  1. 一種製作半導體元件的方法，包含：形成一鰭狀結構於一基底上；形成一淺溝隔離於該鰭狀結構旁；去除部分該鰭狀結構並使該鰭狀結構之一側壁包含一曲面；於該鰭狀結構上表面暴露出來的情況下形成一磊晶層於該鰭狀結構之該側壁，其中該磊晶層包括鍺化矽並且環繞該鰭狀結構；以及形成一閘極結構橫跨該鰭狀結構並覆蓋該鰭狀結構之該側壁上的該磊晶層。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一襯墊層於該鰭狀結構上；以及去除該襯墊層以及部分該鰭狀結構以形成該曲面。
  3. 如申請專利範圍第2項所述之方法，另包含：利用一蝕刻氣體完全去除該襯墊層以及部分該鰭狀結構，該蝕刻氣體係選自由甲烷(CH4)以及二氟甲烷(CH2F2)所構成的群組。
  4. 如申請專利範圍第2項所述之方法，另包含：其中該襯墊層包含氧化矽。
  5. 如申請專利範圍第1項所述之方法，其中形成該磊晶層之氣體係選自由二氯矽甲烷(dichlorosilane,DCS)、甲鍺烷(GeH4)以及鹽酸 (HCl)所構成的群組。
  6. 如申請專利範圍第1項所述之方法，其中形成該磊晶層之氣體係選自由甲矽烷(SiH4)、甲鍺烷(GeH4)以及鹽酸(HCl)所構成的群組。
  7. 如申請專利範圍第1項所述之方法，其中該磊晶層包含一內側壁重疊該鰭狀結構之該側壁以及一外側壁相對於該內側壁。
  8. 如申請專利範圍第7項所述之方法，其中該外側壁包含一平坦部由該鰭狀結構下表面向上延伸以及一彎曲部由該鰭狀結構上表面向下延伸。
  9. 如申請專利範圍第1項所述之方法，其中該曲面包含一平坦部由該鰭狀結構上表面向下延伸以及一彎曲部由該鰭狀結構下表面向上延伸。
  10. 一種半導體元件，包含：一鰭狀結構設於一基底上，其中該鰭狀結構之一側壁包含一曲面；以及一磊晶層位於該鰭狀結構之該側壁上並且包括鍺化矽並且環繞該鰭狀結構；以及一閘極結構橫跨該鰭狀結構並覆蓋該側壁上之該磊晶層。
  11. 如申請專利範圍第10項所述之半導體元件，其中該鰭狀結 構包含一上半部以及一下半部，該半導體元件另包含：一淺溝隔離環繞該鰭狀結構之該下半部，其中該上半部之側壁包含該曲而。
  12. 如申請專利範圍第11項所述之半導體元件，其中該曲面包含一平坦部由該鰭狀結構上表面向下延伸以及一彎曲部由該鰭狀結構下表面向上延伸。
  13. 如申請專利範圍第10項所述之半導體元件，其中該磊晶層包含一內側壁重疊該鰭狀結構之該側壁以及一外側壁相對於該內側壁。
  14. 如申請專利範圍第13項所述之半導體元件，其中該外側壁包含一平坦部由該鰭狀結構下表面向上延伸以及一彎曲部由該鰭狀結構上表面向下延伸。
  15. 一種半導體元件，包含：一鰭狀結構設於一基底上；一磊晶層位於該鰭狀結構之一側壁上並且包括鍺化矽並且環繞該鰭狀結構，該磊晶層之一側壁包含一波浪面；以及一閘極結構橫跨該鰭狀結構並且覆蓋該鰭狀結構之該側壁上的該磊晶層。
  16. 如申請專利範圍第15項所述之半導體元件，其中該鰭狀結 構包含一上半部以及一下半部，該半導體元件另包含：一淺溝隔離環繞該鰭狀結構之該下半部。
  17. 如申請專利範圍第16項所述之半導體元件，其中該磊晶層係環繞該鰭狀結構之該上半部之側壁及上表面。
  18. 如申請專利範圍第16項所述之半導體元件，其中該鰭狀結構之該上半部之側壁包含一平坦表面。
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TW201336076A (zh) * 2012-02-29 2013-09-01 Taiwan Semiconductor Mfg 鰭式場效應電晶體裝置及其形成方法
US20160218180A1 (en) * 2015-01-27 2016-07-28 Jung-Gun You Methods for fabricating semiconductor devices having fin-shaped patterns

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