CN105489494B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

Info

Publication number
CN105489494B
CN105489494B CN201410527948.2A CN201410527948A CN105489494B CN 105489494 B CN105489494 B CN 105489494B CN 201410527948 A CN201410527948 A CN 201410527948A CN 105489494 B CN105489494 B CN 105489494B
Authority
CN
China
Prior art keywords
fin structure
remaining
fin
layer
shallow trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410527948.2A
Other languages
English (en)
Other versions
CN105489494A (zh
Inventor
李镇全
吕水烟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201410527948.2A priority Critical patent/CN105489494B/zh
Priority to US14/533,105 priority patent/US9502259B2/en
Publication of CN105489494A publication Critical patent/CN105489494A/zh
Application granted granted Critical
Publication of CN105489494B publication Critical patent/CN105489494B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

本发明公开一种半导体元件及其制作方法。其制作方法包括：首先提供一基底，然后形成一鳍状结构于基底上、形成一遮盖层于鳍状结构上、去除鳍状结构上方的部分遮盖层、去除部分鳍状结构、去除剩余的遮盖层以及去除部分剩余的鳍状结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用两段式蚀刻方式去除部分鳍状结构的方法。
背景技术
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effecttransistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现有鳍状场效晶体管元件制作工艺中，去除部分鳍状结构后形成凹槽以进行后续外延层成长的标准制作工艺时常因过渡蚀刻鳍状结构而使鳍状结构略低于周围的浅沟隔离，影响后续外延层的成长。因此如何改良现有鳍状场效晶体管制作工艺以改良前述缺点即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成一鳍状结构于基底上、形成一遮盖层于鳍状结构上、去除鳍状结构上方的部分遮盖层、去除部分鳍状结构、去除剩余的遮盖层以及去除部分剩余的鳍状结构。
本发明另一实施例公开一种半导体元件，其包含一基底以及一具有一上半部与一下半部的鳍状结构设于基底上，其中下半部的上表面大于上半部的下表面。
附图说明
图1至图7为本发明的一优选实施例所绘示的半导体装置的制作方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 浅沟隔离 18 遮盖层
20 凹槽 22 聚合物层
24 上半部 26 下半部
28 鳍状结构 30 内凹弧面
32 凹槽 34 栅极结构
36 外延层
具体实施方式
请参照图1至图7，图1至图7是根据本发明的一优选实施例所绘示的半导体装置的制作方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon oninsulator,SOI)基板，然后形成至少一鳍状结构14于基底12上，并接着形成一浅沟隔离(shallow trench isolation,STI)16环绕鳍状结构14。在本实施例中，鳍状结构14虽以四根为例，但其数量并不以此为限，可依据产品需求进行调整，例如可形成一根或一根以上的鳍状结构14于基底12上。
另外依据本发明的优选实施例，鳍状结构(fin structure)14优选通过侧壁图案转移(sidewall image transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
接着可依序进行栅极结构以及源极/漏极区域等相关制作工艺，例如可于基底12上形成栅极结构(图未示)，在栅极结构两侧的鳍状结构14中形成轻掺杂漏极(图未示)，形成间隙壁(图未示)于栅极结构侧壁，并于间隙壁两侧的鳍状结构14中形成轻掺杂漏极(图未示)与源极/漏极区域(图未示)等元件。然后全面性形成一遮盖层18于前述栅极结构等元件以及浅沟隔离16与鳍状结构14上，其中遮盖层18优选覆盖整个鳍状结构14与周围的浅沟隔离16。在本实施例中，遮盖层18优选由氮化硅所构成，但不局限于此。
如图2所示，接着进行一蚀刻制作工艺去除鳍状结构14上方的部分遮盖层18及浅沟隔离16上的部分遮盖层18，由此暴露出鳍状结构14顶部及部分浅沟隔离16表面。需注意的是，本实施例形成遮盖层18与去除部分遮盖层18的动作优选搭配基底12上的不同晶体管区。举例来说，本发明于图1所形成的遮盖层18优选同时覆盖于基底12上的NMOS晶体管区(图未示)与PMOS晶体管区(图未示)，然后于图2去除部分遮盖层18时，优选先以图案化光致抗蚀剂(图未示)覆盖晶体管区的其中一者，例如NMOS晶体管区后再以蚀刻制作工艺去除PMOS晶体管区的部分遮盖层。由于以图案化光致抗蚀剂进行上述图案转移乃此领域所熟知技术，在此不另加赘述。
随后如图3所示，进行另一蚀刻制作工艺去除部分鳍状结构14，且在不去除任何遮盖层18的情况下形成一凹槽20，并使剩余的鳍状结构14上表面高于浅沟隔离16上表面。在本阶段，去除部分鳍状结构14时优选采用由溴化氢(HBr)所组成的蚀刻气体，但不局限于此。
接着如图4所示，再进行一蚀刻制作工艺去除剩余的遮盖层18并同时形成一聚合物层22于剩余的鳍状结构14上，其中聚合物层主要由长碳链为主，并同时包含氟所构成的聚合物。在本实施例中，去除剩余遮盖层18并同时形成聚合物层22所采用的蚀刻气体优选选自由氟甲烷(CH3F)、二氟甲烷(CH2F2)、甲烷(CH4)所构成的群组。更具体而言，由于本实施例优选采用含有氟的蚀刻气体进行上述蚀刻，因此所使用的蚀刻气体组成可包含氟甲烷(CH3F)及甲烷(CH4)、二氟甲烷(CH2F2)及甲烷(CH4)，甚至氟甲烷(CH3F)、二氟甲烷(CH2F2)以及甲烷(CH4)三者。
之后如图5及图6所示，进行另一蚀刻制作工艺，去除聚合物层22及部分剩余的鳍状结构14以于栅极结构34两侧形成一用来形成后续外延层的凹槽32，其中去除聚合物层22及部分剩余鳍状结构14的蚀刻气体优选选自由氯(Cl)及三氟化碳(NF3)所组成的群组。值得注意的是，本实施例以上述蚀刻气体去除聚合物层22与部分鳍状结构14后优选形成一具有一上半部24及下半部26的鳍状结构28。其中上半部24包含两个相对设置的内凹弧面(concave curve)30，或以另一角度看，上半部24包含二斜边，且该二斜边的斜率不同于下半部26。另外以整体结构来看，鳍状结构28下半部26的上表面优选大于上半部24的下表面，且下半部26上表面或上半部24下表面优选与浅沟隔离16的上表面齐平。
待去除部分剩余的鳍状结构28后可依据制作工艺需求进行一含氧等离子体清洗制作工艺完全去除任何残留的聚合物层22并同时去除另一晶体管区，如前述NMOS晶体管区的图案化光致抗蚀剂。接着如图7所示，在鳍状结构28上形成外延层36，然后可进行后续鳍状场效晶体管的标准制作工艺，例如可形成金属硅化物以及接触插塞等元件，在此不另加赘述。
综上所述，本发明优选公开一种以多段式蚀刻去除部分鳍状结构的方法，其主要于移除部分遮盖层并暴露出鳍状结构上表面后先以由溴化氢所构成的蚀刻气体去除部分鳍状结构，接着以含氟的蚀刻气体去除遮盖层并同时于鳍状结构上成长出一聚合物层，之后再以含有氯(Cl)及三氟化碳(NF3)的蚀刻气体去除聚合物层并同时形成一具有上下两部分且分别具有不同斜率的鳍状结构。通过多段式蚀刻来去除部分鳍状结构以形成后续外延层所需的凹槽，本发明可避免鳍状结构受到过渡蚀刻并可同时提升外延层的成长品质。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (11)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一鳍状结构于该基底上；
形成浅沟隔离环绕该鳍状结构；
形成一遮盖层于该鳍状结构上；
去除该鳍状结构上方的部分该遮盖层；
去除部分该鳍状结构，使剩余的该鳍状结构的上表面高于该浅沟隔离的上表面；
去除剩余的该遮盖层并同时形成一聚合物层于剩余的该鳍状结构上；以及
去除该聚合物层及部分剩余的该鳍状结构。
2.如权利要求1所述的方法，包含：
形成一浅沟隔离于该鳍状结构周围；
形成该遮盖层于该浅沟隔离及该鳍状结构上；
去除该鳍状结构上的部分该遮盖层及该浅沟隔离上的部分该遮盖层；以及
去除部分该鳍状结构使剩余的该鳍状结构的上表面高于该浅沟隔离的上表面。
3.如权利要求2所述的方法，还包含利用一气体来去除聚合物层及部分剩余的该鳍状结构，且该气体选自由氯(Cl)及三氟化碳(NF3)所组成的群组。
4.如权利要求2所述的方法，还包含去除该聚合物层及部分剩余的该鳍状结构以形成具有一上半部及一下半部的鳍状结构。
5.如权利要求4所述的方法，其中该下半部的上表面大于该上半部的下表面。
6.如权利要求4所述的方法，其中该上半部包含二相对设置的内凹弧面(concavearc)。
7.如权利要求1所述的方法，还包含利用溴化氢来去除部分该鳍状结构。
8.如权利要求1所述的方法，还包含利用一气体来去除剩余的该遮盖层，且该气体选自由氟甲烷(CH3F)、二氟甲烷(CH2F2)、甲烷(CH4)所构成的群组。
9.如权利要求1所述的方法，其中该遮盖层包含氮化硅。
10.如权利要求1所述的方法，其中该聚合物层包含氟。
11.如权利要求1所述的方法，还包含于去除部分剩余的鳍状结构后进行一含氧等离子体清洗制作工艺。
CN201410527948.2A 2014-10-09 2014-10-09 半导体元件及其制作方法 Active CN105489494B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410527948.2A CN105489494B (zh) 2014-10-09 2014-10-09 半导体元件及其制作方法
US14/533,105 US9502259B2 (en) 2014-10-09 2014-11-05 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410527948.2A CN105489494B (zh) 2014-10-09 2014-10-09 半导体元件及其制作方法

Publications (2)

Publication Number Publication Date
CN105489494A CN105489494A (zh) 2016-04-13
CN105489494B true CN105489494B (zh) 2020-03-31

Family

ID=55655954

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410527948.2A Active CN105489494B (zh) 2014-10-09 2014-10-09 半导体元件及其制作方法

Country Status (2)

Country Link
US (1) US9502259B2 (zh)
CN (1) CN105489494B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102437295B1 (ko) * 2015-11-09 2022-08-30 삼성전자주식회사 반도체 소자의 제조 방법
US9691758B1 (en) * 2016-03-11 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type resistor
US9945618B1 (en) * 2017-01-04 2018-04-17 Wieland Copper Products, Llc Heat transfer surface
CN109390397B (zh) 2017-08-03 2023-03-10 联华电子股份有限公司 半导体元件及其制作方法
CN111900162B (zh) * 2020-07-31 2023-10-13 中国科学院微电子研究所 一种量子点器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050533A (zh) * 2011-10-14 2013-04-17 台湾积体电路制造股份有限公司 用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺
CN103681347A (zh) * 2012-08-30 2014-03-26 台湾积体电路制造股份有限公司 制造FinFET器件的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7678648B2 (en) 2006-07-14 2010-03-16 Micron Technology, Inc. Subresolution silicon features and methods for forming the same
CN100498187C (zh) * 2007-01-15 2009-06-10 高克联管件(上海)有限公司 一种蒸发冷凝兼备型传热管
US9844807B2 (en) * 2008-04-16 2017-12-19 Wieland-Werke Ag Tube with fins having wings
US8313999B2 (en) * 2009-12-23 2012-11-20 Intel Corporation Multi-gate semiconductor device with self-aligned epitaxial source and drain
US8871575B2 (en) 2011-10-31 2014-10-28 United Microelectronics Corp. Method of fabricating field effect transistor with fin structure
US8883570B2 (en) * 2012-07-03 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate FETs and methods for forming the same
US9159832B2 (en) * 2013-03-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050533A (zh) * 2011-10-14 2013-04-17 台湾积体电路制造股份有限公司 用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺
CN103681347A (zh) * 2012-08-30 2014-03-26 台湾积体电路制造股份有限公司 制造FinFET器件的方法

Also Published As

Publication number Publication date
US20160104627A1 (en) 2016-04-14
US9502259B2 (en) 2016-11-22
CN105489494A (zh) 2016-04-13

Similar Documents

Publication Publication Date Title
KR101802715B1 (ko) 반도체 디바이스의 제조 방법
US8936986B2 (en) Methods of forming finfet devices with a shared gate structure
US10134761B2 (en) Semiconductor device and FinFET transistor
US9553025B2 (en) Selective Fin-shaping process
KR101637679B1 (ko) Ｆⅰｎｆｅｔ을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법
TWI500154B (zh) 半導體裝置、電晶體及其形成方法
US8716764B2 (en) Semiconductor device and manufacturing method thereof
CN105489494B (zh) 半导体元件及其制作方法
US10319597B2 (en) Semiconductor device with particular fin-shaped structures and fabrication method thereof
US9378973B1 (en) Method of using sidewall image transfer process to form fin-shaped structures
US10497810B2 (en) Method for fabricating semiconductor device
CN112802901A (zh) 半导体元件及其制作方法
CN110010684B (zh) 半导体元件及其制作方法
CN109830462B (zh) 制作半导体元件的方法
US20230197451A1 (en) Semiconductor device and method for fabricating the same
CN108630544B (zh) 半导体元件及其制作方法
CN106409748B (zh) 半导体元件及其制作方法
TWI703732B (zh) 一種製作半導體元件的方法
TWI707403B (zh) 半導體元件及其製作方法
US20170133460A1 (en) Semiconductor structure and manufacturing method thereof
CN107275399B (zh) 半导体元件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant