CN103681347A - 制造FinFET器件的方法 - Google Patents

制造FinFET器件的方法 Download PDF

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CN103681347A
CN103681347A CN201210580950.7A CN201210580950A CN103681347A CN 103681347 A CN103681347 A CN 103681347A CN 201210580950 A CN201210580950 A CN 201210580950A CN 103681347 A CN103681347 A CN 103681347A
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fin
substrate
finfet
fin formula
fluting groove
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CN103681347B (zh
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巫凯雄
曾博瑞
简珮珊
曾伟雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本方面公开了一种制造鳍式场效应晶体管的方法。制造FinFET器件，首先要接收FinFET前体。该前体包括衬底和衬底上的鳍式结构。沿着前体中的鳍式结构的侧壁可形成侧壁间隔件。对鳍式结构的一部分开槽，以形成将侧壁间隔件作为鳍上部的开槽沟槽。半导体结构外延生长在开槽沟槽中且在开槽沟槽的上方持续生长，以形成外延结构。

Description

制造FinFET器件的方法
技术领域
本申请总体涉及半导体领域，更具体地，涉及制造FinFET器件的方法。
背景技术
半导体集成电路(IC)行业发展迅速。由于IC材料和设计在技术上的进步，使得IC不断地更新换代，新一代IC比前一代IC具有更小但更复杂的电路。在IC的发展过程中，通常增大了功能密度(即，在每个芯片区域内互连器件的数量)，但缩小了几何尺寸(即，通过制造工艺可以得到的最小部件(或线))。这种按比例缩小工艺的优点在于提高了生产效率和降低了相关成本。
这种按比例缩小工艺也增强了IC的加工和制造的复杂度。为了实现这些进步，我们需要IC加工和制造方面也要有相似的发展。例如，已经使用三维晶体管，如鳍式场效应晶体管(FinFET)来代替平面晶体管。虽然现有的FinFET器件和制造FinFET器件的方法一般足以实现其预期的使用目的，但是仍无法做到尽善尽美。例如，源级/漏极极外延结构的高度和宽度发生变化，就会给FinFET工艺发展带来挑战。因此，期望在此领域有所改善。
发明内容
为解决上述问题，本发明提供了一种制造鳍式场效应晶体管(FinFET)器件的方法，该方法包括以下步骤：接收FinFET前体，FinFET前体包括：衬底；和鳍式结构，位于衬底上，鳍式结构彼此之间具有间隔距离(S)；沿着鳍式结构的侧壁形成具有预定间隔件高度(Hs)的侧壁间隔件；对鳍式结构开槽以形成开槽沟槽，其中，侧壁间隔件是开槽沟槽的上部；以及在开槽沟槽的上方形成具有高度(H)和宽度(W)的外延结构。
其中，可通过间隔件蚀刻工艺调节间隔件高度(Hs)。
其中，通过在开槽沟槽中的被开槽的鳍上外延生长半导体材料来形成外延结构，外延生长延伸到开槽沟槽的上方以形成外延结构。
其中，通过多次沉积工艺形成外延结构，其中每一次沉积工艺都对应不同的半导体材料。
其中，可通过Hs和固定的S调节W。
其中，可通过Hs和固定的S调节H。
其中，可通过Hs和固定的S调节两个相邻的外延结构之间的合并间隔(M)。
其中，外延结构包括源级/漏极结构。
该方法进一步包括：在形成外延结构之后，通过选择性蚀刻工艺去除侧壁间隔件。
此外，还提供了一种制造鳍式场效应晶体管(FinFET)器件的方法，该方法包括以下步骤：接收FinFET前体，FinFET前体包括：衬底；鳍式结构，位于衬底上，鳍式结构包括彼此之间具有间隔距离(S)的鳍；隔离区，将鳍隔开；和栅极堆叠件，位于衬底上；沿着鳍式结构的鳍和栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件；去除鳍的一部分以形成开槽沟槽，其中，侧壁间隔件限定开槽沟槽的上部；在开槽沟槽中的被开槽的鳍上外延生长半导体材料；以及持续生长半导体材料，以延伸到开槽沟槽的上方，从而形成外延结构。
其中，通过间隔件蚀刻工艺控制Hs。
其中，外延结构形成有可由Hs调节的宽度(W)。
其中，外延结构形成有可由Hs调节的高度(H)。
其中，相邻的外延结构形成有可由Hs调节的合并间隔(M)。
其中，外延结构的形状具有晶面取向的至少一个切面。
其中，晶面取向是(111)结晶取向。
其中，外延结构具有四个切面，并且四个切面具有(111)结晶取向。
其中，外延结构包括源级/漏极结构。
其中，通过执行多次外延生长工艺利用不同的半导体材料形成外延结构。
此外，提供了一种制造鳍式场效应晶体管(FinFET)器件的方法，该方法包括以下步骤：接收FinFET前体，FinFET前体包括：衬底；鳍式结构，位于衬底上，鳍式结构包括彼此之间具有间隔距离(S)的鳍；隔离区，将鳍隔开；和栅极堆叠件，位于衬底上；沿着鳍和栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件；去除鳍的一部分以形成开槽沟槽，其中，每个开槽沟槽均包括侧壁间隔件作为上部；以及在开槽沟槽的上方形成外延源级/漏极结构，其中，外延源级/漏极结构的宽度和高度可由Hs调节，两个相邻的外延源级/漏极结构之间的合并间隔可由Hs调节。
附图说明
当结合附图进行阅读时，通过下列详细的描述和附图，可以理解本发明的各方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1示出了根据本公开的各方面的制造FinFET器件的实例方法的流程图。
图2示出了根据本公开的各方面的FinFET前体的俯视图。
图3A示出了沿图2中A-A线切割得到的FinFET前体的截面图。
图4A、图5A和图6A示出了沿图2中A-A线切割得到的FinFET器件的截面图。
图3B示出了沿图2中B-B线切割得到的FinFET前体的截面图。
图4B、图5B、图6B、图7A、图7B和图7C示出了沿图2中B-B线切割得到的FinFET器件的截面图。
具体实施方式
以下公开提供了多种不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本公开可以在不同实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
能够从本申请的一个或多个实施例中获益的器件实例是半导体器件。例如，这样的器件是FinFET器件。例如，这种FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)的互补金属氧化物半导体(CMOS)。下文继续以FinFET为例，以示出本申请的不同实施例。然而，应该理解，除非有特殊说明，否则本申请并不用于限制特殊类型的器件。
图1示出了根据本公开的各方面的制造FinFET器件600的方法的流程图。图2示出了FinFET前体200的俯视图。参见图2，沿A-A线和B-B线切割，分别得到FinFET前体200和FinFET器件600的截面图。图3A、图4A、图5A和图6A是沿图2中A-A线切割的截面图。图3B、图4B、图5B、图6B、图7A、图7B和图7C示出了沿图2中B-B线且垂直于A-A线方向的截面图。参见图1到图7，同时介绍了方法100、FinFET前体200和FinFET器件600。应该理解，在方法100之前、之中和之后可以提供附加步骤，并且，在方法的其他实施例中，可以替换或去掉所述的一些附加步骤。
方法100以步骤102为开始，其中，如图2、图3A和图3B所示，接收FinFET前体200。FinFET前体200包括衬底210。衬底210可以是体硅衬底。备选地，衬底210可以包括元素半导体(如晶体结构中的硅或锗)、复合半导体(如硅锗、碳化硅、镓砷、磷化镓、磷化铟、砷化铟，和/或锑化铟)、或其组合。衬底210还可以包括绝缘体上硅(SOI)衬底。通过注氧隔离技术(SIMOX)、晶圆接合和/或其他适合的方法制造SOI衬底。
一些示例性衬底210也包括绝缘层。绝缘层包括任何适合的材料，如，氧化硅、蓝宝石、和/或其组合。示例性绝缘层可以是埋氧层(BOX)。通过任何适合的工艺形成绝缘体，诸如注入(如SIMOX)、氧化、沉积、和/或其他适合工艺。在一些示例性FinFET前体200中，绝缘层是绝缘体上硅衬底的元件(如，层)。
根据现有技术的已知要求，衬底210可以包括各种掺杂区。掺杂区可以掺杂有p型掺杂物(如硼或BF2)、n型掺杂物(如磷或砷)、或其组合。可以通过使用突起结构或直接在P阱结构、N阱结构和双阱结构中的衬底210上形成掺杂区。衬底210还可以进一步包括各种有源区，如为N型金属氧化物半导体晶体管器件配置的区和为P型金属氧化物半导体晶体管器件配置的区。
鳍220形成在衬底210上。在一些实施例中，前体200包括相互之间存在间隔距离(S)的多个鳍220。通过任何适合的工艺(包括各种沉积、光刻、和/或蚀刻工艺)形成鳍220。示例性光刻工艺包括在衬底(如硅层上)的上方形成光刻胶层(抗蚀剂)，将抗蚀剂曝光于图案，进行后曝光烘烤工艺，以及显影抗蚀剂，从而形成包括抗蚀剂的掩模元件(maskingelement)。然后，使用掩模元件将鳍式结构蚀刻入衬底210中。使用反应离子蚀刻(RIE)工艺和/或其他适合的工艺蚀刻不被掩模元件保护的区域。在一个实例中，通过图案化和蚀刻硅衬底210的一部分，以形成硅鳍220。在另一个实例中，通过图案化和蚀刻沉积在绝缘层(例如，SOI衬底的硅-绝缘体-硅堆叠的上硅层)上方的硅层，以形成鳍220。作为代替传统光刻的工艺，通过双图案化光刻(DPL)工艺形成鳍220。DPL是一种通过将图案分为两个交错图形，以在衬底上构建图案的方法。DPL允许增强的功能(例如，鳍)密度。各种DPL方法包括双重曝光(例如，使用两个掩模组)，形成邻近部件的间隔件，然后去除部件以提供间隔件的图案，防冻、和/或其他适合的工艺。应该理解，通过相似的方式可以形成多个平行的鳍式结构220。
在衬底210上形成隔离区230，以将衬底210的有源区隔开，也可进一步用于将鳍220隔开。可以使用传统的隔离技术(如浅沟槽隔离(STI))形成隔离区230，以界定且电隔离各种区。隔离区230包括氧化硅、氮化硅、氮氧化硅、气隙、其他适合的材料、或其组合。通过适合的工艺形成隔离区230。例如，STI的形成包括光刻工艺、蚀刻衬底中沟槽的蚀刻工艺(例如，使用干式蚀刻和/或湿式蚀刻)、以及使用一种或多种介电材料填充沟槽的沉积(例如，使用化学气相沉积工艺)。如本实施例中，可以填充部分的沟槽，其中，沟槽之间残留的衬底形成鳍式结构。在一些实例中，被填充的沟槽可以具有多层结构，如用氮化硅或氧化硅填充的热氧化衬垫层。
一个或多个栅极堆叠件240形成在衬底210的上方以及鳍220的一部分的上方(包裹)。栅极堆叠件240可以包括介电层244、栅电极层246和硬掩模层248。应该理解，栅极堆叠件可以包括附加层，如界面层、覆盖层、扩散/阻挡层、介电层、导电层、其他适合的层、和/或其组合。例如，电介质244可以包括界面层(IL)242和栅极介电层243。IL形成在衬底210和鳍220的上方。通过任何适合的工艺形成具有任何适当厚度的IL 242。示例性IL包括氧化硅(例如，热氧化或化学氧化)和/或氮氧化硅(SiON)。通过任何适当的工艺在IL242的上方形成栅极介电质层243。栅极介电质层243包括介质材料，如氧化硅，氮化硅、氮氧化硅、高k介质材料、其他适合的介质材料、和/或其组合。例如，高k介质材料包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化铪-氧化铝(HfO2-Al2O3)合金、其他适合的高k介质材料、和/或其组合。
通过任何适合的工艺，在介电层244的上方形成栅电极层246。栅电极层246包括任何适合的材料，如多晶硅、铝、铜、钛、钽、钨、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他适合的材料、和/或其组合。
通过任何适合的工艺，在栅电极层246的上方形成硬掩模层248。硬掩模层248包括任何适合的材料，如，氮化硅、SiON、SiC、SiOC、旋涂玻璃(SOG)、低k膜、正硅酸乙脂(TEOS)、等离子增强型(CVD)氧化物(PE氧化物)、高深宽比工艺(HARP)形成的氧化物、和/或其他适合的材料。
通过任何适合的工艺或多个工艺，形成栅极堆叠件240。例如，可以通过一个过程(包括沉积、光刻图案化和蚀刻工艺)形成栅极堆叠件240。沉积工艺包括化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子CVD(HDPCVD)、金属有机CVD(MOCVD)、远程等离子(CVD)(RPCVD)、等离子增强CVD(PECVD)、电镀、其他适合的方法、和/或其组合。光刻图案化工艺包括光刻胶涂覆(例如，旋涂)、软烘、掩模对准、曝光、后曝光烘烤工艺、光刻胶显影、冲洗、干燥(例如，硬烘)、其他适合的工艺、和/或其组合。备选地，用其他适合的方法(如无掩模光刻、电子束写入和离子束写入)完成或代替光刻曝光工艺。蚀刻工艺包括干式蚀刻、湿式蚀刻、和/或其他蚀刻方法(例如，反应离子蚀刻)。
在其他实施例中，栅极堆叠件240是虚拟栅极堆叠件，并且在进行高热预算工艺之后，栅极堆叠件240被金属栅极(MG)代替。虚拟栅极堆叠件240可以包括介电层244、多晶硅层246和硬掩模层248。
再参见图1，只要接收到FinFET前体200，方法100继续步骤104，其中，沿着栅极堆叠件240和鳍220形成侧壁间隔件310，如图4A和图4B所示。侧壁间隔件310通常包括介质材料，如氧化硅。备选地，侧壁间隔件310可以包括氮化硅、SiC、SiON、或其组合。典型的侧壁间隔件310的形成方法包括：在栅极堆叠件240和鳍220的上方沉积介质材料，然后非均质地回蚀介质材料。回蚀工艺可以包括多步蚀刻，才能实现蚀刻的选择性、灵活性和预期的过度蚀刻控制。在本实施例中，控制回蚀的深度以达到预定的鳍-间隔件-高度(Hs)。本文的Hs被定义为沿着鳍220的间隔件高度。可通过调节回蚀工艺，如过度蚀刻的蚀刻参数，来调节Hs。设计Hs的目的是，实现后续外延结构的目标尺寸，下文会给出详细的介绍。
方法100继续步骤106，其中，对鳍220开槽，以形成开槽沟槽400，如图5A和5B所示。在所述的实施例中，形成将侧壁间隔件作为其上部的开槽沟槽400。在一个实施例中，开槽沟槽400的侧壁大致彼此垂直平行。在其他实施例中，用非垂直平行的分布方式(profile)形成开槽沟槽400。
开槽工艺可以包括干式蚀刻工艺、湿式蚀刻工艺、和/或其组合。开槽工艺可以包括选择性湿式蚀刻或选择性干式蚀刻。湿式蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液、或其他适合的溶液。干式和湿式蚀刻工艺具有可调的蚀刻参数，如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻气压、源功率、射频(RF)偏压、RF偏置功率、蚀刻剂流量率、和其他适合的参数。例如，湿式蚀刻溶液可以包括NH4OH、氢氧化钾(KOH)、氢氟酸(HF)、四甲基氢氧化铵(TMAH)、其他适合的湿式蚀刻溶液、或其组合。干式蚀刻工艺包括采用基于氯的化学过程的偏置等离子蚀刻工艺。其他干式蚀刻剂气体包括CF4、NF3、SF6和He。也可以使用深反应离子蚀刻(DRIE)这样的机理，非均质地进行干式蚀刻。
方法100继续步骤108，其中，在开槽沟槽400的上方形成外延结构450，如图6A和6B所示。通过外延生长半导体材料440形成外延结构450。半导体材料440包括单元素半导体材料(如锗(Ge)或硅(Si))、或复合半导体材料(砷化镓(GaAs)和砷化铝镓(AlGaAs))、或半导体合金(如锗化硅(SiGe)、磷砷化镓(GaAsP))。外延结构450具有任何适合的结晶取向(如(100)、(110)、或(111)结晶取向)。在一个实施例中，外延结构450包括源级/漏极外延结构。在一个实例中，期望得到N型FET(NFET)器件，源级/漏极外延结构450可以包括外延生长硅(epi Si)440。备选地，期望得到P型FET(PFET)，外延源级/漏极结构450可以包括外延生长的锗化硅(SiGe)440。
半导体材料440外延生长在开槽沟槽400的被开槽鳍220上，且在开槽沟槽的上方持续生长，以形成具有高度(H)和宽度(W)的外延结构450。
通过一种或多种外延(epi)工艺可以形成外延结构450，这样能够在被开槽鳍220上的结晶状态中形成一个或多个外延部件，如Si部件、SiGe部件和/或其他适合的部件。外延工艺包括CVD沉积技术(如，气相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延生长、和/或其他适合的工艺。
在一个实施例中，外延结构450具有四个切面450A、450B、450C和450D。每个切面具有(111)结晶取向。外延结构450的形状类似于菱形，也就是说，切面450A与切面450C平行，而切面450B与切面450D平行。切面450A和450D与隔离部件220的表面形成固定角
Figure BDA00002662849500081
切面450B和450D与和隔离部件220的表面平行的方向形成固定角例如，角
Figure BDA00002662849500091
和角
Figure BDA00002662849500092
均为54.7度。
参见图7A-图7C，由于两个相邻鳍220之间的间隔距离(S)是固定的，不同的鳍-间隔件-高度(Hs)可能会引起外延结构450的H和W的不同，同时也会引起两个相邻外延结构450之间的合并距离(M)的不同。本文中，M被定义为两个相邻外延结构450的两个最近顶点之间的距离。当两个相邻顶点合并时，M的值介于零和负值之间。在一个实施例中，HsA大于HsB，而HsB大于HsC：
MA＞MB＞MC(均为负值)，
MC＞MB＞MA，以及
HC＞HB＞HA。
在epi工艺中，外延结构450可以是原位掺杂或无掺杂。例如，外延生长的SiGe源级/漏极部件450可以掺杂有硼；并且，外延生长的Si外延源级/漏极部件可以掺杂有碳，以形成Si；C源级/漏极部件，掺杂磷，以形成Si；P源级/漏极部件，或同时掺杂碳和磷，以形成SiCP源级/漏极部件。如果外延结构450不是原位掺杂，进行第二注入工艺(即，接合植入工艺)，以掺杂外延结构450。可以进行一次或多次退火工艺，以激活源级/漏极部件外延结构。退火工艺包括快速热退火(RTA)和/或激光退火工艺。
在一个实施例中，方法100可以进一步包括在形成外延结构450之后，去除侧壁间隔件310。通过选择性蚀刻工艺去除侧壁间隔件310。
在方法100之前、之中和之后能够提供附加步骤，并且，在方法100的其他实施例中，上述的一些附加步骤可以被替代、去除或打乱顺序。例如，当在PMOS器件中形成外延结构450时，通过沉积工艺，在NMOS器件上形成一个或多个层(如光刻胶层或介电层)，以作为保护层。
FinFET器件600可以包括附加部件，该附加部件通过后续处理形成。例如，各种接触件/孔/线和多层互连部件(如金属层和层间电介质)可以形成在衬底的上方，且被配置为连接器件600的各种部件或结构。例如，多层互连件包括垂直互连件(如常规孔或接触件)、和水平互连件(如金属线)。各种互连部件可以实施包括铜、钨、和/或硅化物的各种导电材料。
基于上述可知，本公开提供了制造FinFET器件的方法。该方法包括通过调节鳍-间隔件-高度(Hs)来调节外延结构的高度(H)、宽度(W)和合并距离(M)。所示方法也实现了更好地控制外延结构的H，W和M以及提高了FinFET器件的性能。
本公开提供了制造FinFET器件的多种不同实施例，且与现有技术相比，该FinFET器件在一个或多个方面均有改进。在一个实施例中，制造FinFET器件的方法包括：接收包括衬底和均位于衬底上的鳍式结构和隔离区的FinFET前体，其中，鳍式结构彼此之间具有间隔距离(S)，而隔离区将鳍隔开。该方法进一步包括：沿着鳍的侧壁形成具有预定间隔件高度(Hs)的侧壁间隔件，对鳍开槽以形成将侧壁间隔件作为其上部的开槽沟槽，以及在具有高度(H)和宽度(W)的开槽沟槽的上方形成外延结构。
在另一个实施例中，制造FinFET器件的方法包括：接收包括衬底和均位于衬底上的鳍式结构、隔离区和栅极堆叠件的FinFET前体，鳍式结构彼此之间具有间隔距离(S)，而隔离区将鳍隔开。该方法也包括：沿着鳍和栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件，去除鳍的一部分以形成开槽沟槽，其中，开槽沟槽将侧壁间隔件作为其的上部，在开槽沟槽中的被开槽鳍上外延生长半导体材料，以及持续生长半导体材料，延伸到开槽沟槽的上方以形成外延结构。
在另一个实施例中，制造FinFET器件的方法包括：接收包括衬底和均位于衬底上的鳍式结构、隔离区和栅极堆叠件的FinFet前体，鳍式结构彼此之间具有间隔距离(S)，隔离区将鳍隔开。该方法也包括：沿着鳍和栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件，去除鳍的一部分以形成开槽沟槽，其中，开槽沟槽将侧壁间隔件作为其的上部，以及在开槽沟槽的上方形成外延源级/漏极结构，其中，通过调节Hs，可调外延源级/漏极结构的宽度(W)和高度(H)，以及通过调节Hs，可调两个相邻外延源级/漏极结构的合并间隔(M)。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种制造鳍式场效应晶体管(FinFET)器件的方法，所述方法包括以下步骤：
接收FinFET前体，所述FinFET前体包括：
衬底；和
鳍式结构，位于所述衬底上，所述鳍式结构彼此之间具有间隔距离(S)；
沿着所述鳍式结构的侧壁形成具有预定间隔件高度(Hs)的侧壁间隔件；
对所述鳍式结构开槽以形成开槽沟槽，其中，所述侧壁间隔件是所述开槽沟槽的上部；以及
在所述开槽沟槽的上方形成具有高度(H)和宽度(W)的外延结构。
2.根据权利要求1所述的方法，其中，可通过间隔件蚀刻工艺调节所述间隔件高度(Hs)。
3.根据权利要求1所述的方法，其中，通过在所述开槽沟槽中的被开槽的鳍上外延生长半导体材料来形成所述外延结构，外延生长延伸到所述开槽沟槽的上方以形成所述外延结构。
4.根据权利要求1所述的方法，其中，通过多次沉积工艺形成所述外延结构，其中每一次沉积工艺都对应不同的半导体材料。
5.根据权利要求1所述的方法，其中，可通过Hs和固定的S调节W。
6.根据权利要求1所述的方法，其中，可通过Hs和固定的S调节H。
7.根据权利要求1所述的方法，其中，可通过Hs和固定的S调节两个相邻的外延结构之间的合并间隔(M)。
8.根据权利要求1所述的方法，其中，所述外延结构包括源级/漏极结构。
9.一种制造鳍式场效应晶体管(FinFET)器件的方法，所述方法包括以下步骤：
接收FinFET前体，所述FinFET前体包括：
衬底；
鳍式结构，位于所述衬底上，所述鳍式结构包括彼此之间具有间隔距离(S)的鳍；
隔离区，将所述鳍隔开；和
栅极堆叠件，位于所述衬底上；
沿着所述鳍式结构的鳍和所述栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件；
去除所述鳍的一部分以形成开槽沟槽，其中，所述侧壁间隔件限定所述开槽沟槽的上部；
在所述开槽沟槽中的被开槽的鳍上外延生长半导体材料；以及
持续生长所述半导体材料，以延伸到所述开槽沟槽的上方，从而形成外延结构。
10.一种制造鳍式场效应晶体管(FinFET)器件的方法，所述方法包括以下步骤：
接收FinFET前体，所述FinFET前体包括：
衬底；
鳍式结构，位于所述衬底上，所述鳍式结构包括彼此之间具有间隔距离(S)的鳍；
隔离区，将所述鳍隔开；和
栅极堆叠件，位于所述衬底上；
沿着所述鳍和所述栅极堆叠件形成具有预定间隔件高度(Hs)的侧壁间隔件；
去除所述鳍的一部分以形成开槽沟槽，其中，每个开槽沟槽均包括所述侧壁间隔件作为上部；以及
在所述开槽沟槽的上方形成外延源级/漏极结构，其中，所述外延源级/漏极结构的宽度和高度可由Hs调节，两个相邻的外延源级/漏极结构之间的合并间隔可由Hs调节。
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