CN106252230A - 用于finfet的环绕硅化物 - Google Patents

用于finfet的环绕硅化物 Download PDF

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Publication number
CN106252230A
CN106252230A CN201510798935.3A CN201510798935A CN106252230A CN 106252230 A CN106252230 A CN 106252230A CN 201510798935 A CN201510798935 A CN 201510798935A CN 106252230 A CN106252230 A CN 106252230A
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Prior art keywords
distance piece
grid
dielectric regime
sidewall
semiconductor fin
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CN201510798935.3A
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CN106252230B (zh
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江国诚
刘继文
梁英強
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了用于FINFET的环绕硅化物。一种方法包括在半导体鳍的中间部分上形成栅极堆叠件，以及在栅极堆叠件的侧壁上形成第一栅极间隔件。形成第一栅极间隔件之后，形成模板介电区以覆盖半导体鳍。该方法还包括开槽模板介电区。开槽之后，在栅极堆叠件的侧壁上形成第二栅极间隔件。蚀刻半导体鳍的端部部分以在模板介电区中形成凹槽。在凹槽中外延生长源极/漏极区。

Description

用于FINFET的环绕硅化物
技术领域
本发明涉及用于FINFET的环绕硅化物。
背景技术
在IC材料和设计方面的技术进步已经产生了几代IC，其中，每一代比前一代具有更小和更复杂的电路。在IC发展的过程中，通常已增加了功能性密度(即，每芯片面积的互连器件的数量)，但是减小了几何尺寸(即，使用制造工艺能产生的最小组件(或线))。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。
这种按比例缩小工艺还增加了处理和制造IC的复杂性并且，为了实现这些进步，需要IC处理和制造方面的相似进步。例如，已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管代替平面晶体管。尽管制造FINFET器件的现有FINFET器件和方法已通常满足它们的期望目的，但是它们还不能完全满足所有方面的要求。期望在此领域有所改进。
发明内容
为解决现有技术中存在的问题，根据本发明的一个方面，提供了一种方法，包括：
在半导体鳍的中间部分上形成栅极堆叠件；
在所述栅极堆叠件的侧壁上形成第一栅极间隔件；
形成所述第一栅极间隔件之后，形成模板介电区以覆盖所述半导体鳍；开槽所述模板介电区；
所述开槽之后，在所述栅极堆叠件的所述侧壁上形成第二栅极间隔件；蚀刻所述半导体鳍的端部部分以在所述模板介电区中形成凹槽；以及在所述凹槽中外延生长源极/漏极区。
根据本发明的一个实施例，所述第一栅极间隔件和所述第二栅极间隔件由不同的介电材料形成。
根据本发明的一个实施例，所述第一栅极间隔件由碳氮化硅形成并且所述第二栅极间隔件由碳氧氮化硅形成。
根据本发明的一个实施例，还包括：
当在所述栅极堆叠件的所述侧壁上形成所述第一栅极间隔件时，同时在所述半导体鳍的所述端部部分的侧壁上形成鳍间隔件；以及
形成所述凹槽之后，还蚀刻所述鳍间隔件以扩展所述凹槽，其中，所述源极/漏极区生长在扩展的凹槽中。
根据本发明的一个实施例，还包括：
开槽所述模板介电区之后，对所述第一栅极间隔件实施氧化，其中，所述第一栅极间隔件的位于所述模板介电区上方的第一部分被氧化，并且所述第一栅极间隔件的低于所述模板介电区的顶面的第二部分未被氧化。
根据本发明的一个实施例，还包括：形成所述源极/漏极区之后，去除所述模板介电区。
根据本发明的一个实施例，还包括：形成所述源极/漏极区之后，硅化所述源极/漏极区的侧壁。
根据本发明的另一方面，提供了一种方法，包括：
在半导体鳍的中间部分上形成栅极堆叠件；
在所述栅极堆叠件的侧壁上形成第一栅极间隔件；
形成所述第一栅极间隔件之后，形成模板介电区，所述模板介电区的顶面与所述半导体鳍的顶面大致齐平；
蚀刻所述半导体鳍的端部部分以在所述模板介电区中形成凹槽；
在所述凹槽中外延生长源极/漏极区；
去除所述模板介电区的至少一部分以暴露出所述源极/漏极区的侧壁；以及
硅化所述源极/漏极区的所述侧壁。
根据本发明的一个实施例，去除所述模板介电区包括蚀刻所述模板介电区直至暴露出介电层的与所述模板介电区重叠的部分，并且其中，所述介电层与所述第一栅极间隔件同时形成。
根据本发明的一个实施例，还包括：形成所述模板介电区之后，在所述第一栅极间隔件的侧壁上形成第二栅极间隔件。
根据本发明的一个实施例，其中，所述第一栅极间隔件和所述第二栅极间隔件由不同的介电材料形成。
根据本发明的一个实施例，其中，所述第一栅极间隔件由碳氮化硅形成并且所述第二栅极间隔件由碳氧氮化硅形成。
根据本发明的一个实施例，还包括：
当在所述栅极堆叠件的所述侧壁上形成所述第一栅极间隔件时，同时在所述半导体鳍的所述端部部分的侧壁上同时形成鳍间隔件；以及
形成所述凹槽之后，还蚀刻所述鳍间隔件以扩展所述凹槽。
根据本发明的一个实施例，还包括：
对所述第一栅极间隔件实施氧化，其中，所述第一栅极间隔件的位于所述模板介电区上方的第一部分被氧化，并且所述第一栅极间隔件的位于所述模板介电区的顶面下方的第二部分未被氧化。
根据本发明的一个实施例，还包括：
增大所述第一栅极间隔件的位于所述模板介电区上方的第一部分的k值，并且所述第一栅极间隔件的位于所述模板介电区的顶面下方的第二部分保持不变。
根据本发明的又一方面，提供了一种器件，包括：
鳍式场效应晶体管(FinFET)，包括：
半导体鳍；
栅极，位于所述半导体鳍的侧壁和顶面上；
第一栅极间隔件，从所述栅极的顶面延伸至所述栅极的底面；以及
第二栅极间隔件，从所述栅极的所述顶面延伸至高于所述栅极的所述底面的水平面。
根据本发明的一个实施例，所述第一栅极间隔件和所述第二栅极间隔件由不同的材料形成。
根据本发明的一个实施例，所述第一栅极间隔件由碳氮化硅形成，并且所述第二栅极间隔件由碳氧氮化硅形成。
根据本发明的一个实施例，所述第一栅极间隔件包括上部部分和下部部分，所述上部部分具有比所述下部部分增加的氧量。
根据本发明的一个实施例，所述上部部分和所述下部部分的界面与所述第二栅极间隔件的底端大致齐平。
附图说明
当结合附图进行阅读时，通过下列详细的描述，可以更好地理解本公开的各方面。应该强调的是，根据工业中的标准实践，没有按比例绘制各种部件。实际上，为了清楚地讨论，可以任意地增加或减小各种部件的尺寸。
图1至图19B是根据一些示例性实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面图和立体图；
图20示出了根据一些实施例的FinFET的截面图；
图21A至图21F是根据一些示例性实施例的FinFET的源极/漏极硅化物区的截面图；
图22A、22B和22C是根据一些示例性实施例的形成FinFET的中间阶段的截面图；
图23示出了根据一些实施例的FinFET的截面图；以及
图24示出了根据一些实施例的形成FinFET的工艺流程。
具体实施方式
下列公开提供了用于实现本发明的不同特征的多种不同实施例或实例。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
此外，在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语，以容易的描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除图中所示的方位之外，空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且通过在此使用的空间关系描述符进行相应地解释。
根据各种示例性实施例提供了一种鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。讨论了一些示例性实施例的变化。贯穿各种视图和示例性实施例，相同的参考数字用于指定相同的元件。
图1至图19B示出了根据一些实施例的形成FinFET的中间阶段的截面图和立体图。图1至图19B所示的步骤也在图24所示的工艺流程200中图示性地示出。在后续讨论中，参照图24中的工艺步骤讨论了图1至图19B所示的工艺步骤。
图1示出了形成包括衬底20、隔离区22、隔离区22之间的半导体带24、和隔离区22的顶面上方的半导体鳍26的结构的立体图。衬底20是半导体衬底，其还可为硅衬底、碳化硅衬底、或由其他半导体材料形成的衬底。衬底20可轻掺杂p型或n型杂质。
隔离区22可例如为浅沟槽隔离(STI)区。STI区22的形成可包括蚀刻半导体衬底20以形成沟槽(未示出)，以及使用介电材料填充沟槽以形成STI区22。STI区22可包括氧化硅，并且诸如氮化物的其他介电材料也可使用。半导体鳍26与下面的半导体带24重叠。半导体鳍26的形成可包括开槽STI区22，这样使得半导体材料的位于STI区22的去除部分之间的部分成为半导体鳍26。半导体鳍26和半导体带24的一些或大致整体可由硅(其内没有锗)或包括但不限于碳化硅、硅锗等的其他含硅化合物形成。
栅极堆叠件28形成在半导体鳍26上。相应步骤在图24所示的工艺流程中表示为步骤202。栅极堆叠件28覆盖半导体鳍26的中间部分，并且留下半导体鳍26未被覆盖的相对端部部分。
栅极堆叠件28包括半导体鳍26的侧壁和顶面上的栅极电介质32以及栅极电介质32上方的栅电极34。栅极电介质32可选自氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧、氧化铪、它们的组合、和它们的多层。栅电极34可包括导电材料，导电材料包括多晶硅、难熔金属、或相应的化合物(包括，例如，Ti、W、TiAl、TaC、TaCN、TaAlC、TaAlCN、TiN和TiW)。在其他实例中，栅电极34包括镍(Ni)、金(Au)、铜(Cu)、或它们的合金。
根据本发明的一些实施例，栅极堆叠件28保留在最终的FinFET中，并且形成最终的FinFET的栅极堆叠件。根据本发明的替代实施例，栅极堆叠件28是伪栅极堆叠件，其在后续步骤中将被替换栅极所替代。因此，栅极堆叠件28可包括伪栅电极(其也被表示为34)，其可包括例如多晶硅。伪栅极电介质32可、或不可形成在伪栅电极34和半导体鳍26之间。
栅极堆叠件28还可包括形成在栅电极34上方的硬掩模35和36。根据一些实施例，硬掩模35由氧化硅、碳氧氮化硅(SiOCN)等形成。根据一些实施例，硬掩模36可由氮化硅(SiN)形成。
图2A至图10C示出了形成FinFET的中间阶段。图2A至图10C的图数字中的每一个包括字母“A”、“B”或“C”，其中，字母“A”说明从与图1中含线A-A的垂直平面相同的平面获得相应的视图，并且字母“B”说明从与图1中含线B-B的垂直平面相同的平面获得的相应的图，以及字母“C”说明从与图1中含线C-C的垂直平面相同的平面获得的相应的图。因此，数字后面为字母“A”的附图示出了源极/漏极区的截面图，数字后面为字母“B”的附图示出了半导体鳍26和上面的栅极中的一个的截面图，以及数字后面为字母“C”的附图示出了处于没有横跨半导体鳍26的位置的伪栅极堆叠件28的截面图。
图2A、2B和2C示出了从图1获得的截面图。接着，参照图3A、3B和3C，形成间隔层38。间隔层38可选地被称为第一间隔层，并且相应的间隔件被称为第一间隔件。相应的步骤在图24所示的工艺流程中被表示为步骤204。间隔层38在用于形成源极/漏极硅化物和源极/漏极接触件的接触开口的后续形成中用作蚀刻停止层，因此可选地被称为蚀刻停止层。间隔层38的材料被选择为相对于氧化物(诸如图4A、4B和4C所示的后续形成的模板介电区40)具有高蚀刻选择率。根据本发明的一些实施例，间隔层38包括碳氮化硅(SiCN)，但是可使用其他介电材料。间隔层38可具有范围介于约3nm至约10nm之间的厚度。
间隔层38形成为共形层，因此覆盖半导体鳍26的顶面和侧壁(图3A)以及栅极堆叠件28(图3B和3C)。半导体鳍26的侧壁上的间隔层38的部分也被称为鳍间隔件，如图3A所示，并且半导体鳍26的侧壁上的间隔层38的部分在下文中也被称为栅极间隔件。根据一些实施例，间隔层38的厚度的范围在约3nm至约10nm之间。
接着，如图4A、4B和4C所示，例如使用可流动的化学气相沉积(FCVD)形成模板介电区40。相应的步骤在图24所示的工艺流程中被表示为步骤206。根据一些实施例，模板介电区40可包括氧化硅。剩余的模板介电区40的顶面高于半导体鳍26的顶面和栅极堆叠件28的顶面。然后实施诸如化学机械抛光(CMP)的平坦化工艺以使模板介电区40的顶面平坦。在产生的结构中，模板介电区40的顶面高于半导体鳍26的顶面，并且可齐平于或高于栅极堆叠件28的顶端(以及间隔层38的上面部分)。
图5A、5B和5C示出了例如通过湿蚀刻的模板介电区40的回蚀刻。相应的步骤在图24所示的工艺流程中被表示为步骤208。由于回蚀刻，如图5A所示，模板介电区40的剩余部分的顶面大致齐平于或低于间隔层的与半导体鳍26重叠的部分的顶面。在图5A中，通过模板介电区40可暴露间隔层38的顶部部分的顶面。蚀刻选择率(模板介电区40的蚀刻率与间隔层38的蚀刻率之间的比值)很高，例如，高于约30。因此，回蚀刻模板介电区40之后留有间隔层38。如图5B和5C所示，去除了直接位于半导体鳍26上方的模板介电区40的部分(图5B)。另一方面，直接位于STI区22上方的模板介电区40的部分仍留有一些部分(图5C)。根据本发明的一些实施例，剩余模板介电区40的厚度T1的范围介于约20nm至约80nm之间。
根据本发明的一些实施例，图5A、5B和5C中的工艺步骤之后，实施图22A、22B和22C所示的工艺步骤，并且氧化间隔层38的暴露部分。因此，间隔层38的暴露部分被氧化为部分38_1(下文被称为氧化部分38_1)。相应的步骤在图24所示的工艺流程中被表示为步骤209。代表步骤209的框用虚线表示以说明可实施或跳过该步骤。未氧化间隔层38的未暴露部分38_2。当间隔层38由SiCN形成时，产生的氧化部分38_1包括碳氧氮化硅(SiOCN)，其具有比未转变的部分38_2减小的k值。例如，SiCN可具有范围介于约5.0和7.0之间的k值，并且SiOCN可具有范围介于约4.5和5.0之间的k值。氧化部分38_1和未氧化部分38_2的k值的差值可大于约0.5、或大于约1.0。k值的减小导致寄生电容的有利降低。根据本发明的一些实施例，使用炉退火(在含氧气体中)、氧气注入等实施间隔层38的氧化，其中，使用箭头示出氧化。
图22A、22B和22C中工艺步骤之后，实施图6A、6B和6C中的工艺步骤。根据替换实施例，图5A、5B和5C中的工艺步骤之后，工艺进行至图6A、6B和6C所示的步骤，但是省略图22A、22B和22C中的工艺步骤。
在后续的步骤中，如图6A、6B和6C所示，形成硬掩模间隔件42。硬掩模间隔件42可选地被称为第二间隔件或第二间隔层。相应的步骤在图24所示的工艺流程中被示出为步骤210。选择硬掩模间隔件42的材料，使得蚀刻选择率(硬掩模间隔件42的蚀刻率与间隔层38的蚀刻率之间的比值)很高，例如，高于约30。例如，当间隔层38由SiCN形成时，硬掩模间隔件42可由碳氧硅氮化物(SiOCN)形成，其具有与SiCN不同的蚀刻特性。此外，与SiCN相比，使用湿蚀刻更易于去除SiOCN。
根据一些示例性实施例，如图6B和6C所示，硬掩模间隔件42的形成包括毯式沉积共形硬掩模层，以及实施各向异性蚀刻以去除硬掩模层的水平部分。硬掩模层的剩余部分为硬掩模间隔件42，其形成在间隔层38的侧壁部分上。
如图6C所示，间隔层38具有掩埋在栅极堆叠件28和模板介电区40之间的一些部分。间隔层38的底端38A与STI区22的顶面接触。因为形成模板介电区40之后形成硬掩模间隔件42，所以底端42A高于模板介电区40的顶面。因此，硬掩模间隔件42的底端42A高于间隔层38的底端38A，并且两者高度差值等于模板介电区40的厚度T1，其范围可介于约20nm至约80nm之间。
图6A还示出了去除间隔层38的顶部部分。间隔层38的剩余部分在下文中被称为(鳍)间隔件38。在截面图中，鳍间隔件具有U型(也包括L型)。
图1至图6C示出的工艺流程示出了在形成PMOS和NMOS器件中可使用的工艺，尽管PMOS器件和NMOS器件彼此物理分隔开。在后续示出的源极区和漏极区的形成中，PMOS器件和NMOS器件采用单独的工艺步骤。因此，当形成PMOS器件的源极/漏极区时，掩模层44掩盖NMOS器件，如图7A、7B和7C所示。根据本发明的一些示例性实施例，掩模层44由SiN形成，并且还可使用在图8A至图10C所示的步骤中不会被蚀刻掉的其他材料。在掩模层44保护PMOS器件或NMOS器件的情况下，工艺步骤进行至图8A至图10C中所示的步骤。当完成PMOS器件或NMOS器件的在图8A至图10C所示的工艺步骤时，去除掩模层44，并且另一个掩模层(未示出)将覆盖完成的器件。然后对于其他器件可重复图8A至图10C所示的工艺步骤。
图7A、7B和7C所示的步骤之后，在蚀刻步骤中对半导体鳍26的未被栅极堆叠件28覆盖的端部部分(参照图1和图7A)开槽。图8A、8B和8C中示出了产生的结构。相应的步骤在图24所示的工艺流程中被表示为步骤212。参照图8A，由于去除半导体鳍26的端部部分，所以形成凹槽46。间隔层38和模板介电区40未被覆盖，因此，限定了凹槽46。根据一些实施例，凹槽46的底部大致齐平于间隔层38的底面。根据本发明的代替实施例，凹槽46的底部高于或低于间隔层38的底面。
图8B示出去除了半导体鳍26的端部部分，以及保留了半导体鳍26的被栅极堆叠件28覆盖的中间部分。如图8C所示，形成凹槽46之后仍有模板介电区40。
接着，实施蚀刻步骤以去除间隔件38的暴露给凹槽46的侧壁部分(38的鳍间隔部分)，如图9A所示。蚀刻可以是各向同性的，例如，使用湿蚀刻。因此，如图8A所示，增加了凹槽46的横向宽度。相应的步骤在图24所示的工艺流程中表示为步骤214。这样可有利地增加凹槽46中后续生长的源极/漏极区的宽度。图9B和9C所示的结构分别与图8B和8C所示的结构相似。
在后续步骤中，源极和漏极区(下文中被称为源极/漏极区)外延生长在凹槽46中。图10A、10B和10C中示出了产生的结构。相应的步骤在图24所示的工艺流程中表示为步骤216。根据本发明的一些实施例，源极/漏极区48的形成包括外延生长。当产生的FinFET是n型FinFET时，源极/漏极区48包括硅磷(SiP)或磷掺杂的碳化硅(SiCP)。当产生的FinFET是p型FinFET时，源极/漏极区48可包括SiGe，并且在外延期间诸如硼或铟的p型杂质可原位掺杂。根据一些实施例，根据源极/漏极区48是属于PMOS器件还是NMOS器件，源极/漏极区48包括具有不同的磷、锗、碳等百分比的下部部分48’和上部部分48’。随着外延的进行，适当的p型或n型杂质可原位掺杂，并且在外延之后可(或不可)注入到源极/漏极区48中。
源极/漏极区48包括具有垂直侧壁的平直部分。此外，在平直部分上方可(或不可)具有源极/漏极区48的扩展部分。例如，图21A至图21F示出了源极/漏极区48包括具有垂直侧壁48A的平直部分和具有刻面48B的扩展部分。根据替代实施例，源极/漏极区48不会明显地生长在凹槽46的外部。因此，源极/漏极区48不会具有扩展部分，并且产生的源极/漏极区48与图10A所示相似。源极/漏极区48的宽度的范围可介于约6nm和约12nm之间。源极/漏极区48的高度的范围可介于约30nm和约80nm之间。
在源极/漏极区48的形成中，模板介电区40用作限制源极/漏极区48的形成的模板，这样使得源极/漏极区48具有平直侧壁，并且扩展部分被最小化(如果形成的话)。
图11至图16示出了根据一些实施例的在先硅化物(silicide-first)工艺中形成源极/漏极硅化物区、层间介电层(ILD)和接触插塞。在先硅化物工艺中，形成ILD之前形成源极/漏极硅化物区。图11示出了图10A中所示的结构的一部分。接着，实施蚀刻(诸如干蚀刻)以去除源极/漏极区48之间的模板介电区40，并且图12中示出产生的结构。相应的步骤在图24所示的工艺流程中表示为步骤218。在蚀刻步骤中，间隔件38用作蚀刻停止层。因为间隔件38具有相对于模板介电区40较高的蚀刻选择率，所以间隔件38有效地保护下面的STI区22。
接着，如图13所示，实施硅化工艺以在源极/漏极区48的侧壁上形成硅化物区50。相应的步骤在图24所示的工艺流程中被表示为步骤220。根据本发明的一些实施例，硅化物区包括硅化镍、硅化钛、硅化钴等。硅化物区50的厚度的范围可介于约2nm和约8nm之间。
接着，如图14所示，形成阻挡层51和ILD 52。然后实施CMP以使ILD 52的顶面平坦。阻挡层51可由非晶硅形成。ILD 52可由FCVD氧化物形成，该氧化物可以为氧化硅。根据代替实施例，ILD 52由磷硅酸玻璃(PSG)、硼硅酸玻璃(BSG)、硼掺杂磷硅酸玻璃(BPSG)、氟掺杂硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。然后实施退火，产生图15所示的结构。在退火期间，阻挡层51吸收ILD 52中的氧气，因此被转化为氧气。另一方面，阻挡层51防止硅化物区50被氧化。
形成ILD 52之后，形成替换栅极。首先，去除图10B和10C所示的伪栅极堆叠件28，从而如图15中那样在ILD 52中形成开口。在去除的伪栅极堆叠件28所留下的开口中形成替换栅极。图20中示出产生的结构。根据一些实施例，替换栅极56包括界面层58、高k栅极电介质60和栅电极62。界面层58可由氧化硅形成。高k栅极电介质60可由k值大于约7.0的高k电介质形成，并且可包括金属氧化物或Hf、Al、Zr、La等的硅化物。栅电极62可包括由诸如TiN、TaN、TiAl、钴和Al的材料形成的多层。
形成替换栅极56之后，接触插塞54形成，如图16所示。相应的步骤在图24所示的工艺流程中被表示为步骤222。形成工艺包括在ILD 52中形成接触开口，以及使用接触插塞54填充接触开口。因此完成FinFET 70的形成。
图17至20示出了根据代替实施例的在后硅化物工艺中形成源极/漏极硅化物区、ILD、和接触插塞。在后硅化物工艺中，形成ILD之后源极/漏极硅化物区形成，并且穿过接触开口。图17再次示出了图10A所示的结构的一部分。接着，参照图18，ILD 52形成之后形成接触蚀刻停止层(CESL)68。CESL 68可由氮化硅或其他介电材料形成。CESL 68位于模板介电区40的剩余部分上。此外，如图20所示，CESL 68还形成在硬掩模间隔件42的侧壁上。此外，CESL 68包括与模板介电区40重叠的部分，并且CESL68的底面68A与模板介电区40的顶面接触。底面68A还高于间隔件38的底端38A。在图20中，使用虚线示出CESL 68以说明CESL 68可在采用后硅化物工艺时形成，并且在采用先硅化物工艺时CESL 68不可能形成。
在形成CESL 68和ILD 52之后，形成替换栅极56，其中，替换栅极56与图20所示栅极相似。
图19A和图19B示出了根据一些实施例的通过图18所示的结构形成的接触插塞54。如图19A所示，接触插塞54与剩余的模板介电区40重叠且接触。在这些实施例中，在接触开口的形成中，未完全去除暴露给接触开口的介电区40。图19B示出了根据代替实施例的结构，其中，去除暴露给接触开口的一个模板介电区40的整体，因此，接触插塞延伸至接触间隔件38。还可具有其他剩余的模板介电区40。
图20示出了产生的FinFET 70的截面图。从包含图1中线D-D的相同垂直平面获得该截面图。并且，为了简单，图20示出了单个鳍26，尽管图1示出了两个鳍26。应该意识到，当形成间隔件38(图3A至3C)、模板介电区40(图4A至5C)、硬掩模层42(图6A至6C)和CESL 68(图18)时，这些部件还同时形成在栅极堆叠件28的左端侧壁和右端侧壁上(参照图1)。因此，图20示出了间隔件38、模板介电区40、硬掩模层42和CESL 68的这些部分。
如图20所述，间隔件38从替换栅极56的顶面延伸至底面，并且底面38A位于STI区22的顶面上。模板介电区40形成为与STI区22重叠。硬掩模层42具有与模板介电区40的顶面接触的底面。硬掩模层42的底面42A还高于间隔件38的底面/底端38A。CESL 68(如果形成)的底面68A还将接触模板介电区40的顶面，因此还高于间隔件38的底端38A。
根据一些实施例，FinFET 70的沟道鳍高度FH的范围在约30nm和约80nm之间。沟道鳍宽度FW的范围可在约1nm和约12nm之间。间隔件38的厚度T2、硬掩模层42的厚度T3和CESL 68的厚度T4中的每一个的范围在约1nm和约10nm之间。间隔件高度差T1与鳍高度FH之间的比值的范围可在约0.6和约1之间。间隔件高度差T1与替换栅极56的高度MGH之间的比值的范围可在约0.1和约0.3之间。
图21A至图21F示出了根据各种实施例的源极/漏极硅化物区50和接触插塞54的剖面图。图21A、21B和21C示出了使用先硅化物工艺形成的硅化物区50和接触插塞54。因此，因为在形成接触开口时已经形成了硅化物区50，所以可形成很小的接触开口。例如，在图21A、21B和21C中，接触插塞54小于包括两个源极/漏极区48和源极/漏极区48之间的区的组合区。相比而言，在图21D至图21F(后硅化物工艺)中，接触插塞54大于包括两个源极/漏极区48和源极/漏极区48之间的区的组合区。这是因为在后硅化物方法中，接触开口将足够大，使得硅化物区可形成在接触开口中。
图21A、21B、21D和21E示出了用于形成硅化物区50的剩余金属55在形成硅化物区50之后未被去除。此外，图21A和21D示出了金属55限定在源极/漏极区48之间，而图21B和21E示出了金属55扩展出最外层的源极/漏极区48之外。图21C示出了ILD 52仍在接触插塞54下方，并且图21F示出了接触插塞54一直延伸至间隔件38。
图23示出了根据一些实施例的FinFET 70的截面图。通过实施图22A、22B和22C所示的步骤获得根据一些实施例的FinFET 70(图24中的步骤209)。因此，产生的硬掩模层42包括氧化的上部部分38_1和未被氧化的下部部分38_2，未被氧化的下部部分38_2的k值高于氧化的上部部分38_1的k值。参照图22C，氧化的上部部分38_1和未被氧化的下部部分38_2之间的界面与模板介电区40的顶面大致齐平(例如，高度差值小于约2nm)。根据替代实施例，氧化的上部部分38_1和未被氧化的下部部分38_2之间的界面低于模板介电区40的顶面。
本发明的实施例具有一些有利部件。通过形成介电区以用作源极/漏极外延的模板，产生的源极/漏极区具有平直侧壁，因此硅化物区可更均匀地形成在源极/漏极区的所有侧壁和顶面上。因此降低了源极/漏极接触电阻，并且增加了FinFET的驱动电流。
根据本发明的一些实施例，一种方法包括在半导体鳍的中间部分形成栅极堆叠件以及在栅极堆叠件的侧壁上形成第一栅极间隔件。形成第一栅极间隔件之后，形成模板介电区以覆盖半导体鳍。该方法还包括开槽模板介电区。开槽之后，在栅极堆叠件的侧壁上形成第二栅极间隔件。蚀刻半导体鳍的端部部分以在模板介电区中形成凹槽。在凹槽中外延生长源极/漏极区。
根据本发明的替代实施例，一种方法包括在半导体鳍的中间部分上形成栅极堆叠件以及在栅极堆叠件的侧壁上形成栅极间隔件。形成第一栅极间隔件之后，形成模板介电区，模板介电区的顶面与半导体鳍的顶面大致齐平。蚀刻半导体鳍的端部部分以在模板介电区中形成凹槽。在凹槽中外延生长源极/漏极区。该方法还包括至少去除模板介电区的一部分以暴露出源极/漏极区的侧壁，以及硅化源极/漏极区的侧壁。
根据本发明的替代实施例，FinFET包括半导体鳍、半导体鳍的侧壁和顶面上的栅极、从栅极的顶面延伸至栅极的底面的第一栅极间隔件、以及从栅极的顶面延伸至高于栅极的底面的水平面的第二栅极间隔件。
上面论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解，可以很容易地使用本公开作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的技术人员也应该意识到，这种等效构造并不背离本公开的精神和范围，并且在不背离本公开的精神和范围的情况下，可以进行多种变化、更换以及改变。

Claims (10)

1.一种方法，包括：
在半导体鳍的中间部分上形成栅极堆叠件；
在所述栅极堆叠件的侧壁上形成第一栅极间隔件；
形成所述第一栅极间隔件之后，形成模板介电区以覆盖所述半导体鳍；
开槽所述模板介电区；
所述开槽之后，在所述栅极堆叠件的所述侧壁上形成第二栅极间隔件；
蚀刻所述半导体鳍的端部部分以在所述模板介电区中形成凹槽；以及
在所述凹槽中外延生长源极/漏极区。
2.根据权利要求1所述的方法，其中，所述第一栅极间隔件和所述第二栅极间隔件由不同的介电材料形成。
3.根据权利要求2所述的方法，其中，所述第一栅极间隔件由碳氮化硅形成并且所述第二栅极间隔件由碳氧氮化硅形成。
4.根据权利要求1所述的方法，还包括：
当在所述栅极堆叠件的所述侧壁上形成所述第一栅极间隔件时，同时在所述半导体鳍的所述端部部分的侧壁上形成鳍间隔件；以及
形成所述凹槽之后，还蚀刻所述鳍间隔件以扩展所述凹槽，其中，所述源极/漏极区生长在扩展的凹槽中。
5.根据权利要求1所述的方法，还包括：
开槽所述模板介电区之后，对所述第一栅极间隔件实施氧化，其中，所述第一栅极间隔件的位于所述模板介电区上方的第一部分被氧化，并且所述第一栅极间隔件的低于所述模板介电区的顶面的第二部分未被氧化。
6.根据权利要求1所述的方法，还包括：形成所述源极/漏极区之后，去除所述模板介电区。
7.根据权利要求1所述的方法，还包括：形成所述源极/漏极区之后，硅化所述源极/漏极区的侧壁。
8.一种方法，包括：
在半导体鳍的中间部分上形成栅极堆叠件；
在所述栅极堆叠件的侧壁上形成第一栅极间隔件；
形成所述第一栅极间隔件之后，形成模板介电区，所述模板介电区的顶面与所述半导体鳍的顶面大致齐平；
蚀刻所述半导体鳍的端部部分以在所述模板介电区中形成凹槽；
在所述凹槽中外延生长源极/漏极区；
去除所述模板介电区的至少一部分以暴露出所述源极/漏极区的侧壁；以及
硅化所述源极/漏极区的所述侧壁。
9.根据权利要求8所述的方法，其中，去除所述模板介电区包括蚀刻所述模板介电区直至暴露出介电层的与所述模板介电区重叠的部分，并且其中，所述介电层与所述第一栅极间隔件同时形成。
10.一种器件，包括：
鳍式场效应晶体管(FinFET)，包括：
半导体鳍；
栅极，位于所述半导体鳍的侧壁和顶面上；
第一栅极间隔件，从所述栅极的顶面延伸至所述栅极的底面；以及
第二栅极间隔件，从所述栅极的所述顶面延伸至高于所述栅极的所述底面的水平面。
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