TWI602225B - 用於ｆｉｎｆｅｔ的環繞矽化物 - Google Patents

用於ｆｉｎｆｅｔ的環繞矽化物 Download PDF

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TWI602225B
TWI602225B TW104139374A TW104139374A TWI602225B TW I602225 B TWI602225 B TW I602225B TW 104139374 A TW104139374 A TW 104139374A TW 104139374 A TW104139374 A TW 104139374A TW I602225 B TWI602225 B TW I602225B
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dielectric region
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TW104139374A
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TW201643946A (zh
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江國誠
劉繼文
英強 梁
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台灣積體電路製造股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description

用於FINFET的環繞矽化物
本揭露涉及用於FINFET的環繞矽化物。
IC材料和設計方面的技術進步已經產生了若干代IC，其中每一代比前一代具有更小並更複雜的電路。在IC演進的過程中，功能密度(即，每晶片區域互連的裝置的數目)普遍增加，而幾何尺寸(即，使用製造工藝能夠生產的最小元件(或線))減小。這種尺寸縮小工藝通常提供增加生產效率並降低相關成本的好處。
這種尺寸縮小工藝也增加了處理和製作IC的複雜度，並且對於待實現的這些改進，需要在IC處理和製造上有類似的改進。例如，已經引入諸如鰭式場效電晶體(FinFET)的三維電晶體來代替平面電晶體。儘管現有的FinFET裝置以及製造FinFET裝置的方法通常能夠滿足它們預期的目的，但是它們不能在所有方面都完全滿足。需要在這方面有所改進。
根據本揭露的一些實施例，提供有一種方法，其包括：在半導體鰭片的中間部分形成閘極堆疊；在閘極堆疊的側壁上形成第一閘極間隔物；在形成第一閘極間隔物後，形成模板介電區以覆蓋半導體鰭片；凹進模板介電區；在凹進之後，在閘極堆疊的側壁上形成第二閘極間隔物；蝕刻半導體鰭片的端部分以在模板介電區中形成 凹槽；以及在凹槽中磊晶地生長源極/汲極區。
優選地，第一閘極間隔物和第二閘極間隔物由不同的介電材料形成。
優選地，第一閘極間隔物由碳氮化矽形成，而第二閘極間隔物由氧碳氮化矽形成。
優選地，還包括：當在閘極堆疊的側壁上形成第一閘極間隔物時，同時在半導體鰭片的端部分的側壁上形成鰭片間隔物；以及在凹槽形成之後，進一步蝕刻鰭片間隔物以擴展凹槽，其中，源極/汲極區在擴展的凹槽中生長。
優選地，還包括：在凹進模板介電區後，在第一閘極間隔物上執行氧化，其中，模板介電區上的第一閘極間隔物的第一部分被氧化，而低於模板介電區頂表面的第一閘極間隔物的第二部分不被氧化。
優選地，還包括在形成源極/汲極區後，移除模板介電區。
優選地，還包括在形成源極/汲極區後，矽化源極/汲極區的側壁。
根據本揭露另外的實施例，提供有一種方法，其包括：在半導體鰭片的中間部分形成閘極堆疊；在閘極堆疊的側壁上形成第一閘極間隔物；在形成第一閘極間隔物後，形成模板介電區，模板介電區的頂表面大體上與半導體鰭片的頂表面對齊；蝕刻半導體鰭片的端部分以在模板介電區中形成凹槽；在凹槽中磊晶地生長源極/汲極區；移除模板介電區的至少一部分以暴露源極/汲極區的側壁；以及矽化源極/汲極區的側壁。
優選地，移除模板介電區包括蝕刻模板介電區直到暴露由模板介電區覆蓋的介電層的一部分，且其中介電層同時形成為第一閘極間隔物。
優選地，還包括在形成模板介電區後，在第一閘極間隔物的側壁上形成第二閘極間隔物。
優選地，第一閘極間隔物和第二閘極間隔物由不同的介電材料形成。
優選地，第一閘極間隔物由碳氮化矽形成，而第二閘極間隔物由氧碳氮化矽形成。
優選地，還包括：當在閘極堆疊的側壁上形成第一閘極間隔物時，同時在半導體鰭片的端部分的側壁上形成鰭片間隔物；以及在凹槽形成之後，進一步蝕刻鰭片間隔物以擴展凹槽。
優選地，還包括：在第一閘極間隔物上執行氧化，其中，模板介電區上的第一閘極間隔物的第一部分被氧化，而模板介電區頂表面之下的第一閘極間隔物的第二部分不被氧化。
優選地，還包括：增加模板介電區上的第一閘極間隔物的第一部分的k值，而模板介電區頂表面之下的第一閘極間隔物的第二部分的k值保持不變。
根據本揭露另外的實施例，提供有一種裝置，其包括：鰭式場效電晶體(FinFET)，其包括：半導體鰭片；半導體鰭片的側壁和頂表面上的閘極；第一閘極間隔物，其從閘極的頂表面延伸至底表面；以及第二閘極間隔物，其從閘極的頂表面延伸至高於閘極的底表面的水平。
優選地，第一閘極間隔物和第二閘極間隔物由不同的介電材料形成。
優選地，第一閘極間隔物由碳氮化矽形成，而第二閘極間隔物由氧碳氮化矽形成。
優選地，第一閘極間隔物包括上部和下部，上部比下部具有更多的含氧量。
優選地，上部和下部的交界面大體上與第二閘極間隔物的底端對齊。
20‧‧‧基板
22‧‧‧隔離區
24‧‧‧半導體條
26‧‧‧半導體鰭片
28‧‧‧閘極堆疊
32‧‧‧閘極介電質
34‧‧‧閘極電極
35‧‧‧硬遮罩
36‧‧‧硬遮罩
38‧‧‧間隔物層
38A‧‧‧間隔物層38的底端
38_1‧‧‧經氧化的部分
38_2‧‧‧未氧化的部分
50‧‧‧矽化物區
51‧‧‧阻擋層
52‧‧‧ILD
54‧‧‧接觸插塞
55‧‧‧金屬
56‧‧‧替代閘極
58‧‧‧介面層
60‧‧‧閘極介電質
62‧‧‧閘極電極
68‧‧‧接觸蝕刻停止層CESL
68A‧‧‧CESL的底表面
70‧‧‧FinFET
AA‧‧‧線
40‧‧‧模板介電區
42‧‧‧硬遮罩間隔物
42A‧‧‧底端
44‧‧‧遮罩層
46‧‧‧凹槽
48‧‧‧源極/汲極區
48’‧‧‧下部
48”‧‧‧上部
48A‧‧‧豎直壁
48B‧‧‧切面
BB‧‧‧線
CC‧‧‧線
DD‧‧‧線
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
T4‧‧‧厚度
MGH‧‧‧高度
FH‧‧‧高度
FW‧‧‧寬度
當閱讀隨附的附圖時，從以下詳細的描述可以最清楚地理解本揭露的各個方面。需要強調的是，根據本行業的標準做法，不是按比例繪製各個特徵。事實上，各個特徵的尺寸可以任意增大或減小以便進行清楚的討論。
圖1A至圖19B根據一些示例性實施例示出形成鰭式場效電晶體(FinFET)的中間階段的剖面圖和透視圖；圖20根據一些實施例示出FinFET的剖面圖；圖21A至圖21F根據一些示例性實施例示出FinFET的源極/汲極矽化物區的剖面圖；圖22A、22B和22C根據一些示例性實施例示出形成FinFET的中間階段的剖面圖；圖23根據一些實施例示出FinFET的剖面圖；以及圖24根據一些實施例示出形成FinFET的流程圖。
如下公開提供了很多不同的實施例或示例，用於實施所提供的主題的不同特徵。如下描述了元件和佈置的具體示例，以簡化本揭露。當然，它們僅僅是示例，並不是旨在限制本揭露。例如，以下描述中在第二特徵之上或在第二特徵上形成第一特徵可以包括形成直接接觸的第一特徵和第二特徵的實施例，還可以包括在第一特徵和第二特徵之間可以形成附加特徵從而使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本揭露可以在各個示例中重複使用符號和/或字母。這種重複使用用於簡化和清楚的目的，其本身並不表明所述的各個實施例和/或配置之間的關係。
而且，空間關係術語，例如“之下”、“下方”、“下面”、“之上”、“上方”等，在此用於簡化描述附圖所示的一個單元或特徵對另一個單元或特徵的關係。除了附圖中描寫的方向，空間關係術語旨在包含使用或操作的裝置的不同方向。設備可以以其他方式定向(旋轉90度或者在其他方向)，並可以據此同樣地解釋本文所使用的空間關係描述語。
根據各個示例性實施例提供了鰭式場效電晶體(FinFET)及其形成方法。示出了形成FinFET的中間階段。討論的一些實施例的變體。在整個附圖和說明性實施例中，相同的符號用於表示相同的元件。
圖1A至圖19B根據一些實施例示出形成FinFET的中間階段的剖面圖和透視圖。圖1A至圖19B所示的步驟也概要地表示在圖24所示的方法流程200中。在隨後的討論中，參照圖24的方法步驟討論圖1A至圖19B所示的步驟。
圖1示出了一種結構形成的透視圖，該結構包括基板20、隔離區22、隔離區22之間的半導體條24以及隔離區22的頂表面上的半導體鰭片26。基板20是半導體基板，其還可以是矽基板、碳化矽基板或其他半導體材料形成的基板。基板20可以輕度摻雜有p型或n型雜質。
隔離區22例如可以是淺溝隔離(STI)區。SIT區22的形成可以包括蝕刻半導體基板20以形成渠道(未示出)，並以介電材料填充該渠道以形成STI區22。STI區22可包括氧化矽，也可以使用諸如氮化物的其他介電材料。半導體鰭片26覆蓋下面的半導體條24。半導體鰭片26的形成可包括凹進STI區22，從而使得STI區22所移除的部分之間的半導體材料部分成為半導體鰭片26。半導體鰭片26和一部分的或大體上全部的半導體條24可以由矽(其中沒有鍺)或其他含矽化合物形成，該矽化合物包括但不限於碳化矽、鍺化矽等。
閘極堆疊28在半導體鰭片26上形成。相應的步驟如圖24的流程圖中步驟202所示。閘極堆疊28覆蓋半導體鰭片26的中間部分，並且不覆蓋半導體鰭片26的相對端部分。
閘極堆疊28包括半導體鰭片26的側壁和頂表面上的閘極介電質32以及閘極介電質32上的閘極電極34。閘極介電質32可從氧化矽、氮化矽、氧化鎵、氧化鋁、氧化鈧、氧化鋯、氧化鑭、氧化鉿、它們的組合以及它們的多層中選擇。閘極電極34可包括導電材料，其包括多晶矽、耐火金屬或相應的化合物，例如，Ti，W，TiAl，TaC，TaCN，TaAlC，TaAlCN，TiN和TiW。在其他示例中，閘極電極34包括鎳(Ni)、金(Au)、銅(Cu)或其合金。
根據本揭露的一些實施例，閘極堆疊28保持在最終的FinFET內，並形成最終FinFET的閘極堆疊。根據揭露的其他實施例，閘極堆疊28是虛置閘極堆疊，其在隨後的步驟中將被替代閘極代替。因此，閘極堆疊28可包括虛置閘極電極(其也表示為34)，其可包括(例如)多晶矽。虛置閘極介電質32可在或可不在閘極電極34和半導體鰭片26之間形成。
閘極堆疊28還可包括在閘極電極34上形成的硬遮罩35和36。根據一些實施例，硬遮罩35由氧化矽、氧碳氮化矽(silicon oxycarbo-nitride,SiOCN)等形成。根據一些實施例，硬遮罩36可由氮化矽(SiN)形成。
圖2A至圖10C示出了形成FinFET的中間階段。圖2A至圖10C的每一個圖號包括字母“A”、“B”或“C”，其中字母“A”表示對應的附圖是從與含圖1中線A-A的豎直面相同的平面獲得視圖；字母“B”表示對應的附圖是從與含圖1中線B-B的豎直面相同的平面獲得視圖；而字母“C”表示對應的附圖是從與含圖1中線C-C的豎直面相同的平面獲得視圖。因此，數字後跟著字母“A”的圖顯示的是 源極/汲極區的剖面圖，數字後跟著字母“B”的圖顯示的是半導體鰭片26和上覆蓋的閘極中一者的剖面圖，而數字後跟著字母“C”的圖顯示的是位置不與半導體鰭片26相交的虛置閘極堆疊28的剖面圖。
圖2A、2B和2C示出從圖1獲得的剖面圖。接下來，參見圖3A、3B和3C，形成間隔物層38。間隔物層38或者可稱為第一間隔層，而對應的間隔物被稱為第一間隔物。對應的步驟如圖24的流程的步驟204所示。間隔物層38在隨後的形成接觸開口以形成源極/汲極矽化物和源極/汲極觸點中作為蝕刻停止層，因此也被被稱為蝕刻停止層。間隔物層38的材料被選定為對於氧化物(例如，如隨後形成的圖4A、4B和4C所示的模板介電區)具有高蝕刻選擇性。根據本揭露的一些實施例，間隔物層38包括碳氮化矽(SiCN)，同時也可以使用其他介電材料。間隔物層38可具有的厚度在約3nm至約10nm的範圍。
間隔物層38形成為共形層，因此覆蓋半導體鰭片26(圖3A)和閘極堆疊28(圖3B和3C)的頂表面和側壁。半導體鰭片26的側壁上的部分間隔物38被稱為鰭片間隔物，如圖3A所示，並且半導體鰭片26的側壁上的部分間隔物38此後也被稱為閘極間隔物。根據一些實施例，間隔物層38的厚度在約3nm至約10nm的範圍。
接下來，如圖4A、4B和4C所示，使用(例如)可流動的化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)形成模板介電區40。對應的步驟如圖24的流程圖的步驟206所示。根據一些實施例，模板介電區40可包括氧化矽。剩餘的模板介電區40的頂表面高於半導體鰭片26的頂表面以及閘極堆疊28的頂表面。然後，執行諸如化學機械拋光(CMP)的平坦化操作以弄平模板介電區40的頂表面。在所產生的結構中，模板介電區40的頂表面高於半導體鰭片26的頂表面，並可以與閘極堆疊28(以及上覆蓋的間隔物層38部分)的頂端對齊或高於閘極堆疊28(以及上覆蓋的間隔物層38部分)的頂端。
圖5A、5B和5C示出了模板介電區40的回蝕，例如，通過濕蝕刻。對應步驟如圖24的流程圖的步驟208所示。由於回蝕，如圖5A所示，模板介電區40的剩餘部分的頂表面大體上低於或與覆蓋半導體鰭片26的間隔物層38的部分的頂表面對齊。在圖5A中，間隔物38的頂部部分的頂表面可通過模板介電區40暴露。蝕刻選擇性(模板介電區40的蝕刻率與間隔物層38的蝕刻率的比例)較高，例如，高於約30。因此，在回蝕模板介電區40後，間隔物層38殘留。如圖5B和5C所示，直接位於半導體鰭片26(圖5B)上的模板介電區40部分被移除。另一方面，直接位於STI區22(圖5C)上的模板介電區40部分具有一些部分殘留。根據本揭露的一些實施例，殘留的模板介電區40的厚度T1範圍在約20nm至約80nm之間。
根據本揭露的一些實施例，在圖5A、5B和5C的處理步驟之後，執行如圖22A、22B和22C所示的處理步驟，並且間隔物層38所暴露的部分被被氧化。這樣，間隔物層38所暴露的部分被氧化為部分38_1(此後稱為經氧化的部分38_1)。對應步驟如圖24的流程圖的步驟209所示。步驟209的框以虛線表示以表明該步驟可以執行或跳過。間隔物層38中未暴露的部分38_2不被氧化。當間隔物層38由SiCN形成時，所產生的經氧化的部分38_1包括氧碳氮化矽(silicon oxycarbo-nitride,SiOCN)，其具有比未轉化的部分38_2低的k值。例如，SiCN所具有的k值在5.0至7.0之間，而SiOCN所具有的k值在4.5至5.0之間。經氧化的的部分38_1和未氧化的部分38_2的k值之差可大於約0.5，或大於約1.0。k值的降低導致有利地減少寄生電容。根據本揭露的一些實施例，使用爐退火(在含氧氣體中)、氧氣注入等執行間隔物層38的氧化，其中氧化使用箭頭表示。
在圖22A、22B和22C的處理步驟之後，執行圖6A、6B和6C的處理步驟。根據另外的實施例，在圖5A、5B和5C的處理步驟之後，過 程進行到圖6A、6B和6C所示的步驟，而省略圖22A、22B和22C所示的處理步驟。
在隨後的步驟中，如圖6B和6C所示，形成硬遮罩間隔物42。硬遮罩間隔物42或者可稱為第二間隔物或第二間隔物層。對應步驟如圖24的流程圖的步驟210所示。選擇硬遮罩間隔物42的材料，從而使得蝕刻選擇性(硬遮罩間隔物42的蝕刻率與間隔物層38的蝕刻率的比例)較高，例如，高於約30。例如，當間隔物層38由SiCN形成時，硬遮罩間隔物42可由具有不同於SiCN的蝕刻特性的氧碳氮化矽(silicon oxycarbo-nitride,SiOCN)形成。而且，SiOCN比SiCN更容易採用濕蝕刻移除。
根據一些示例性實施例，如圖6B和圖6C所示，硬遮罩間隔物42的形成包括毯式沉積共形硬遮罩層，並執行非等向蝕刻移除該硬遮罩層的水平部分。該硬遮罩層的剩餘部分是硬遮罩間隔物42，其在間隔物層38的側壁部分上形成。
如圖6C所示，間隔物層38中的一些部分埋在閘極堆疊28和模板介電區40之間。間隔物層38的底端38A接觸STI區22的頂表面。由於硬遮罩間隔物42在形成模板介電區40之後形成，所以底端42A高於模板介電區40的頂表面。因此，硬遮罩間隔物42的底端42A高於間隔物層38的底端38A，高度差等於模板介電區40的厚度T1，T1的範圍在約20nm至約80nm之間。
圖6A還示出了移除間隔物層38的頂部部分。間隔物層38的剩餘部分此後也被稱為(鰭片)間隔物38。在剖面圖中，鰭片間隔物具有U形(也包括L形)。
圖1至圖6C所示的處理流程示出了用在形成PMOS和NMOS裝置二者的流程，儘管PMOS裝置和NMOS裝置彼此物理上不同。在隨後示出的源極和汲極區的形成中，PMOS和NMOS採用單獨的處理步 驟。因此，如圖7A、7B和7C所示，當形成PMSO裝置的源極/汲極區時，NMOS被遮罩層44遮蔽。根據本揭露的一些示例性實施例，遮罩層44由SiN形成，也可以採用在圖8A至圖10C所示的步驟中不被蝕刻的其他材料。由於PMOS裝置和NMOS裝置被遮罩層44保護，處理步驟進行至圖8A至圖10C所示的步驟。當圖8A至圖10C所示的處理步驟完成了PMOS裝置或NMOS裝置，移除遮罩層44，並且所完成的裝置將被另一個遮罩層(未示出)覆蓋。然後對其他裝置重複圖8A至圖10C所示的處理步驟。
在圖7A、7B和7C所示的步驟之後，未被閘極堆疊28覆蓋的半導體鰭片26的端部分(參見圖1和圖7A)在蝕刻步驟被凹進。所產生的結構如圖8A、8B和8C所示。對應步驟如圖24的流程圖的步驟212所示。參見圖8A，由於移除了半導體鰭片26的端部分，形成凹槽46。間隔物層38和模板介電區40沒有被移除，因此界定了凹槽46。根據一些實施例，凹槽46的底部與間隔物層38的底表面大體上對齊。根據本揭露的其他實施例，凹槽46的底部高於或低於間隔物層38的底表面。
圖8B示出了移除了半導體鰭片26的端部分，留下由柵極堆疊28覆蓋的半導體鰭片26的中間部分。如圖8C所示，在形成凹槽46後，留下模板介電區40。
接下來，如圖9A所示，執行蝕刻步驟以移除暴露於凹槽46的間隔物38的側壁部分(38的鰭片間隔物)。該蝕刻可以是等向性使用(例如)濕蝕刻。這樣，凹槽46的橫向寬度增加超過圖8A所示的凹槽46。對應步驟如圖24的流程圖的步驟214所示。這有利地增加隨後在凹槽46中增長的源極/汲極區的寬度。圖9B和9C所示的結構分別類似於圖8B和8C所示的結構。
在隨後的步驟中，源極和汲極區(此後稱為源極/汲極區)在凹槽46中磊晶生長。所產生的結構如圖10A、10B和10C所示。對應步驟 如圖24的流程圖的步驟216所示。根據本揭露的一些實施例，源極/汲極區48的形成包括磊晶生長。當所產生的FinFET是n型FinFET時，源極/汲極區48包括矽磷(SiP)或磷摻雜的矽碳(SiCP)。當所產生的FinFET是p型FinFET時，源極/汲極區48包括SiGe，諸如硼或銦的p型摻雜可以在磊晶過程中原位摻雜(in-situ doped)。根據一些實施例，源極/汲極區48包括具有百分比不同的磷、鍺、碳等的下部48’和上部48”，這取決於源極/汲極區48是否屬於PMOS或NMOS裝置。適當的p型或n型雜質可以隨著磊晶的進行而原位摻雜，並且可(或可不)在磊晶後注入源極/汲極區48。
源極/汲極區48包括具有豎直壁的直部分。而且，在該直部分上可(或可不)存在源極/汲極區48的擴展部分。例如，圖21A至圖21F示出源極/汲極區48包括具有豎直壁48A的直部分和具有切面(facets)48B的擴展部分。根據另外的實施例，在源極/汲極區48不顯著的生長出凹槽46。因此，源極/汲極區48不具有擴展部分，並且所產生的源極/汲極區48類似於圖10A所示的源極/汲極區48。源極/汲極區48的寬度範圍在約6nm至約12nm之間。源極/汲極區48的高度範圍在約30nm至約80nm之間。
源極/汲極區48的形成過程中，模板介電區40用作模板以限定源極/汲極區48的形成，從而使得源極/汲極區48具有直的側壁，並且如果形成擴展部分的話，擴展部分被最小化。
圖11至圖16根據一些實施例示出了在先矽化物工藝(silicide-first process)中源極/汲極區、層間介電質(ILD)以及接觸插塞的形成。在先矽化物工藝中，源極/汲極區在ILD形成之前形成。圖11示出了圖10A所示的結構的一部分。接下來，執行蝕刻(例如幹蝕刻)以示出源極/汲極區48之間的模板介電區40，所產生的結構如圖12所示。對應步驟如圖24的流程圖的步驟218所示。在蝕刻步驟中，間隔 物38用作蝕刻停止層。由於間隔物38具有比模板介電區40高的蝕刻選擇性，間隔物38有效地保護下面的STI區22。
接下來，如圖13所示，執行矽化過程在源極/汲極區48的側壁上形成矽化物區50。對應步驟如圖24的流程圖的步驟220所示。根據本揭露的一些實施例，矽化物區包括矽化鎳、矽化鈦、矽化鈷等類似物。矽化物區50的厚度範圍在約2nm至約8nm之間。
接下來，如圖14所示，形成阻擋層51和ILD 52。然後執行CMP以平整ILD 52的頂表面。阻擋層51可由非晶矽形成。ILD 52可由FCVD氧化物形成，可以為氧化矽。根據另外的實施例，ILD 52由磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、摻氟矽玻璃(FSG)、原矽酸四乙酯(TEOS)等形成。然後執行退火，導致如圖15所示的結構。在退火期間，阻擋層51吸收ILD 52中的氧，從而轉變為氧化物。另一方面，矽化物區50被阻擋層51保護，免於被氧化。
在形成ILD 52後，形成替代閘極。第一，移除如圖10B和10C所示的虛置閘極堆疊28，形成如圖15所示的ILD 52中的開口。在移除虛置閘極堆疊28後留下的開口中形成替代閘極。所產生的結構如圖20所示。替代閘極56根據一些實施例包括介面層58、高k閘極介電質60以及閘極電極62。介面層58可由氧化矽形成。高k閘極介電質60可由k值大於約7.0的高k介電質形成且可包括金屬氧化物或鉿，鋁，鋯，鑭等的矽酸鹽。閘極電極62可包括由諸如TiN、TaN、TiAl、鈷和Al的材料形成的複數個層。
如圖16所示，在形成替代閘極56後，形成接觸插塞54。對應步驟如圖24的流程圖的步驟222所示。該形成過程包括在ILD52中形成接觸開口並用接觸插塞54填充該接觸開口。於是，完成了FinFET 70的形成。
圖17至圖20根據另外的實施例示出了在後矽化物工藝(silicide-last process)中源極/汲極矽化物區、ILD和接觸插塞的形成。在後矽化物工藝中，源極/汲極矽化物區在ILD形成之後形成，並通過接觸開口形成。圖17再次示出了圖10A所示的結構的一部分。接下來，參見圖18，在形成ILD52後，形成接觸蝕刻停止層(Contact Etch Stop Layer,CESL)68。CESL 68可由氮化矽或其他介電材料形成。CESL 68位於模板介電區40的剩餘部分上。此外，如圖20所示，CESL 68還在硬遮罩間隔物42的側壁上形成。而且，CESL 68包括覆蓋模板介電區40的部分，CESL 68的底表面68A接觸模板介電區40的頂表面。底表面68A也高於間隔物38的底端38A。在圖20中，CESL 68用虛線示出以表明當採用後矽化物工藝時可以形成，而在採用先矽化物工藝時可不形成。
在形成CESL 68和ILD 52後，形成替代閘極56，其中替代閘極56類似於圖20所述的替代閘極。
圖19A和圖19B根據一些實施例示出了從圖18所示的結構形成的接觸插塞54。如圖19A所示，接觸插塞54覆蓋並接觸剩餘的模板介電區40。在這些實施例中，在形成接觸開口的過程中，暴露於接觸開口的介電區40不被完全移除。圖19B示出了根據另外的實施例的結構，其中，移除暴露於接觸開口的整個模板介電區40，從而接觸插塞擴展至接觸間隔物38。還可存在其他剩餘的模板介電區40。
圖20示出了所產生的FinFET 70的剖面圖。該剖面圖是從包含圖1的線D-D的相同豎直平面獲得的。並且，為了簡便起見，儘管圖1示出了兩個鰭片26，但圖20示出單個鰭片26。能夠認識到，當間隔物38(圖3A至圖3C)、模板介電區40(圖4A至圖5C)、硬遮罩層42(圖6A至圖6C)以及CESL 68(圖18)形成時，這些特徵也同時在閘極堆疊28的左端側壁和右端側壁(參見圖1)上形成。因此，圖20示出了 間隔物38、模板介電區40、硬遮罩層42以及CESL 68的這些部分。
如圖20所示，間隔物38從替代閘極56的頂表面延伸至底表面，底表面38A在STI區22的頂表面上。模板介電區40形成為覆蓋STI區22。硬遮罩層42具有接觸模板介電區40的頂表面的底表面。硬遮罩層42的底表面42A還高於間隔物38的底表面/底端38A。CESL 68(如果形成了)的底表面68A還接觸板介電區40的頂表面，因此也高於間隔物38的底端38A。
根據一些實施例，FinFET 70的溝道鰭片高度FH在約30nm至約80nm的範圍之間。溝道鰭片寬度FW的可在約1nm至約12nm的範圍之間。間隔物38的厚度T2、硬遮罩層42的厚度T3以及CESL 68的厚度T4的每一者在約1nm至約10nm的範圍之間。間隔物高度差T1與鰭片高度FH之比在約0.6至約1之間的範圍。間隔物高度差T1與替代閘極56的高度MGH之比在約0.1至約0.3之間的範圍。
圖21A至圖21F根據各種實施例示出了源極/汲極矽化物區50和接觸插塞54的輪廓。圖21A、21B和21C示出了使用先矽化物工藝形成的矽化物區50和接觸插塞54。因此，由於當接觸開口形成時矽化物區50已經形成，接觸開口能夠形成的小。例如，在圖21A、21B和21C中，接觸插塞54小於包括兩個源極/汲極區48及它們之間的區域的組合區域。作為對照，在圖21D至圖21F中(後矽化物工藝)，接觸插塞54大於包括兩個源極/汲極區48及它們之間的區域的組合區域。這是由於在後矽化物方法中，接觸開口將足夠大從而使得矽化物區可在接觸開口中形成。
圖21A、21B、21D和21E示出了，在形成矽化物區50後，用於形成矽化物區50的剩餘金屬55沒有被移除。而且，圖21A和21D示出了金屬55被限於源極/汲極區48之間，而圖21B和圖21E示出金屬55擴展出了最外面的源極/汲極區48。圖21C示出了ILD 52保留在接觸插塞54 之下，而圖21F示出接觸插塞54一直延伸到間隔物38。
圖23根據一些實施例示出了FinFET 70的剖面圖。根據一些實施例，FinFET 70通過執行如圖22A、22B和22C所示的步驟(圖24的步驟209)而獲得。因此，所形成的硬遮罩層42包括經氧化的上部38_1和未氧化的下部38_2，下部38_2具有比氧化的上部38_1更高的k值。參見圖22C，經氧化的上部38_1和未氧化的下部38_2之間的交界面大體上與模板介電區40的頂表面對齊(例如，高度差小於約2nm)。根據另外的實施例，經氧化的上部38_1和未氧化的下部38_2之間的交界面低於模板介電區40的頂表面。
本揭露的實施例具有一些有利的特徵。通過形成介電區以作為源極/汲極磊晶的模板，所產生的源極/汲極區具有直的的側壁，從而矽化物區可在源極/汲極區的所有側壁和頂表面上更均勻地形成。於是減少了源極/汲極接觸電阻，增加FinFET的驅動電流。
根據本揭露的一些實施例，一種方法包括在半導體鰭片的中間部分形成閘極堆疊，並在該閘極堆疊的側壁上形成第一閘極間隔物。在形成該第一閘極間隔物後，形成模板介電區以覆蓋該半導體鰭片。該方法還包括凹進該模板介電區。在凹進之後，在該閘極堆疊的該側壁上形成第二閘極間隔物。蝕刻該半導體鰭片的端部分以在該模板介電區中形成凹槽。在該凹槽中磊晶地生長源極/汲極區。
根據本揭露另外的實施例，一種方法包括在半導體鰭片的中間部分形成閘極堆疊，並在該閘極堆疊的側壁上形成第一閘極間隔物。在形成該第一閘極間隔物後，形成模板介電區，該模板介電區的頂表面大體上與該半導體鰭片的頂表面對齊。蝕刻該半導體鰭片的端部分以在該模板介電區中形成凹槽。在該凹槽中磊晶地生長源極/汲極區。該方法還包括移除該模板介電區的至少一部分以暴露該源極/汲極區的側壁，以及矽化該源極/汲極區的該側壁。
根據本揭露另外的實施例，一種FinFET包括半導體鰭片、該半導體鰭片的側壁和頂表面上的閘極、從該閘極的頂表面延伸至底表面的第一閘極間隔物，以及從該閘極的該頂表面延伸至高於該閘極的該底表面的平面的第二閘極間隔物。
前面所述概括了幾個實施例的特徵，使得本領域技術人員可更好地理解本揭露的各個方面。本領域技術人員應該明白他們可以將本揭露當作基礎，用來設計或修改用於執行相同目的和/或獲得在此介紹的實施例的相同好處的其他過程和結構。本領域技術人員也可意識到這樣等同的構造並不脫離本揭露的精神和保護範圍，並且在不脫離本揭露的精神和保護範圍的情況下，他們可以在此做各種改變、替換和修改。
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Claims (10)

  1. 一種半導體結構的製造方法，其包括：在半導體鰭片的中間部分形成閘極堆疊；在該閘極堆疊的側壁上形成第一閘極間隔物；在形成該第一閘極間隔物後，形成模板介電區以覆蓋該半導體鰭片；凹進該模板介電區；在凹進之後，在該閘極堆疊的該側壁上形成第二閘極間隔物；蝕刻該半導體鰭片的端部分以在該模板介電區中形成凹槽；以及在該凹槽中磊晶地生長源極/汲極區。
  2. 如請求項1所述的方法，其中，該第一閘極間隔物和該第二閘極間隔物由不同的介電材料形成。
  3. 如請求項2所述的方法，其中，該第一閘極間隔物由碳氮化矽形成，而該第二閘極間隔物由氧碳氮化矽形成。
  4. 如請求項1所述的方法，還包括：當在該閘極堆疊的側壁上形成該第一閘極間隔物時，同時在該半導體鰭片的該端部分的側壁上形成鰭片間隔物；以及在該凹槽形成之後，進一步蝕刻該鰭片間隔物以擴展該凹槽，其中，該源極/汲極區在擴展的凹槽中生長。
  5. 如請求項1所述的方法，還包括：在凹進該模板介電區後，在該第一閘極間隔物上執行氧化，其中，該模板介電區上的該第一閘極間隔物的第一部分被氧化，而低於該模板介電區頂表面的該第一閘極間隔物的第二部分不被氧化。
  6. 一種半導體結構的製造方法，其包括：在半導體鰭片的中間部分形成閘極堆疊；在該閘極堆疊的側壁上形成第一閘極間隔物；在形成該第一閘極間隔物後，形成模板介電區，該模板介電區的頂表面大體上與該半導體鰭片的頂表面對齊；蝕刻該半導體鰭片的端部分以在該模板介電區中形成凹槽；在該凹槽中磊晶地生長源極/汲極區；移除該模板介電區的至少一部分以暴露該源極/汲極區的側壁；以及矽化該源極/汲極區的該側壁。
  7. 如請求項6所述的方法，其中，移除該模板介電區包括蝕刻該模板介電區直到暴露由該模板介電區覆蓋的介電層的一部分，且其中該介電層同時形成為該第一閘極間隔物。
  8. 如請求項6所述的方法，還包括：增加該模板介電區上的該第一閘極間隔物的第一部分的k值，而該模板介電區頂表面之下的該第一閘極間隔物的第二部分的k值保持不變。
  9. 一種半導體結構，其包括：鰭式場效電晶體(FinFET)，其包括：半導體鰭片；該半導體鰭片的側壁和頂表面上的閘極；第一閘極間隔物，其從該閘極的頂表面延伸至底表面；以及第二閘極間隔物，其從該閘極的該頂表面延伸至高於該閘極的該底表面的水平。
  10. 如請求項9所述的半導體結構，其中，該第一閘極間隔物包括上部和下部，該上部比該下部具有更多的含氧量。
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