CN115692202A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN115692202A
CN115692202A CN202211368785.9A CN202211368785A CN115692202A CN 115692202 A CN115692202 A CN 115692202A CN 202211368785 A CN202211368785 A CN 202211368785A CN 115692202 A CN115692202 A CN 115692202A
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gate
semiconductor device
gate structure
layer
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郭家铭
庄博仁
王俞仁
颜英伟
庄馥戎
萧雅茵
黄南元
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法，该制作半导体元件的方法为，先形成一栅极结构于基底上，然后形成一第一间隙壁于栅极结构旁，其中该第一间隙壁包含氮碳化硅。接着形成一第二间隙壁于第一间隙壁旁，其中该第二间隙壁包含氮碳氧化硅，随后再形成一源极/漏极区域于第二间隙壁两侧。

Description

半导体元件及其制作方法
本申请是中国发明专利申请(申请号：201810436649.6，申请日：2018年05月09日，发明名称：半导体元件及其制作方法)的分案申请。
技术领域
本发明涉及一种半导体元件及其制作方法，尤其是涉及一种金属栅极晶体管及其制作方法。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
然而，在现今金属栅极晶体管制作过程中，由于间隙壁与接触洞蚀刻停止层等元件通常均由具有较高介电常数的材料所构成，使栅极结构与源极/漏极区域之间的重叠电容值(capacitance overlap,Cov)无法控制在一优选的范围内，进而影响元件效能。因此如何改良现今制作工艺以解决上述问题即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法，其主要先形成一栅极结构于基底上，然后形成一第一间隙壁于栅极结构旁，其中该第一间隙壁包含氮碳化硅(SiCN)。接着形成一第二间隙壁于第一间隙壁旁，其中该第二间隙壁包含氮碳氧化硅(SiOCN)，随后再形成一源极/漏极区域于第二间隙壁两侧。
本发明另一实施例公开一种半导体元件，其主要包含一栅极结构于基底上；一第一间隙壁设于该栅极结构旁，其中该第一间隙壁包含氮碳化硅(SiCN)；一第二间隙壁设于第一间隙壁旁，其中第二间隙壁包含氮碳氧化硅(SiOCN)；以及一源极/漏极区域于第二间隙壁两侧。
附图说明
图1至图6为本发明优选实施例制作一半导体元件的方法示意图；
图7为本发明一实施例的半导体元件的结构示意图；
图8为本发明一实施例的半导体元件的结构示意图。
主要元件符号说明
12 基底 14 栅极结构
16 栅极介电层 18 高介电常数介电层
20 栅极材料层 22 硬掩模
24 间隙壁 26 间隙壁
28 间隙壁 30 轻掺杂漏极
32 间隙壁 34 源极/漏极区域
36 接触洞蚀刻停止层 38 层间介电层
40 功函数金属层 42 低阻抗金属层
44 接触插塞 46 金属栅极
48 金属栅极 50 金属栅极
具体实施方式
请参照图1至图6，图1至图6为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，然后于基底上形成至少一栅极结构14或虚置栅极。在本实施例中，栅极结构14的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的先高介电常数介电层制作工艺为例，可先依序形成一栅极介电层16或介质层、一高介电常数介电层18、一由多晶硅所构成的栅极材料层20以及一选择性硬掩模22于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模22、部分栅极材料层20、部分高介电常数介电层18以及部分栅极介电层16，然后剥除图案化光致抗蚀剂，以于基底12上形成由图案化的栅极介电层16、图案化的高介电常数介电层18、图案化的栅极材料层20以及图案化的硬掩模22所构成的栅极结构14。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层16可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层20可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模22可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
在本实施例中，高介电常数介电层18优选包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanateoxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafniumzirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(bariumstrontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂阱(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallow trench isolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面型晶体管例如鳍状结构晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后分别在栅极结构14侧壁形成至少一间隙壁，例如间隙壁24、间隙壁26以及间隙壁28。在本实施例中，间隙壁24、26、28的制作可先依序形成多个衬垫层(图未示)于基底12表面并覆盖栅极结构14，接着利用蚀刻去除部分衬垫层以于栅极结构14侧壁形成间隙壁24、间隙壁26以及间隙壁28。其中间隙壁24以及间隙壁26优选为L形而设于最外侧的间隙壁28则优选为一字形或I字形，且此阶段所形成的三个间隙壁24、26、28可统称为第一间隙壁。在本实施例中，直接接触栅极结构14的内侧间隙壁24优选包含氮碳化硅(silicon carbonnitride,SiCN)，设于中间且同时接触内侧间隙壁24以及外侧间隙壁28的间隙壁26优选包含氮碳氧化硅(silicon oxycarbonitride,SiOCN)，而设于外侧的间隙壁28则与间隙壁24同样包含氮碳化硅。
在本实施例中，各间隙壁24、26、28的厚度优选约介于10埃至30埃或更加约25埃，且最内侧的间隙壁24以及最外侧的间隙壁28的厚度优选大于10埃。需注意的是，本实施例所揭露的三个间隙壁24、26、28之间虽优选具有相同厚度，但不局限于此，依据本发明其他实施例间隙壁24、26、28之间又可依据产品需求具有相同及/或不同厚度。举例来说，依据本发明一实施例，内侧间隙壁24以及中间间隙壁26可具有相同厚度同时外侧间隙壁28的厚度在此阶段可大于各间隙壁24、26的厚度。
随后如图2所示，进行一轻掺杂离子注入，利用约930℃温度进行一快速升温退火制作工艺活化注入基底12的掺质，以于间隙壁28两侧的基底12中形成一轻掺杂漏极30。值得注意的是，本实施例在形成轻掺杂漏极30的过程中，最外侧的间隙壁28可能在形成轻掺杂漏极30时所伴随的清洗制作工艺(例如湿式清洗)中被一同去除，因此形成轻掺杂漏极30之后栅极侧壁14可能仅留下间隙壁24及间隙壁26，而原本为L形的中间间隙壁26在去除外侧间隙壁28后也优选改变为I字形。
随后图3所示，形成另一衬垫层(图未示)于基底12上并覆盖栅极结构14及间隙壁24、26，然后再利用蚀刻去除部分衬垫层，以于间隙壁26的侧壁形成另一间隙壁32或第二间隙壁。在本实施例中，间隙壁32优选与间隙壁24、26包含不同材料例如但不局限于氮化硅。接着于间隙壁32两侧的基底12中形成一源极/漏极区域34及/或外延层(图未示)，并选择性于源极/漏极区域34及/或外延层的表面形成一金属硅化物(图未示)。源极/漏极区域34与外延层可依据所置备晶体管的导电型式而包含不同掺质或不同材料，例如源极/漏极区域34可包含P型掺质或N型掺质，而外延层则可包含锗化硅、碳化硅或磷化硅。
如图4所示，然后形成一接触洞蚀刻停止层36于栅极结构14及基底12上，其中接触洞蚀刻停止层36可选任何具有应力的材料，例如可自由氮化硅以及氮碳化硅所构成的群组，但并不局限于此。接着形成一层间介电层38于接触洞蚀刻停止层36上，并进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺去除部分层间介电层38以及部分接触洞蚀刻停止层36，使硬掩模22上表面切齐剩余接触洞蚀刻停止层36以及层间介电层38上表面齐平。其中层间介电层38可由任何包含氧化物的绝缘材料所构成，例如四乙氧基硅烷(Tetraethyl orthosilicate,TEOS)，但不局限于此。
如图5所示，随后进行一金属栅极置换制作工艺将栅极结构14转换为金属栅极46。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除硬掩模22以及栅极结构14中的多晶硅材料20，以于层间介电层38中形成凹槽(图未示)。之后依序形成至少包含U形功函数金属层40与低阻抗金属层42的导电层于凹槽内，再搭配进行一平坦化制作工艺使U形功函数金属层40与低阻抗金属层42上表面与层间介电层38上表面齐平。
在本实施例中，功函数金属层40优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层40可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层40可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层40与低阻抗金属层42之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层42则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将栅极结构14或虚置栅极转换为金属栅极时此领域者所熟知技术，在此不另加赘述。
接着如图6所示，进行一接触插塞制作工艺，例如先形成多个接触洞(图未示)于层间介电层38与接触洞蚀刻停止层36中，然后于接触洞中填入所需的金属材料，包括依序形成一选自由钛(Ti)、氮化钛(TiN)、钽(Ta)及氮化钽(TaN)等群组所构成的阻障层以及一选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)及钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料所构成的金属层。随后搭配进行一平坦化制作工艺，例如以CMP去除部分阻障层与部分金属层以形成接触插塞44电连接基底12内的源极/漏极区域34。
请参照图7，图7为本发明一实施例的半导体元件的结构示意图，如图7所示，相较于前述实施例利用先高介电常数介电层制作工艺制作出图6的金属栅极晶体管，本发明又可依据后高介电常数介电层(high-k last)制作工艺来进行金属栅极置换制作工艺。在此情况下，所形成的金属栅极晶体管同样具有一由金属栅极48所构成的栅极结构14设于基底12上，其中金属栅极48优选包含一栅极介电层16或介质层、U形高介电常数介电层18设于栅极介电层16上、U形功函数金属层40以及低阻抗金属层42。由于先高介电常数介电层制作工艺或后高介电常数介电层制作工艺均为本领域所熟知技术，在此不另加赘述。
请参照图8，图8为本发明一实施例的半导体元件的结构示意图，如图8所示，相较于前述实施例于图2形成轻掺杂漏极30时去除最外侧的间隙壁28，本发明又可依据制作工艺需求在形成轻掺杂漏极30时保留原本的三层间隙壁24、26、28，如此进行后续图3至图5的制作工艺时栅极结构14侧壁便一共设有四层间隙壁，包括L形间隙壁24、L形间隙壁26、I形间隙壁28以及间隙壁32。本实施例的栅极结构14或金属栅极50虽以先高介电常数介电层制作工艺为例，但不局限于此，本发明又可将此实施例的复合式间隙壁结构结合前述图7依据后高介电常数介电层(high-k last)制作工艺所制备出的金属栅极，亦即可在图7的金属栅极48侧壁形成如本实施例般的四层间隙壁结构，此变化型也属本发明所涵盖的范围。
另外需注意的是，本实施例外侧的间隙壁28厚度在形成轻掺杂漏极30之前可选择等于或大于中间的间隙壁26厚度或内侧的间隙壁24厚度。依据本发明一实施例，若外侧的间隙壁28厚度在形成轻掺杂漏极30之前等于中间的间隙壁26厚度或内侧的间隙壁24厚度，则在形成轻掺杂漏极30后优选被完全去除而仅留下中间的间隙壁26于栅极结构14侧壁。
然而若外侧的间隙壁28厚度在形成轻掺杂漏极30之前大于中间的间隙壁26厚度或内侧的间隙壁24厚度，则在形成轻掺杂漏极30后外侧的间隙壁28厚度则优选大幅降低使其剩余厚度小于中间的间隙壁26或内侧的间隙壁24厚度，这些变化型均属本发明所涵盖的范围。
综上所述，本发明主要揭露一种应用于金属栅极晶体管的间隙壁结构，其中间隙壁结构可包含第一间隙壁以及第二间隙壁，而第一间隙壁又可依据制作工艺需求包含二层间隙壁结构或三层间隙壁结构。依据本发明一实施例，若第一间隙壁为二层间隙壁结构，内侧或紧邻栅极结构的间隙壁优选包含氮碳化硅而外侧的间隙壁则包含氮碳氧化硅。若第一间隙壁为三层间隙壁结构，内侧或紧邻栅极结构的间隙壁优选包含氮碳化硅，中间的间隙壁优选包含氮碳氧化硅，而外侧的间隙壁则与内侧间隙壁同样包含氮碳化硅。第二间隙壁在各种情况下均优选与第一间隙壁中的任何一部分包含不同材料，例如但不局限于氮化硅。依据本发明的优选实施例，第一间隙壁中内侧由氮碳化硅所构成的间隙壁可用来保护栅极结构中高介电常数介电层的品质，而外侧同样由氮碳化硅所构成的间隙壁则可用来维持轻掺杂漏极所形成的位置，进而提升元件的稳定性及效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作半导体元件的方法，包含：
形成栅极结构于基底上；
形成第一间隙壁于该栅极结构旁，其中该第一间隙壁包含氮碳化硅；
形成第二间隙壁于该第一间隙壁旁，其中该第二间隙壁包含氮碳氧化硅；
形成第三间隙壁于该第二间隙壁旁，其中该第三间隙壁直接接触该第一间隙壁和该第二间隙壁；以及
形成源极/漏极区域于该第三间隙壁两侧。
2.如权利要求1所述的方法，其中该第三间隙壁与该第一间隙壁和该第二间隙壁中的任何一部分包含不同材料。
3.如权利要求1所述的方法，其中该第三间隙壁和该栅极结构的上表面共平面，且该第三间隙壁不设置在该栅极结构的正上方。
4.如权利要求1所述的方法，其中该第三间隙壁包含氮化硅。
5.如权利要求1所述的方法，其中该第一间隙壁以及该第二间隙壁包含相同厚度。
6.如权利要求1所述的方法，其中该第一间隙壁以及该第二间隙壁包含不同厚度。
7.如权利要求1所述的方法，其中该第一间隙壁是L形。
8.如权利要求1所述的方法，其中该第二间隙壁是I形。
9.如权利要求1所述的方法，其中该第一间隙壁直接接触该第二间隙壁。
10.一种半导体元件，包含：
栅极结构，在基底上；
第一间隙壁，设于该栅极结构旁，其中该第一间隙壁包含氮碳化硅；
第二间隙壁，设于该第一间隙壁旁，其中该第二间隙壁包含氮碳氧化硅；
第三间隙壁，设于该第二间隙壁旁，其中该第三间隙壁直接接触该第一间隙壁和该第二间隙壁；以及
源极/漏极区域，在该第三间隙壁两侧。
11.如权利要求10所述的半导体元件，其中该第三间隙壁与该第一间隙壁和该第二间隙壁中的任何一部分包含不同材料。
12.如权利要求11所述的半导体元件，其中该第三间隙壁和该栅极结构的上表面共平面，且该第三间隙壁不设置在该栅极结构的正上方。
13.如权利要求10所述的半导体元件，其中该第三间隙壁包含氮化硅。
14.如权利要求10所述的半导体元件，其中该第一间隙壁以及该第二间隙壁包含相同厚度。
15.如权利要求10所述的半导体元件，其中该第一间隙壁以及该第二间隙壁包含不同厚度。
16.如权利要求10所述的半导体元件，其中该第一间隙壁是L形。
17.如权利要求10所述的半导体元件，其中该第二间隙壁是I形。
18.如权利要求10所述的半导体元件，其中该第一间隙壁直接接触该第二间隙壁。
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