CN105304490A - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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CN105304490A
CN105304490A CN201410352445.6A CN201410352445A CN105304490A CN 105304490 A CN105304490 A CN 105304490A CN 201410352445 A CN201410352445 A CN 201410352445A CN 105304490 A CN105304490 A CN 105304490A
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CN105304490B (zh
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简金城
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构的制作方法，至少包括以下步骤：首先，提供一基板，基板上的一第一区域包含有多个鳍状结构，并包含有一绝缘层位于该基板上，且位于各该鳍状结构之间，然后形成一第一材料层覆盖该鳍状结构以及该绝缘层，接着部分移除各该鳍状结构，以及形成至少一外延层于各该剩余的鳍状结构顶部。

Description

半导体结构的制作方法
技术领域
本发明涉及半导体制作工艺领域，尤其是涉及一种避免形成于鳍状结构上的外延层与相邻的其他外延层互相接触的制作流程。
背景技术
随着场效晶体管(fieldeffecttransistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)场效晶体管元件，例如多栅极场效晶体管(multi-gateMOSFET)元件及鳍式场效晶体管(finfieldeffecttransistor,FinFET)元件取代平面晶体管元件已成为目前的主流发展趋势。由于非平面晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的由源极引发的能带降低(draininducedbarrierlowering,DIBL)效应，并可以抑制短通道效应(shortchanneleffect,SCE)。此外，相较于平面式场效晶体管元件，非平面晶体管元件在同样的栅极长度下具有较宽的通道宽度，因而也可提供加倍的漏极驱动电流。
另一方面，目前业界也发展出所谓的「应变硅(strained-silicon)技术」，以进一步增加晶体管元件的载流子迁移率。举例来说，其中一种主流的应变硅技术是将硅锗(SiGe)或硅碳(SiC)等晶格常数(latticeconstant)不同于单晶硅(singlecrystalSi)的外延结构设置于半导体元件的源/漏极区域。由于硅锗外延结构及硅碳外延结构的晶格常数分别比单晶硅大及小，使得与外延结构相邻的载流子通道会感受到一外加应力，而产生了晶格以及带结构(bandstructure)的改变。在此情况之下，载流子迁移率以及相对应场效晶体管的速度均会有效提升。
然而，随着半导体元件的尺度不断减缩，即便同时采用非平面场效晶体管元件以及应变硅技术，仍无法解决所有的技术缺失。举例来说，两相邻的外延结构一般会因为外延过度成长之故而容易互相结合，因此如何排除外延结构的晶格缺陷即成为一重要课题。
发明内容
为解决上述问题，本发明提供一种半导体结构的制作方法，至少包括以下步骤：首先，提供一基板，基板上的一第一区域包含有多个鳍状结构，并包含有一绝缘层位于该基板上，且位于各该鳍状结构之间，然后形成一第一材料层覆盖该鳍状结构以及该绝缘层，接着部分移除各该鳍状结构，以及形成至少一外延层于各该剩余的鳍状结构顶部。
本发明特点在于，在制作过程中额外增加形成一光致抗蚀剂层的步骤，该光致抗蚀剂层的形成，可调节鳍状结构与绝缘层之间的高度比例，使得鳍状结构的顶面高度低于绝缘层的顶面高度，并由绝缘层与鳍状结构顶部共同定义出一凹槽，后续形成于鳍状结构顶部的外延层同时也位于该凹槽内，因此较不容易与相邻的其他外延层接触而互相影响。
附图说明
图1至图9为本发明的第一优选实施例的半导体结构的制作方法示意图；
图10为本发明半导体结构的立体图。
主要元件符号说明
10基底
10a表面
12鳍状结构
14绝缘层
16介电层
18光致抗蚀剂层
20光致抗蚀剂层
21凹槽
22凹槽
24外延层
26栅极结构
A第一区域
B第二区域
h1高度
h2高度
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所公开的范围，在此容先叙明。
图1至图9绘示了本发明的第一优选实施例的半导体结构的制作方法示意图。请参照图1，图1绘示了半导体结构于初始阶段的透视图。如图1所示，首先，提供一基底10，基底10上设置有多个鳍状结构12。基底10的表面10a可具有一预定晶面，且鳍状结构12的长轴轴向平行于一晶向。举例来说，对于一块硅基底而言，上述预定晶面可以是(100)晶面，且鳍状结构12可沿着〈110〉晶向延伸，但晶面与晶向不限于此。除了块硅基底之外，上述基底10也可例如是一含硅基底、一三五族半导体覆硅基底(例如GaAs-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或硅覆绝缘(silicon-on-insulator,SOI)基底、氧化硅基底(silicondioxide)、铝化硅基底(aluminumoxide),蓝宝石基底(sapphire)、含锗(germanium)基底或是硅锗合金基底(alloyofsiliconandgermanium)等半导体基底。
详细来说，鳍状结构12的制备方法可包括下列步骤，但不以此为限。举例来说，首先提供一块状基底(未绘示)，并在其上形成硬掩模层(未绘示)。接着利用光刻以及蚀刻制作工艺，将硬掩模层图案化，以定义出后续欲对应形成的鳍状结构12的位置。接着，进行一蚀刻制作工艺，将定义于硬掩模层内的图案转移至块状基底中，而形成所需的鳍状结构12。最后选择性地去除硬掩模层，便可获得如图1所示的结构。在此情况下，鳍状结构12可视为延伸出自基底10的一表面10a，且彼此间具有相同的成分组成，例如单晶硅。另一方面，当基底并非选自上述块状基底，而是选自于三五族半导体覆硅基底时，则鳍状结构的主要组成会与此基底的三五族半导体组成相同。
本实施例中，在各相邻的鳍状结构12之间均具有一绝缘层14，例如为一浅沟槽绝缘(shallowtrenchisolation,STI)结构，其可通过一浅沟槽绝缘制作工艺而制得。由于其详细形成方法为本领域技术人员所熟知，故不再赘述，但本发明不以此为限。接着，基底10上定义有一第一区域A以及一第二区域B，举例来说，第一区域可能为半导体元件的PMOS区域，第二区域B可能为半导体元件的NMOS区。A/B两区域在后续制作工艺中，将会分别在其内部形成外延层，为简化说明，本发明后续的制作流程图只到第一区域A内形成外延层为止。
接着，如图2～图4所示，在基底10上形成一图案化掩模层，其可包含绝缘或金属材料。例如先全面性覆盖一介电层16于第一区域A以及第二区域B的各鳍状结构12与绝缘层14上，介电层16例如为氧化硅、氮化硅或其他适合材料。然后如图3所示，覆盖一材料层，例如为一光致抗蚀剂层18于第二区域B内，因此光致抗蚀剂层仅保护第二区域B的介电层16。如图4所示，进行一蚀刻步骤，将第一区域A内的介电层16移除，由于第二区域B内的绝缘层16受到光致抗蚀剂层18的保护，因此仍然保留而不被移除。
接着请参考图5～图8，如图5所示，再全面性覆盖一材料层，优选形成一蚀刻速率相近于光致抗蚀剂层18的材料层，例如形成光致抗蚀剂层20于第一区域A以及第二区域B内，亦即光致抗蚀剂层20覆盖于第一区域A内的各鳍状结构12以及绝缘层14上，以及第二区域B内的光致抗蚀剂层18上。如图6所示，进行另一蚀刻步骤，此处选择对光致抗蚀剂层蚀刻速率较快的液体或是气体等，将第一区域A以及第二区域B内的部分光致抗蚀剂层18与部分光致抗蚀剂层20移除。更详细说明，由于第一区域A内的鳍状结构12主要被光致抗蚀剂层20所覆盖，因此在此蚀刻步骤之后，第一区域A内的鳍状结构12顶部已经被曝露出来，而第二区域B内的鳍状结构，由于还被介电层16所覆盖，因此在此步骤中不会被曝露出来。值得一提的是，本实施例中，光致抗蚀剂层18与光致抗蚀剂层20的材料可能相同或不同，但无论是光致抗蚀剂层18或是光致抗蚀剂层20，其与介电层16都有明显的蚀刻选择比，上述明显蚀刻选择比的意思，至少满足当进行蚀刻步骤并曝露出第一区域A内的鳍状结构12顶部时，第二区域B内的介电层16依然会覆盖于第二区域B内的鳍状结构12上，也许仅会受到些微的蚀刻影响，但并不会使第二区域B内部的鳍状结构12顶部被曝露。
如图7～图8所示，在第一区域A内的各绝缘层14上覆盖有材料层(亦即光致抗蚀剂层20)的情况下，进行一蚀刻步骤，将第一区域A内曝露的鳍状结构12部分移除，此时由于鳍状结构12的顶面较绝缘层14以及光致抗蚀剂层20的顶面低，因而由鳍状结构12的顶面与绝缘层14、光致抗蚀剂层20的侧壁共同定义出一凹槽21。接着再如图8所示，将第一区域A以及第二区域B内的光致抗蚀剂层18与光致抗蚀剂层20同时移除，以本实施例来说，由于光致抗蚀剂层18与光致抗蚀剂层20都属于光致抗蚀剂，因此可通过一剥除(strip)步骤或是一灰化(ash)步骤同时移除。值得注意的是，第一区域A内的鳍状结构12高度缩短后，其顶面高度h1比起绝缘层14的高度h2更低，因此由鳍状结构12的顶部与绝缘层14的侧边共同在第一区域A内定义出多个凹槽22。
最后，如图9所示，进行一外延成长制作工艺，形成一外延层24于各凹槽22内，其中，上述外延成长制作工艺可例如是一分子束外延制作工艺(molecularbeamepitaxy,MBE)、一共流外延成长制作工艺(co-flowepitaxialgrowthprocess)、一循环选择性外延成长制作工艺(cyclicselectiveepitaxialgrowthprocess)或其他类似的外延制作工艺。由于外延层24沿着凹槽22内部生长，当外延层24超过绝缘层14的高度时，才开始朝向上方以及两侧生长，因此本发明的第一区域A内，具有由鳍状结构12与绝缘层14共同定义的凹槽，导致外延层24会有部分被限制于凹槽22内，可避免外延层24过度生长，造成外延层与相邻的其他外延层互相接触，影响半导体元件的效能。
本发明还可应用于晶体管制作上，如图10，其绘示本发明半导体结构的立体图。图10可对应到图7的第一区域A。如图10所示，本发明还可配合一栅极制作工艺，形成至少一栅极结构26跨越鳍状结构12而形成一晶体管结构，本发明的特征在于，当图6所示的鳍状结构12被部分移除时，在绝缘层14表面上，仍有光致抗蚀剂层20，换句话说，光致抗蚀剂层20仍覆盖在除了栅极结构26所在区域之外的绝缘层14表面上。接着将光致抗蚀剂层20移除之后，才于凹槽22内形成外延层24(最终结构如图9所示)。此外，本实施例中，以先形成鳍状结构12与栅极结构26，接着移除未被栅极结构覆盖的鳍状结构后，才形成外延层24为例，因此被栅极结构26跨越覆盖的鳍状结构12并不会生长外延层24。但是本发明的栅极结构也可能在外延层24完成之后才形成，也属于本发明的涵盖范围内。
另外，值得注意的是，在上述图5～图8的步骤中，将光致抗蚀剂层20形成于第二区域B内的光致抗蚀剂层18上，但在本发明的另外一优选实施例中，可以在形成光致抗蚀剂层20之前，先移除光致抗蚀剂层18，之后才形成光致抗蚀剂层20于第一区域A与第二区域B内。亦即光致抗蚀剂层20覆盖于第一区域A内的各鳍状结构12以及绝缘层14上，以及第二区域B内的介电层16上，该制成步骤也属于本发明的涵盖范围内，其他制作的细节与上述第一优选实施例相同，在此不另外赘述。
本发明比起现有制作具有外延层的鳍状半导体结构，差别在于在图案化光致抗蚀剂层18之后，还多形成一材料层，例如光致抗蚀剂层20，而此光致抗蚀剂层20的存在，即用以保护第一区域A内的绝缘层14不受蚀刻，进而能调节鳍状结构12与绝缘层之间的高度差，换句话说，若无光致抗蚀剂层20存在，在蚀刻移除第一区域A内的部分鳍状结构12时，也容易一并蚀刻鳍状结构12两旁的绝缘层14，因此造成鳍状结构12与绝缘层14的高度一起降低，无法形成上述本发明图8所示的凹槽22，甚至鳍状结构的高度可能会比绝缘层的高度来得高，因此，后续形成的外延层，就会沿着鳍状结构的顶部以及两侧壁生长，如此，少了凹槽限制外延层的生长，外延层将更有可能接触到两侧相邻的其他外延层，并影响半导体元件的效能。而本发明因为鳍状结构被“埋”在绝缘层内，因此外延层将不会沿着鳍状结构的两侧壁生长，而仅从鳍状结构的顶端开始生长。
综上所述，本发明特征在于，在制作过程中额外增加形成一光致抗蚀剂层的步骤，该光致抗蚀剂层的形成，可调节鳍状结构与绝缘层之间的高度比例，使得鳍状结构的顶面高度低于绝缘层的顶面高度，并由绝缘层与鳍状结构顶部共同定义出一凹槽，后续形成于鳍状结构顶部的外延层同时也位于该凹槽内，因此相较于直接在鳍状结构的顶部与两侧生长外延层，本发明的流程所生长的外延层较不容易与相邻的其他外延层接触而影响半导体结构的效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (11)

1.一种半导体结构的制作方法，至少包含以下步骤：
提供一基板，基板上的一第一区域包含有多个鳍状结构，并包含有一绝缘层位于该基板上，且位于各该鳍状结构之间；
形成一第一材料层位于该绝缘层上，并同时曝露部分该鳍状结构；
部分移除各该鳍状结构；以及
分别形成一外延层于各该剩余的鳍状结构顶部。
2.如权利要求1所述的制作方法，其中在覆盖该第一材料层之后，还包含进行一回蚀刻步骤将该鳍状结构顶部曝露出来。
3.如权利要求1所述的制作方法，其中还包含一第二区域，并包含有多个鳍状结构，以及一绝缘层位于该基板上，且位于各该鳍状结构之间。
4.如权利要求3所述的制作方法，其中还包含形成一掩模层覆盖该第一区域与该第二区域的该鳍状结构以及该绝缘层。
5.如权利要求4所述的制作方法，其中还包含形成一第二材料层，位于该掩模层上。
6.如权利要求5所述的制作方法，其中还包含移除该第一区域内的该掩模层。
7.如权利要求1所述的制作方法，其中在部分移除各该鳍状结构之后，还包括移除该第一区域内的该第一材料层。
8.如权利要求1所述的制作方法，其中在移除部分该鳍状结构之后，该鳍状结构顶部比该绝缘层顶部更低，并由该材料层、该绝缘层与该鳍状结构顶部定义出一凹槽。
9.如权利要求8所述的制作方法，其中各该外延层均有部分形成于该凹槽内。
10.如权利要求1所述的制作方法，其中两相邻的该外延层不互相接触。
11.如权利要求1所述的制作方法，其中当各该鳍状结构被部分移除时，该绝缘层上还存在有该第一材料层。
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